CN103325696A - 晶圆级半导体封装件的制法及其晶圆级封装基板的制法 - Google Patents

晶圆级半导体封装件的制法及其晶圆级封装基板的制法 Download PDF

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CN103325696A
CN103325696A CN2012100976804A CN201210097680A CN103325696A CN 103325696 A CN103325696 A CN 103325696A CN 2012100976804 A CN2012100976804 A CN 2012100976804A CN 201210097680 A CN201210097680 A CN 201210097680A CN 103325696 A CN103325696 A CN 103325696A
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layer
making
dielectric layer
wafer
level
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CN103325696B (zh
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程吕义
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种晶圆级半导体封装件的制法及其晶圆级封装基板的制法，该晶圆级半导体封装件的制法包括：形成第一介电层于一承载板上，且外露部分承载板；形成线路层于该第一介电层与该第一开孔上；形成第二介电层于该第一介电层与该线路层上，且外露部分线路层；形成导电凸块于该第二开孔中；结合半导体组件于该导电凸块上；以封装胶体包覆该半导体组件；以及移除该承载板，以露出该线路层。借由先制作线路层，待侦测该线路层的良率后，再置放该半导体组件，以避免将良好的半导体组件与封装件一同作废，所以可节省制作成本及提高良率。

Description

晶圆级半导体封装件的制法及其晶圆级封装基板的制法
技术领域
本发明涉及一种半导体封装件的制法，特别是关于一种提升精度的晶圆级半导体封装件的制法及其晶圆级封装基板的制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。为了满足半导体封装件微型化(miniaturization)的封装需求，发展出晶圆级封装(Wafer Level Packaging，WLP)的技术。
第6452265号美国专利与第7202107号美国专利提供一种晶圆级封装的制法。请参阅图1A至图1E，其为现有晶圆级半导体封装件1的制法的剖面示意图。
如图1A所示，形成一热化离型胶层(thermal release tape)11于一承载板10上。
如图1B所示，置放多个半导体组件12于该热化离型胶层11上，该些半导体组件12具有相对的作用面12a与非作用面12b，各该作用面12a上均具有多个电极垫120，且各该作用面12a结合于该热化离型胶层11上。
如图1C所示，以模压(molding)方式形成一封装胶体13于该半导体组件12与该热化离型胶层11上。
如图1D所示，移除该热化离型胶层11与该承载板10，以外露该半导体组件12的作用面12a。
如图1E所示，进行重布线路层(Redistribution layer，RDL)及凸块(Bump)的工艺，即形成一线路结构14于该封装胶体13与该半导体组件12的作用面12a上，令该线路结构14电性连接该半导体组件12的电极垫120。
然而，现有半导体封装件1的制法中，该热化离型胶层11具有挠性，其于模压工艺中的热膨胀系数(Coefficient of thermal expansion，CTE)及受封装胶体13的侧推力将影响半导体组件12(如芯片)固定的精度，因而当进行重新排列的承载板10尺寸越大时，各该半导体组件12间的位置公差也随之加大，造成该RDL及Bump工艺的良率损失。
此外，现有的制法中，先形成该封装胶体13封装该半导体组件12，再进行RDL工艺，若于后续测试中，侦测该线路结构14的良率不佳时，需将半导体封装件1整体作废，也就是一并将良好的半导体组件12作废，所以现有工艺容易浪费材料，也就是丢弃良好的半导体组件12，致使成本提高，因而完全不符合经济效益。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺点，本发明的主要目的在于提供一种晶圆级半导体封装件的制法及其晶圆级封装基板的制法，以避免将良好的半导体组件与封装件一同作废，所以可节省制作成本及提高良率。
本发明的晶圆级封装基板的制法，其包括：形成第一介电层于一承载板上，且该第一介电层形成有多个第一开孔以外露该承载板的部分表面；形成线路层于该第一介电层的部分表面与该第一开孔上；形成第二介电层于该第一介电层的部分表面与该线路层上，且该第二介电层形成有多个第二开孔以外露该线路层的部分表面；以及形成导电凸块于该第二开孔中的线路层上，以电性连接该线路层。
前述的封装基板的制法中，还可包括移除该承载板，以露出该线路层。
本发明还提供一种晶圆级半导体封装件的制法，其包括：提供一承载封装基板的承载板，该封装基板包含有结合于该承载板上的第一介电层及设于该第一介电层上的第二介电层，该第一介电层上形成有线路层，且该线路层也结合于该承载板上，而该第二介电层上形成有导电凸块，以电性连接该线路层；结合半导体组件于该导电凸块上，该半导体组件具有结合至该导电凸块上的作用面与相对该作用面的非作用面；形成封装胶体于该第二介电层上，以包覆该半导体组件；以及移除该承载板，以露出该线路层。
前述的封装件的制法中，该半导体组件的作用面上可具有导电部，以借由点胶工艺或回焊工艺，可将焊锡或胶材电性连接至该导电凸块上。
前述的封装件的制法中，该半导体组件为单一芯片或堆栈芯片组结构。
前述的封装件的制法中，该封装胶体可外露该半导体组件的非作用面。
前述的封装件的制法还可包括研磨该封装胶体，以薄化其厚度。
前述的封装件的制法中，还可包括于形成封装胶体的前，可形成底胶于该半导体组件与该第二介电层之间。
前述的封装件的制法中，还可包括切单工艺。
前述的两种制法中，形成该第一与第二介电层的材质为亚聚酰胺(Polyimide，PI)、苯并环丁烯(Benezocy-clobutene，BCB)、聚苯并噁唑(Polybenzoxazole，PBO)、二氧化硅或氮化硅。
前述的两种制法中，该承载板可为硅晶圆、玻璃板、表面具铝层的板体或铝板；较佳地，可为表面具铝层的硅晶圆。
前述的两种制法中，形成该线路层的工艺可包括：形成一金属层于该第一介电层的全部表面与该第一开孔上；形成阻层于该金属层上，且该阻层形成有多个开口以外露该金属层的部分表面；形成该线路层于该些开口中的金属层上；以及移除该阻层及其下的金属层。
前述的两种制法中形成该导电凸块的工艺可包括：形成一金属层于该第二介电层的全部表面与该第二开孔上；形成阻层于该金属层上，且该阻层形成有多个开口以外露该金属层的部分表面；形成该导电凸块于该些开口中的金属层上；以及移除该阻层及其下的金属层。
前述的两种制法中，该导电凸块可含有焊锡材料，并回焊该导电凸块。
前述的两种制法中，还可包括形成线路增层结构于该第一介电层与该第二介电层之间，且电性连接该线路层与该导电凸块。
前述的两种制法中，可借由研磨工艺或蚀刻工艺，移除该承载板。
另外，前述的两种制法中，还可包括于移除该承载板之后，形成导电组件于该露出的线路层上。
由上可知，本发明晶圆级半导体封装件的制法及其晶圆级封装基板的制法，借由先制作线路层，再移除该承载板，所以于移除该承载板之后无需再进行RDL工艺。因此，相比于现有技术，本发明于制作线路层时，可避免热化离型胶层的热膨胀系数及挠性影响半导体组件固定的精度，因而当进行重新排列的承载板尺寸越大时，各该半导体组件间的位置公差不会随的加大，所以可精确控制半导体组件重新排列的精度。
此外，本发明的制法通过先制作线路层，再置放半导体组件，所以可先侦测该线路层的良率，待测试完成后，再置放该半导体组件，因而必要时只需将半成品作废，而不需将半导体组件作废。因此，相比于现有技术，本发明的制法不会浪费材料，也就是不会丢弃良好的半导体组件，因而有效降低成本，以符合经济效益。
附图说明
图1A至图1E为现有晶圆级半导体封装件的制法的剖面示意图；以及
图2A至图2K为本发明的晶圆级半导体封装件的制法的剖面示意图；其中，图2G’为图2G的另一实施例，图2K’及图2K”为图2K的不同实施例；以及
图2A至图2H’为本发明的晶圆级封装基板的制法的剖面示意图；其中，图2H”为图2H’的另一实施例。
主要组件符号说明
1，2，2’，2”        半导体封装件
10，20                承载板
11                    热化离型胶层
12，28                半导体组件
12a，28a              作用面
12b，28b              非作用面
120，280              电极垫
13，29b，29b’，29b”    封装胶体
14                       线路结构
2a，2a’                 封装基板
21，21’                 第一介电层
21a                      第一表面
21b                      第二表面
210，210’               第一开孔
22                       第一金属层
23a，23b                 阻层
230a，230b               开口
24                       线路层
24a                      线路增层结构
240                      增层介电层
241                      增层线路层
25，25’                 第二介电层
250，250’               第二开孔
26                       第二金属层
27                       导电凸块
27’                     焊接点
280a                     导电部
280b                     焊锡或胶材
29a                      底胶
30                       导电组件。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2K，其为本发明的晶圆级半导体封装件2的制法的剖面示意图。
如图2A所示，以涂布方式形成一第一介电层21于一承载板20上，且进行图案化工艺，于该第一介电层21上形成多个第一开孔210，以外露该承载板20的部分表面。
于本实施例中，形成该第一介电层21的材质为亚聚酰胺(Polyimide，PI)、苯并环丁烯(Benezocy-clobutene，BCB)或聚苯并噁唑(Polybenzoxazole，PBO)，且该承载板20为硅晶圆、玻璃板、表面具铝层的板体或铝板，较佳为表面具溅镀铝层的硅晶圆，但该承载板20的种类仅需为刚性材质即可，并不限于上述。
如图2B所示，以溅镀方式形成一第一金属层22于该第一介电层21的全部表面与该第一开孔210上。
接着，以涂布方式形成如光阻的阻层23a于该第一金属层22上，且以曝光、显影方式进行图案化工艺，于该阻层23a上形成多个开口230a，以外露该第一金属层22的部分表面与该些第一开孔210中的第一金属层22。
于本实施例中，该第一金属层22可作为供电镀用的导电层(seedlayer)，且形成该第一金属层22的材质为Ti、Cu、Ni、V、Al、W、Au或其组成，但不限于此。
如图2C所示，利用该第一金属层22作为电流路径，电镀形成线路层24于该些开口230a中的第一金属层22上。
于本实施例中，形成该线路层24的材质可为铜(Cu)或铝(Al)等，但不限于此。
如图2D所示，剥除该阻层23a，且以蚀刻方式将该阻层23a下方的第一金属层22移除。
如图2E所示，以涂布方式形成第二介电层25于该第一介电层21的部分表面与该线路层24上，且以曝光、显影方式进行图案化工艺，于该第二介电层25上形成多个第二开孔250，以外露该线路层24的部分表面。
接着，以溅镀方式形成第二金属层26于该第二介电层25的全部表面与该第二开孔250上。
于本实施例中，形成该第二介电层25的材质为亚聚酰胺(Polyimide，PI)、苯并环丁烯(Benezocy-clobutene，BCB)或聚苯并噁唑(Polybenzoxazole，PBO)，且形成该第二金属层26的材质为Ti、Cu、Ni、V、Al、W、Au或其组成，但该第二金属层26的材质不限于此。
如图2F所示，以涂布方式形成如光阻的另一阻层23b于该第二金属层26上，且以曝光、显影方式进行图案化工艺，于该另一阻层23b上形成多个开口230b，以外露该第二开孔250上及其周围的第二金属层26的表面。
接着，利用该第二金属层26作为电镀用的电流途径，以电镀形成导电凸块27于该些开口230b中的第二金属层26上，令该导电凸块27电性连接该线路层24。
于本实施例中，该导电凸块27含有焊锡材料，如锡银(Sn-Ag)无铅焊料，且该焊锡材料中也可含有Cu、Ni或Ge等，但该导电凸块27的材质无特别限制。又该第二金属层26也作为凸块底下金属(UnderBump Metallurgy，UBM)。
如图2G所示，剥除该另一阻层23b，且以蚀刻方式将该另一阻层23b下方的第二金属层26移除。接着，回焊该导电凸块27。
如图2G’所示，于另一实施例中，该第一与第二介电层21’，25’可为二氧化硅(SiO2)或氮化硅(silicon nitrate)，并以电浆辅助化学气相沉积(Plasma-Enhanced Chemical Vapor Deposition，PECVD)的方式形成，且以干蚀刻方式形成第一与第二开孔210’，250’。
此外，若该承载板20为铝板或表面为溅镀铝层的硅晶圆，即可进行电测，以得到该线路层24与导电凸块27的良率。因此，若侦测该线路层24与导电凸块27的良率不佳时，即可将该半成品(即该承载板20及其上的结构)作废，而不须进行后续的置晶与封装工艺，所以本发明的制法可有效控管品质，以避免丢弃良好的半导体组件。
如图2H所示，接续图2G的工艺，结合一半导体组件28于该导电凸块27上，该半导体组件28具有结合至该导电凸块27上的作用面28a与相对该作用面28a的非作用面28b。
于本实施例中，该半导体组件28上具有用以结合铜导电部280a的电极垫280，且可选择性地于该导电部280a上形成焊锡或胶材280b，如：非导电焊膏(Non Conductive Paste，NCP)或异方性导电膜(anisotropic conductive film，ACF)等方式，以借由回焊工艺或点胶工艺，将导电部280a精准对位结合且电性连接于该导电凸块27，以形成焊接点27’，令该半导体组件28固设于该第二介电层25上，如图2I所示。
此外，该半导体组件28为单一芯片；而于其它实施例中，该半导体组件可为堆栈芯片组结构。
再者，如图2H’所示，也是接续图2G的工艺，移除该承载板20，以露出该第一金属层22，以形成一晶圆级封装基板2a。例如：若该承载板20为硅晶圆，可先借由研磨工艺移除该承载板20至一定的薄度后，再以干蚀刻及化学机械研磨(Chemical Mechanical Polishing，CMP)的方式，移除剩余的承载板20。
另外，如图2H”所示，也可于图2D的工艺后，形成线路增层结构24a于该第一介电层21的部分表面与该线路层24上，再形成第二介电层25于该线路增层结构24a上。
于本实施例中，该线路增层结构24a具有至少一增层介电层240与形成于该增层介电层240上的增层线路层241，且该增层线路层241电性连接该线路层24与该导电凸块27。
如图2I所示，接续图2H的工艺，形成底胶29a于该半导体组件28与该第二介电层25之间，再形成封装胶体29b于该第二介电层25上，以包覆该半导体组件28与底胶29a。
如图2J所示，研磨该封装胶体29b，以薄化其厚度或印字。
接着，移除该承载板20，以露出该第一金属层22。例如：若该承载板20为硅晶圆，可先借由研磨工艺移除该承载板20至一定的薄度后，再以干蚀刻及化学机械研磨(Chemical Mechanical Polishing，CMP)的方式，移除剩余的承载板20。
如图2K所示，形成导电组件30于该露出的第一金属层22上，令该第一金属层22作为凸块底下金属(Under Bump Metallurgy，UBM)。之后，再进行切单工艺。
于本实施例中，该导电组件30可为焊球、凸块或导针等，并无特别限制。
此外，若接续图2G’的工艺，将形成如图2K’所示的半导体封装件2’。
此外，也可接续图2H”的工艺，以形成具有该线路增层结构24a的半导体封装件(图略)。
另外，若于模压工艺中可克服气洞问题，即可省略形成底胶29a的工艺，直接形成封装胶体29b’，如图2K’所示。或者，于研磨工艺中，可依厚度需求研磨该封装胶体29b’，如图2K”所示的半导体封装件2”，令该封装胶体29b’的顶面与该半导体组件28的非作用面28b齐平，使该封装胶体29b’外露该半导体组件28的非作用面28b，以增加散热效果。
本发明的制法于移除该承载板20之后无需再制作线路层24，也就是先制作线路层24，再进行后续作业，如：形成封装胶体29b，29b’，29b”，所以该封装胶体29b，29b’，29b”的热膨胀系数不可能影响半导体组件28固定的精度，因而免去半导体组件28重复经RDL工艺的热效应影响。因此，当进行重新排列的承载板20尺寸越大时，各该半导体组件28间的位置公差不会随的加大，所以可精确控制半导体组件28重新排列的精度。例如：当半导体组件28表面的电极垫280间距为40um时，也可在12寸晶圆(承载板20)的作业面积内精准对位其固定位置，而不受热化离型胶层的热膨胀系数及挠性的影响，不仅可大幅提高良率，且可节省成本。
此外，本发明的制法中，先制作线路层24，再置放该半导体组件28，所以可先侦测该线路层24的良率，待测试完成后，再置放该半导体组件28。若该线路层24的良率不佳时，只需将半成品作废，不需将半导体组件28作废。因此，本发明的制法不会浪费材料，也就是不会丢弃良好的半导体组件28，所以可节省制作成本。
此外，若该承载板20的表面为导体，以于制作线路层24与导电凸块27完成后，即可直接进行电测(不需外接其它电子装置)，以确定得到良品后，再置放该半导体组件28，所以不仅可大幅提高良率，且可节省制作的时间成本。
综上所述，本发明的晶圆级半导体封装件的制法及其晶圆级封装基板的制法，借由半导体组件上的导电部精准对位导电凸块后，经封装胶体固定后，再移除该承载板，所以不会受热化离型胶层影响半导体组件固定的精度，不仅有效提高良率，且可节省成本。
此外，借由先制作线路层，以于侦测该线路层的良率之后，再置放该半导体组件，因而避免将良好的半导体组件与封装件一同作废，所以可节省制作成本及提高良率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种晶圆级封装基板的制法，其包括：
形成第一介电层于一承载板上，且该第一介电层形成有多个第一开孔以外露该承载板的部分表面；
形成线路层于该第一介电层的部分表面与该第一开孔上；
形成第二介电层于该第一介电层的部分表面与该线路层上，且该第二介电层形成有多个第二开孔以外露该线路层的部分表面；以及
形成导电凸块于该第二开孔中的线路层上，以电性连接该线路层。
2.根据权利要求1所述的晶圆级封装基板的制法，其特征在于，该承载板为表面具铝层的硅晶圆。
3.根据权利要求1所述的晶圆级封装基板的制法，其特征在于，形成该线路层的工艺包括：
形成一金属层于该第一介电层的全部表面与该第一开孔上；
形成阻层于该金属层上，且该阻层形成有多个开口以外露该金属层的部分表面；
形成该线路层于该些开口中的金属层上；以及
移除该阻层及其下的金属层。
4.根据权利要求1所述的晶圆级封装基板的制法，其特征在于，形成该导电凸块的工艺包括：
形成一金属层于该第二介电层的全部表面与该第二开孔上；
形成阻层于该金属层上，且该阻层形成有多个开口以外露该金属层的部分表面；
形成该导电凸块于该些开口中的金属层上；以及
移除该阻层及其下的金属层。
5.根据权利要求1所述的晶圆级封装基板的制法，其特征在于，该制法还包括移除该承载板，以露出该线路层。
6.根据权利要求5所述的晶圆级封装基板的制法，其特征在于，是借由研磨工艺或蚀刻工艺，移除该承载板。
7.根据权利要求5所述的晶圆级封装基板的制法，其特征在于，该制法包括于移除该承载板之后，形成导电组件于该露出的线路层上。
8.根据权利要求1所述的晶圆级封装基板的制法，其特征在于，该制法包括形成该线路层之后，先形成线路增层结构于该第一介电层的部分表面与该线路层上，再形成该第二介电层于该线路增层结构上，使该线路增层结构电性连接该导电凸块与该线路层。
9.一种晶圆级半导体封装件的制法，包括：
提供一承载封装基板的承载板，该封装基板包含有结合于该承载板上的第一介电层及设于该第一介电层上的第二介电层，该第一介电层上形成有线路层，且该线路层还结合于该承载板上，而该第二介电层上形成有导电凸块，以电性连接该线路层；
结合半导体组件于该导电凸块上，该半导体组件具有结合至该导电凸块上的作用面与相对该作用面的非作用面；
形成封装胶体于该第二介电层上，以包覆该半导体组件；以及
移除该承载板，以露出该线路层。
10.根据权利要求9所述的晶圆级半导体封装件的制法，其特征在于，该承载板为表面具铝层的硅晶圆。
11.根据权利要求9所述的晶圆级半导体封装件的制法，其特征在于，形成该线路层的工艺包括：
形成一金属层于该第一介电层的全部表面与该第一开孔上；
形成阻层于该金属层上，且该阻层形成有多个开口以外露该金属层的部分表面；
形成该线路层于该些开口中的金属层上；以及
移除该阻层及其下的金属层。
12.根据权利要求9所述的晶圆级半导体封装件的制法，其特征在于，形成该导电凸块的工艺包括：
形成一金属层于该第二介电层的全部表面与该第二开孔上；
形成阻层于该金属层上，且该阻层形成有多个开口以外露该金属层的部分表面；
形成该导电凸块于该些开口中的金属层上；以及
移除该阻层及其下的金属层。
13.根据权利要求9所述的晶圆级半导体封装件的制法，其特征在于，该封装基板还包含有线路增层结构，形成于该第一介电层与该第二介电层之间，且电性连接该线路层与该导电凸块。
14.根据权利要求9所述的晶圆级半导体封装件的制法，其特征在于，该半导体组件的作用面上具有导电部，以借由焊锡或胶材电性连接至该导电凸块上。
15.根据权利要求14所述的晶圆级半导体封装件的制法，其特征在于，该半导体组件借由点胶工艺或回焊工艺结合至该导电凸块上。
16.根据权利要求9所述的晶圆级半导体封装件的制法，其特征在于，该半导体组件为单一芯片或堆栈芯片组结构。
17.根据权利要求9所述的晶圆级半导体封装件的制法，其特征在于，该制法还包括研磨该封装胶体，以薄化其厚度。
18.根据权利要求17项所述的晶圆级半导体封装件的制法，其特征在于，该封装胶体外露该半导体组件的非作用面。
19.根据权利要求9所述的晶圆级半导体封装件的制法，其特征在于，是借由研磨工艺或蚀刻工艺，移除该承载板。
20.根据权利要求9所述的晶圆级半导体封装件的制法，其特征在于，该制法还包括于移除该承载板之后，形成导电组件于该露出的线路层上。
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