CN102593102B - 半导体芯片、堆叠型半导体封装体及其制造方法 - Google Patents
半导体芯片、堆叠型半导体封装体及其制造方法 Download PDFInfo
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- CN102593102B CN102593102B CN201110463172.9A CN201110463172A CN102593102B CN 102593102 B CN102593102 B CN 102593102B CN 201110463172 A CN201110463172 A CN 201110463172A CN 102593102 B CN102593102 B CN 102593102B
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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Abstract
本发明公开了一种半导体芯片包括:第一基板,其具有第一表面和背对该第一表面的第二表面;第一测试硅通孔(TSV),从该第一表面到第二表面贯穿该第一基板;以及导电凸起,耦合到该第一测试TSV并从该第二表面突出。
Description
技术领域
本发明的示意性实施例总体涉及一种半导体封装体及其制造方法,更具体涉及一种具有形成在其中的导电凸起以便于封装测试的半导体芯片、使用该半导体芯片的半导体封装体及其制造方法。
背景技术
随着诸如移动产品的小型化和高性能的电子产品的广泛使用,一直努力追求小型化、高容量的半导体存储器件。为了提高存储容量,可在一个封装体内安装和组装多个半导体芯片。相比于提高半导体芯片的高集成度,通常认为封装能够更有效和低成本地提高存储容量。因此,人们做出各种尝试以通过其中具有多个半导体芯片的多芯片封装来提高半导体存储器件的存储容量。
多芯片封装可以具有垂直构型或水平构型。垂直构型包括多个垂直堆叠的半导体芯片,而且对于这种类型的具有高密度和高性能的多芯片封装来说,硅通孔(TSV)是关键技术之一。采用硅通孔的封装具有这样的构型:多个半导体芯片在垂直方向上通过形成在各个晶片级的半导体芯片中的硅通孔而耦合。
系统级封装(以下称为SIP)已知为一种封装体,其中相同种类或各种不同种类的半导体器件在芯片水平或晶片水平上垂直堆叠,且堆叠的晶片或芯片通过硅通孔相互耦合。在这样的SIP中,通过垂直堆叠相同种类的芯片可以增加数据存储密度。此外,通过堆叠各种不同类型的芯片可以制造各种不同类型的封装。
另一方面,在将存储芯片堆叠到基板上之前,需要测试存储芯片的性能。存储芯片包括形成在其下部中的大量凸块(bump),但是这些凸块的尺寸和节距非常小。因此,难以进行探针测试。
发明内容
本发明的实施例涉及一种半导体芯片及其制造方法,在实现精细的节距的同时,对每个单独封装产品,该半导体芯片能够测试电路层是否正常运行以及电路层是否电耦合。
在实施例中,半导体芯片包括:第一基板,具有一个表面和背对该一个表面的另一表面;第一测试TSV,从一个表面到另一表面贯穿该第一基板;以及导电凸起,电耦合到第一测试TSV并从另一表面突出。
导电凸起可设置在基板的边缘,导电凸起偏离该第一测试TSV的中心。
半导体芯片可进一步包括焊盘(land)部分,其耦合导电凸起和第一测试TSV。焊盘部分可以通过重排互连而耦合到第一测试TSV。
在实施例中,半导体封装体包括:基板;堆叠在该基板上的两个或更多个半导体芯片,每个半导体芯片包括一个表面和背对该一个表面的另一表面以及从一个表面到另一表面贯穿半导体芯片的测试TSV;以及导电凸起,从半导体芯片之中的最上面的半导体芯片的另一表面突出并电耦合到测试TSV。
导电凸起可设置在基板的边缘,导电凸起偏离第一测试TSV的中心。
半导体封装体可进一步包括形成在最上方的半导体芯片的另一表面上并且连接导电凸起和测试TSV的焊盘部分。
焊盘部分可通过重排互连而耦合到测试TSV。
半导体封装体可进一步包括基板与半导体芯片之间的控制器。
在实施例中,半导体封装体的制造方法包括:在第二半导体芯片上堆叠第一半导体芯片;第一半导体芯片具有一个表面和背对该一个表面的另一表面并包括从一个表面到另一表面贯穿第一半导体芯片的第一测试TSV;在第一半导体芯片的另一表面上形成绝缘层,并图案化绝缘层以暴露第一测试TSV;以及形成导电凸起,其电耦合到暴露的第一测试TSV并从另一表面突出。
该方法可进一步包括在形成导电凸起之前形成焊盘部分,其电耦合暴露的第一测试TSV与导电凸起。
导电凸起可设置在第一半导体芯片的边缘,导电凸起偏离第一测试TSV的中心。
导电凸起的形成可包括:在第一半导体芯片上定位掩膜;在掩膜的开口部分中放置焊料球;以及执行回流工艺使焊料球熔接到第一测试TSV。
附图说明
从下面结合附图的更详细的描述可更清晰的理解上面以及其他方面、特征和其他的优点,其中:
图1和图2分别为示出根据本发明的实施例的半导体芯片的局部结构的平面图和截面图;
图3和图4为示出根据本发明的实施例半导体芯片的局部结构的截面图;
图5A至图5C为示出根据本发明的实施例的导电凸起的各种示例的截面图;
图6A-6G为示出根据本发明的实施例的半导体芯片的制造方法的截面图;
图7A和图7B为示出根据本发明的实施例的堆叠型半导体封装的局部结构的截面图;以及
图8A至图8E为示出根据本发明的实施例的半导体封装的制造方法的截面图。
具体实施方式
以下,将参照附图来描述本发明的实施例。但是,实施例仅用于示意目的而并不旨在限制本发明的范围。
图1和图2分别为示出根据本发明的实施例的半导体芯片的局部结构的平面图和截面图。图2示出沿着图1中的线A-A`的截面。
参照图1和图2,根据本发明的实施例的半导体芯片400包括第一基板401、第一测试TSV540和导电凸起700。
第一基板401具有第一表面401a和背对第一表面401a的第二表面401b。第一表面401a包括有源区402,诸如晶体管的半导体器件形成在有源区402中。此外,第一基板401可包括互连层(未示出),其将半导体器件电耦合到另一器件或功能单元。
第一测试TSV540从第一表面401a到第二表面401b贯穿第一基板401而形成。第一基板401可包括形成在其中的多个测试TSV,但是测试TSV540总体称为第一测试TSV540。第一测试TSV540可耦合到第一基板401内侧的电路层(未示出),以测试电路是否正常运行。电路层可包括用于施加电信号到半导体器件的互连层,该半导体器件例如为形成在第一基板401的有源区402中的半导体器件。
导电凸起700电耦合到第一测试TSV540,且其形状或材料不受限。例如,导电凸起700可形成为各种形状,例如半球形、球形和六棱柱形,以及如图2所示的蘑菇形,这将会在下面更详细描述。由于导电凸起700成为电路径,因此导电凸起700可包括导电材料,例如导电聚合物、其衍生物、金属、或导电聚合物和金属的复合材料。例如,导电凸起700可包括选自由导电聚合物及其衍生物,例如聚苯胺、聚噻吩、聚(3,4-乙烯基二氧噻吩)、聚吡咯和PPV(聚苯乙烯撑)构成的组中的一种或多种。此外,导电凸起700可包括选自由金(Au)、银(Ag)、铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)、铂(Pt)、钯(Pd)、锡(Sn)、铅(Pb)、锌(Zn)、铟(In)、镉(Cd)、铬(Cr)和钼(Mo)构成的组中的一种或多种金属。
焊盘部分420用于电耦合导电凸起700和第一测试TSV540。焊盘部分420可通过重排互连(未示出)而被耦合到第一测试TSV540。由于焊盘部分420成为第一测试TSV540和导电凸起700之间的电耦合路径,焊盘部分420可包括导电材料,例如导电聚合物、其衍生物、金属、或导电聚合物与金属的复合材料。这里,焊盘部分420可包括选自由Au、Ag、Cu、Al、Ni、W、Ti、Pt、Pd、Sn、Pb、Zn、In、Cd、Cr和Mo构成的组中的一种或多种金属,并且可以具有多层结构。当导电凸起700直接耦合到第一测试TSV540时,焊盘部分420可以省略。
在第一基板401和导电凸起700之间,可插入第一绝缘层410和第二绝缘层430。第一绝缘层410和第二绝缘层430可包括一种或多种有机绝缘材料和无机绝缘层材料。可以使用任何能够实现绝缘功能的材料。有机绝缘材料的示例包括聚酰亚胺、苯并环丁烯、光丙烯醛(photoacryl)、聚酯、包括光致抗蚀剂的光敏树脂、SiOCH、SiCHN和SiCH,无机绝缘材料的示例可包括氧化硅、氮化硅、碳化硅、金属氧化物、SiC和SiCN。但是,本发明并不限于此。
光致抗蚀剂可包括对光呈现感光反应的敏化剂、形成薄膜本体的树脂和用于溶解树脂的有机溶剂,且正光致抗蚀剂和负光致抗蚀剂都可使用。在正性光致抗蚀剂的情况下,线性酚醛清漆(novolak)、热固性酚醛树脂(resole)和酚醛树脂可以用作树脂,而二氮醌、PMMA(聚甲基丙烯酸甲酯)及其衍生物可用作敏化剂。在使用负光致抗蚀剂的情况下,聚肉桂酸乙烯酯、DCPA(丙烯酸2,3-二氯-1-丙酯,2,3-dichloro-1-prophy-acrylate)和烯丙酯预聚物可用作树脂。
SiOCH、SiCHN和SiCH可包括利用聚有机硅烷通过等离子化学气相沉积(CVD)方法形成的有机绝缘材料。可使用的聚有机硅烷可包括选自三甲基乙烯基硅烷、三乙基乙烯基硅烷、二甲基二乙烯基硅烷、二乙基二乙烯基硅烷、甲基三乙烯基硅烷、乙基三乙烯基硅烷、四乙烯基硅烷、四乙基硅烷和三乙基硅烷构成的组中的一种或多种。
此外,根据导电凸起700的形状和位置,第一绝缘层410和第二绝缘层430二者或其中任一可不存在。此外,第一信号TSV640可形成在第一基板401中并可耦合到存在于第一基板401中的电路层(未示出)。
参照图1,多个导电凸起700可定位为离第一测试TSV540的中心部分预定距离d并且排列为一条线。此外,导电凸起700可以排成两条线,两条线之间具有双倍距离,或三条线或更多条线。导电凸起700可定位在离开第一测试TSV540的中心部分的半导体芯片的边缘X处,但是本发明并不限于此。
图3和图4为示出根据本发明的实施例的半导体芯片的局部结构的截面图。
参照图3,根据本发明的实施例的导电凸起700可以这样的方式定位:导电凸起700的中心与第一测试TSV540重合。参照图4,导电凸起700可直接连接到第一测试TSV540,而可省略焊盘部分420和第二绝缘层430。
图5A至图5C为示出根据本发明的实施例的导电凸起的各种示例的截面图。
参照图5A,导电凸起700可包括柱形部分700a和凸块部分700b。柱形部分700a和凸块部分700b可由相同的材料或不同材料形成。这里,柱形部分700a可由金属材料形成,而凸块部分700b可包括焊料凸块。例如,柱形部分700a可包括选自由Au、Ag、Cu、Al、Ni、W、Ti、Pt、Pd、Sn、Pb、Zn、In、Cd、Cr和Mo构成的组中的一种或多种金属,并且可具有多层结构。凸块部分700b可包括由Sn-Pb基合金焊料、Sn-Pb-Ag基合金焊料或SAC(Sn-Ag-Cu)基合金焊料形成的焊料凸块。由于柱形部分700a以这样的方式形成,因此能够有效减小半导体器件(芯片)的尺寸和重量。
而且,第二绝缘层430可不存在,而柱形部分700a可由各种方法形成,该各种方法包括诸如无电镀或电镀的镀覆、离子镀覆、丝网印刷、旋涂、真空沉积和溅射。例如,施加和图案化光致抗蚀剂材料以暴露要在其中形成柱形部分700a的区域,并且通过电镀形成由铜形成的柱形部分700a和由焊料形成的凸块部分700b。然后,去除光致抗蚀剂材料,通过回流工艺使得凸块部分700b的表面形成为凸起状。此外,用于释放应力的缓冲层可以形成在柱形部分700a下方。
参照图5B,导电凸起700可以形成为球形。参照图5C,导电凸起700可以具有截面形成为三角形的上部。此外,导电凸起700可以制造成各种形状。
以下,参照图6A至图6G,描述根据本发明的实施例的半导体芯片的制造方法。在下面的描述中,将省略或简单描述与上面描述的内容重复的部分。
参照图6A,准备半导体基板401,其具有第一表面401a和背对第一表面401a的第二表面401b。然后,通过已知半导体制造技术在第一表面401a上形成诸如晶体管的半导体器件。其中形成有半导体器件的区域称为有源区402。严格来说,图6A中的半导体基板401不同于通过切割半导体基板401所得到的第一基板401。但是,为了便于描述,使用相同的参考标号。
在存储器件的情况下,半导体基板401可包括单晶硅基板,但是本发明并不限于此。半导体基板401可包括由GaAs、LiTaO3、LiNbO3或蓝宝石形成的基板以及多晶硅基板。这就是说,根据要形成的半导体器件可使用不同的基板。
参照图6B,形成第一测试TSV540和第一信号TSV640。第一测试TSV540和第一信号TSV640可以通过TSV形成技术而形成。例如,可在半导体基板的第一表面401a上形成接合垫(未示出),相邻于接合垫形成沟道。沟道可通过激光钻孔或深反应离子蚀刻(RIE)方法形成,并可包括垂直沟道和锥形沟道。在沟道形成工艺之后,执行化学或物理处理以去除在沟道形成工艺过程中产生的残留物以便于后面的镀覆工艺,从而改善镀覆粘着性。然后,形成种子金属层,以及通过电镀在沟道中埋置导电材料而形成第一测试TSV540。第一测试TSV540和第一信号TSV640可分别具有形成在其一端的前端凸块5401和6401。
参照图6C,在其中形成有TSV540和640的半导体基板401的第一表面401a上接合载体晶片110,并且研磨半导体基板401的第二表面401b以暴露TSV540和640。这里,可以以这样的方式进行研磨:暴露的TSVs的上表面的水平与半导体基板401的第二表面401b的水平相同。载体晶片110可由玻璃或硅形成。载体晶片110是暂时附着的,以容易处理由去除半导体基板401的上部(另一表面)至预定厚度而变薄的半导体基板401。载体晶片110通过可容易去除的粘结剂形成的粘结层而粘附。
减小半导体基板401厚度的研磨工艺可以通过用于制造半导体器件的典型的研磨装置来进行。例如,研磨工艺可利用研磨装置进行,研磨装置包括装载区、粗加工区、精加工区和卸载区。粗加工用来对装载的基板的第二表面401b进行粗磨,而精加工用来对基板的第二表面401b进行更平滑的研磨。
参照图6D,在半导体基板的被研磨的第二平面401b上形成第一绝缘层410,然后图案化以暴露第一测试TSV540的上部540b。第一绝缘层410可以通过诸如旋涂、溶凝胶涂敷、深涂覆、真空沉积或化学气相沉积(CVD)的薄膜形成工艺而形成。例如,当第一绝缘层410包括氧化硅时,可采用CVD或热氧化法,而当第一绝缘层410包括光致抗蚀剂时,可采用旋涂。
可根据绝缘层材料的类型选择使用第一绝缘层410的图案化方法。例如,当绝缘层材料为光致抗蚀剂时,可采用曝光和显影方法。对于另一示例,当绝缘层材料为氧化硅(SiO2)时,光致抗蚀剂材料施加到氧化硅上,通过曝光和显影进行图案化,然后通过采用CF4/H2气体的干蚀刻工艺或采用缓冲氢氟酸(BHF)的湿蚀刻工艺以使第一TSV540的上部540b暴露。然后,利用诸如O2等离子灰化的已知技术去除剩余的光致抗蚀剂。
参照图6E,形成焊盘部分420以耦合到具有暴露的上表面的测试TSV540。焊盘部分420可通过无电镀、电镀、真空沉积或溅射而形成。例如,施加光致抗蚀剂,并通过曝光和显影使得其中要形成焊盘部分420的区域暴露。然后,采用电镀形成由金属材料形成的焊盘部分。对于另一示例,首先沉积金属材料,并施加光致抗蚀剂。然后,将其中要形成焊盘部分420的光致抗蚀剂部分通过光刻(lithography)工艺去除,并且利用剩余的光致抗蚀剂作为蚀刻掩膜通过诸如干蚀刻或湿蚀刻的蚀刻工艺图案化沉积的金属材料。
参照图6F,形成和图案化第二绝缘层430以暴露其中导电凸起要接触焊盘的区域420b。第二绝缘层430可包括与第一绝缘层410相同的材料或不同的材料,并且可通过相同的制造工艺或不同的制造工艺形成。根据第一绝缘层410的上述图案化工艺可对第二绝缘层430执行图案化。
参照图6G,分离粘附到半导体基板401的载体晶片110,贴上切割带120,并将基板400切割成单个半导体芯片。基板400的切割可以通过金刚石切割或激光切割执行。
下面将描述根据本发明的实施例的堆叠型半导体封装体。根据本发明的实施例的堆叠型半导体封装体可包括一个或多个半导体芯片的堆叠结构。下面的描述将集中于例如三个半导体芯片(或插入体)的堆叠结构。
图7A和7B为截面图,示出了根据本发明的一个实施例的堆叠型半导体封装体的局部结构。
参照图7A,根据本发明的实施例的半导体封装体包括堆叠在基板150上的多个半导体芯片200、300和400。基板150可包括印刷电路板(PCB)或封装基板,在该封装基板的中部耦合PCB和半导体芯片。控制器160可插入基板150和半导体芯片200之间。控制器160可包括具有诸如SER/DES电路的逻辑电路的控制芯片。例如,第一半导体芯片200和第二半导体芯片300可包括诸如FRAM或DRAM的存储芯片。此外,相同类型或不同类型的半导体芯片可用作第一半导体芯片200和第二半导体芯片300。
半导体芯片200、300和400分别包括测试TSV520、530和540以及信号TSV620、630和640。各个半导体芯片的测试TSV和信号TSV在彼此对应的位置对准并互相耦合。各个半导体芯片200、300和400之间的空间填充有填隙材料810,而堆叠的半导体芯片通过诸如环氧树脂模制材料(EMC)的模制材料820被最终模制成型。
在封装中堆叠的半导体芯片中排布在最上部的半导体芯片400包括耦合到测试TSV540并设置用于测试的导电凸起700。由于上面已经描述过导电凸起700的形状和材料,这里将省略其详细描述。此外,与根据本发明的实施例的半导体芯片中所述结构的构件相同的构件的详细描述也被省略。
图7B示出半导体封装的示例,其中一个或多个图7A的堆叠型封装体被水平安装。除了堆叠型封装体是水平安装之外,该半导体封装体具有与图7A中所示的相同结构。因此,这里省略其详细描述。
参照图8A至图8E,将描述根据本发明的实施例的堆叠型半导体封装体的制造方法。
首先,参照图8A,其中形成有第三TSV520的插入体(或第三半导体芯片)200设置在载体晶片100上,而其中形成有第二测试TSV530的第二半导体芯片300设置在插入体200上。这里,插入体200和第二半导体芯片300可分别包括形成在其中的第三信号TSV620和第二信号TSV630。而且,第三信号TSV620和第二信号TSV630在彼此对应的位置上对准,第二测试TSV530和第三测试TSV520也在彼此对应的位置上对准从而相互耦合。插入体200和第二半导体芯片300之间的空间可由填隙材料810填充。
参照图8B,通过图6A至图6G的工艺制造的第一半导体芯片400设置在第二半导体芯片300上。此时,第一测试TSV540和第二测试TSV530在彼此对应的位置上对准,第一信号TSV640和第二信号TSV630在彼此对应的位置上对准从而相互耦合。位于第一半导体芯片400和第二半导体芯片300之间的空间由填隙材料810填充。
第一测试TSV540和第二测试TSV530以及第一信号TSV640和第二信号630分别通过介于其间但未示出的焊料膏、焊料凸块或导电粘接剂相互耦合。
参照图8C,焊料球放置在掩膜750的开口部分中,即在掩膜750设置于第一半导体芯片400上的状态下的导电凸起接触焊盘的区域。当使用掩膜时,可以不用光致抗蚀剂或蚀刻工艺。掩膜750可包括金属掩膜并由SUS304等形成,但是本发明并不限于此。此外,可以涂覆焊膏,取代放置焊料球。
参照图8D,去除掩膜750,然后通过回流工艺形成导电凸起700。回流工艺的温度可根据所使用的焊料球的成分而不同,并可提高到所用焊料球的熔点或更高的温度。例如,用作通常的焊料的共晶Pb-Sn合金(63Sn/37Pb)具有183℃的熔点。因此,回流工艺的温度可升到183℃或更高或比熔点高5至30℃的温度,从而确保良好的焊料回流以及优选的熔融质量。
图8C和图8D示出通过焊料球安放和回流工艺形成导电凸起的工艺,然而本发明并不限于此。也就是,施加(沉积)导电材料,施加光致抗蚀剂,通过诸如光学光刻、电子束光刻、X射线光刻或极UV光刻的光刻工艺进行曝光和显影,以及进行蚀刻以形成所希望的图形(导电凸起)。此外,导电膏可通过丝网印刷工艺施加,然后可进行干燥或烘烤工艺以形成导电凸起。如上所述,导电凸起可包括具有柱形部分和凸块部分的导电凸起。可以利用任何制造方法,且导电凸起的上部可形成为便于封装测试凸状。
参照图8E,载体晶片110被分离,并通过切割工艺完成封装。如果必要,可以执行附加工艺。通过形成上述封装,可以通过导电凸起700对每个单独的封装进行测试。
以上公开的本发明实施例用于示例目的。本领域的技术人员应理解在不超出本发明所附权利要求公开的本发明的精神和范围的情况下,可以进行各种变型、添加和替代。
本申请要求2010年12月1日和2011年11月23日提交韩国知识产局的韩国申请第10-2010-0121243号和第10-2011-0123016号的优先权,其全部内容通过参考引入结合于此。
Claims (20)
1.一种半导体芯片,包括:
第一基板,具有第一表面和与背对该第一表面的第二表面;
信号硅通孔,从该第一表面到该第二表面贯穿该第一基板;
第一测试硅通孔,从该第一表面到该第二表面贯穿该第一基板,其中该第一测试硅通孔设置为与该信号硅通孔间隔开;
绝缘层,设置在该第一基板的该第二表面之上,其中该绝缘层覆盖该信号硅通孔并具有暴露该第一测试硅通孔的通路孔;以及
导电凸起,通过该通路孔耦合到该第一测试硅通孔并从该第二表面突出。
2.如权利要求1所述的半导体芯片,其中该导电凸起选自由金(Au)、银(Ag)、铜(Cu)、铝(Al)、镍(Ni)、钨(W)、钛(Ti)、铂(Pt)、钯(Pd)、锡(Sn)、铅(Pb)、锌(Zn)、铟(In)、镉(Cd)、铬(Cr)和钼(Mo)构成的组中的一种或多种金属。
3.如权利要求1所述的半导体芯片,其中该导电凸起设置在该基板的边缘,该导电凸起偏离该第一测试硅通孔的中心。
4.如权利要求1所述的半导体芯片,还包括耦合该导电凸起和该第一测试硅通孔的焊盘部分。
5.如权利要求4所述的半导体芯片,其中该焊盘部分通过重排互连耦合到该第一测试硅通孔。
6.如权利要求4所述的半导体芯片,其中该焊盘部分包括选自由Au、Ag、Cu、Al、Ni、W、Ti、Pt、Pd、Sn、Pb、Zn、In、Cd、Cr和Mo构成的组中的一种或多种金属。
7.一种半导体封装体,包括:
基板;
堆叠在该基板上的两个或更多个半导体芯片,其中每个半导体芯片具有第一表面和背对该第一表面的第二表面,并包括从该第一表面到该第二表面贯穿该半导体芯片的信号硅通孔和测试硅通孔;
绝缘层,设置在该所述两个或更多个半导体芯片之中的最上面的半导体芯片的该第二表面之上,其中该绝缘层覆盖该信号硅通孔并具有暴露该测试硅通孔的通路孔;以及
导电凸起,从该最上面的半导体芯片的该第二表面突出并通过该通路孔耦合到该测试硅通孔。
8.如权利要求7所述的半导体封装体,其中该导电凸起包括选自由Au、Ag、Cu、Al、Ni、W、Ti、Pt、Pd、Sn、Pb、Zn、In、Cd、Cr和Mo构成的组中的一种或多种金属。
9.如权利要求7所述的半导体封装体,其中该导电凸起位于该基板的边缘,该导电凸起偏离该测试硅通孔的中心。
10.如权利要求7所述的半导体封装体,还包括焊盘部分,形成在该最上面的半导体芯片的该第二表面上并耦合该导电凸起和该测试硅通孔。
11.如权利要求10所述的半导体封装体,其中该焊盘部分通过重排互连耦合到该测试硅通孔。
12.如权利要求11所述的半导体封装体,其中该焊盘部分包括选自由Au、Ag、Cu、Al、Ni、W、Ti、Pt、Pd、Sn、Pb、Zn、In、Cd、Cr和Mo构成的组中的一种或多种金属。
13.如权利要求7所述的半导体封装体,还包括该基板和该半导体芯片之间的控制器。
14.一种半导体封装体的制造方法,包括:
在第二半导体芯片上设置第一半导体芯片,该第一半导体芯片具有第一表面和背对该第一表面的第二表面并包括从该第一表面到该第二表面贯穿该第一半导体芯片的信号硅通孔和第一测试硅通孔;
在该第一半导体芯片的该第二表面上形成绝缘层,并图案化该绝缘层,使得图案化的绝缘层覆盖该信号硅通孔并具有暴露该第一测试硅通孔的通路孔;以及
形成通过该通路孔电耦合到该暴露的第一测试硅通孔并从该第二表面突出的导电凸起。
15.如权利要求14所述的方法,还包括在形成导电凸起之前,形成电耦合该暴露的第一测试硅通孔和该导电凸起的焊盘部分。
16.如权利要求14所述的方法,其中该导电凸起位于该第一半导体芯片的边缘,该导电凸起偏离该第一测试硅通孔的中心。
17.如权利要求14所述的方法,其中该导电凸起的形成包括:
在该第一半导体芯片上定位掩膜;
在该掩膜的开口部分中放置焊料球;以及
执行回流工艺使得该焊料球熔接到该第一测试硅通孔。
18.如权利要求14所述的方法,其中该导电凸起包括选自由Au、Ag、Cu、Al、Ni、W、Ti、Pt、Pd、Sn、Pb、Zn、In、Cd、Cr和Mo构成的组中的一种或多种金属。
19.如权利要求14所述的方法,其中该导电凸起包括柱形部分和凸块部分。
20.如权利要求19所述的方法,其中该柱形部分包含铜,该凸块部分包含焊料。
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US8237257B2 (en) * | 2008-09-25 | 2012-08-07 | King Dragon International Inc. | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same |
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US6239495B1 (en) * | 1998-07-29 | 2001-05-29 | Kabushiki Kaisha Toshiba | Multichip semiconductor device and memory card |
CN1841689A (zh) * | 2005-03-28 | 2006-10-04 | 富士通株式会社 | 半导体器件及半导体器件制造方法 |
CN101123242A (zh) * | 2006-08-11 | 2008-02-13 | 国际商业机器公司 | 制造通孔和电子器件的方法 |
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CN102593102A (zh) | 2012-07-18 |
US20120138925A1 (en) | 2012-06-07 |
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