KR100912427B1 - 적층 칩 패키지 및 그 제조 방법 - Google Patents
적층 칩 패키지 및 그 제조 방법 Download PDFInfo
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- KR100912427B1 KR100912427B1 KR20060103043A KR20060103043A KR100912427B1 KR 100912427 B1 KR100912427 B1 KR 100912427B1 KR 20060103043 A KR20060103043 A KR 20060103043A KR 20060103043 A KR20060103043 A KR 20060103043A KR 100912427 B1 KR100912427 B1 KR 100912427B1
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- 238000000034 method Methods 0.000 title claims description 30
- 239000002184 metal Substances 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 62
- 125000006850 spacer group Chemical group 0.000 claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims description 147
- 239000000758 substrate Substances 0.000 claims description 16
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- 238000009713 electroplating Methods 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
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- 238000005520 cutting process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
Description
Claims (20)
- 제 1반도체 칩 상에 제 2반도체 칩을 적층하는 단계,상기 제2 반도체 칩의 측면을 둘러싸는 스페이서를 형성하는 단계,상기 측벽 스페이서 상에 상기 제1 반도체 칩 및 제2 반도체 칩을 전기적으로 연결하는 금속 배선을 형성 하는 단계,상기 금속 배선 상에 솔더 범프를 형성하는 단계, 및상기 솔더 범프를 통해 상기 제2 반도체 칩을 기판에 연결하는 단계를 포함하는 반도체 패키지 제조 방법.
- 제1 항에 있어서,상기 스페이서는 접착제를 사용하여 형성되는 반도체 패키지 제조 방법.
- 제1 항에 있어서,상기 금속 배선을 형성하는 단계는:금속 배선을 위한 배선막을 형성하는 단계; 그리고상기 배선막을 패터닝하는 단계를 포함하는 반도체 패키지 제조 방법.
- 제3 항에 있어서,상기 배선막을 형성하는 단계는:시드금속막을 형성하는 단계; 그리고전기 도금을 진행하여 상기 시드금속막 상에 금속막을 형성하는 단계를 포함하는 반도체 패키지 제조 방법.
- 제4 항에 있어서,상기 전기 도금을 진행하기 전에 상기 시드금속막 상에 마스크 패턴을 형성하는 단계; 그리고,상기 전기 도금을 진행한 후에 상기 마스크 패턴을 제거하는 단계를 더 포함하며,상기 금속막은 상기 마스크 패턴으로 덮이지 않은 시드금속층상에 선택적으로 형성되며,상기 배선막을 패터닝하는 단계는 상기 마스크 패턴 아래의 시드금속층을 제거하는 것을 포함하는 반도체 패키지 제조 방법.
- 제1 항에 있어서,상기 금속 배선은 구리인 반도체 패키지 제조 방법.
- 제6 항에 있어서,상기 구리 금속 배선은 전기 도금법을 이용하여 형성하는 반도체 패키지 제조 방법.
- 삭제
- 반도체 웨이퍼에 제 1 반도체 칩을 형성하는 단계,제 2반도체 칩을 상기 제 1반도체 칩 상에 부착하는 단계,상기 제 2반도체 칩의 측면을 둘러싸는 스페이서를 형성하는 단계,상기 웨이퍼와 상기 반도체 칩 들 상에 금속막을 증착하는 단계,상기 금속막을 패터닝하여 상기 제1 반도체 칩 및 상기 제2 반도체 칩을 전기적으로 연결하는 금속 배선을 형성하는 단계,상기 금속 배선 상에 솔더 범프를 형성하는 단계, 및상기 솔더 범프를 통해 상기 제2 반도체 칩을 기판에 연결하는 단계를 포함하는 반도체 패키지 제조 방법.
- 제 9항에 있어서,상기 부착 단계는 상기 제2 반도체 칩은 접착제를 사용하여 상기 제1 반도체 칩 상에 부착되는 것을 포함하고, 상기 스페이서의 형성 단계는 상기 부착될 때 상기 제2 반도체 칩의 측면에 상기 접착제를 사용하여 상기 스페이서를 형성하는 것을 포함하는 반도체 패키지 제조 방법.
- 제 10항에 있어서,상기 측벽 스페이서의 높이와 너비가 동일한 반도체 패키지 제조 방법.
- 제 11항에 있어서,상기 측벽 스페이서의 높이는 제 2반도체 칩의 두께와 동일한 반도체 패키지 제조 방법.
- 삭제
- 제9 항에 있어서,상기 금속 막은 구리를 포함하는반도체 패키지 제조 방법.
- 제12 항에 있어서,상기 구리는 전기 도금법을 이용하여 형성하는 반도체 패키지 제조 방법.
- 제1 반도체 칩;상기 제1 반도체 칩 상에 부착된 제2 반도체 칩;상기 제1 반도체 칩 상에 형성되어 상기 제2 반도체 칩의 측면을 둘러싸는 스페이서;상기 스페이서 상에 형성되고 상기 제1 반도체 칩 및 상기 제2 반도체 칩을 전기적으로 연결하는 금속 배선; 및기판과 상기 제2 반도체 칩을 연결시키는, 상기 금속 배선 상의 솔더 범프를 포함하는 적층 반도체 패키지.
- 제16 항에 있어서,상기 제2 반도체 칩은 상기 제1 반도체 칩 상에 접착제를 사용하여 부착되며, 상기 스페이서는 상기 제2 반도체 칩이 상기 제1 반도체 칩에 부착될 때 상기 접착제로부터 형성되는 적층 반도체 패키지.
- 제16 항에 있어서,상기 제2 반도체 칩의 크기는 상기 제1 반도체 칩의 크기보다 작은 적층 반도체 패키지.
- 제16 항에 있어서,상기 스페이서의 높이와 너비는 실질적으로 동일한 적층 반도체 패키지.
- 제16 항에 있어서,상기 금속 배선은 구리를 포함하는 적층 반도체 패키지.
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US11/623,279 US7638365B2 (en) | 2006-10-23 | 2007-01-15 | Stacked chip package and method for forming the same |
JP2007274271A JP2008109138A (ja) | 2006-10-23 | 2007-10-22 | 積層チップパッケージ及び該パッケージの製造方法 |
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US8106520B2 (en) * | 2008-09-11 | 2012-01-31 | Micron Technology, Inc. | Signal delivery in stacked device |
US9548283B2 (en) * | 2012-07-05 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package redistribution layer structure and method of forming same |
US9136213B2 (en) | 2012-08-02 | 2015-09-15 | Infineon Technologies Ag | Integrated system and method of making the integrated system |
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JP4413452B2 (ja) | 2001-05-30 | 2010-02-10 | パナソニック株式会社 | 半導体装置およびその製造方法 |
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JP2004063569A (ja) * | 2002-07-25 | 2004-02-26 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
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JP2002289766A (ja) * | 2001-03-26 | 2002-10-04 | Matsushita Electric Ind Co Ltd | 積層型半導体装置およびその製造方法 |
KR20030059459A (ko) * | 2001-12-29 | 2003-07-10 | 주식회사 하이닉스반도체 | 칩 적층 패키지 |
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US20080096315A1 (en) | 2008-04-24 |
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