CN101740415B - 集成电路结构及其形成方法 - Google Patents

集成电路结构及其形成方法 Download PDF

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CN101740415B
CN101740415B CN2009101782984A CN200910178298A CN101740415B CN 101740415 B CN101740415 B CN 101740415B CN 2009101782984 A CN2009101782984 A CN 2009101782984A CN 200910178298 A CN200910178298 A CN 200910178298A CN 101740415 B CN101740415 B CN 101740415B
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wafer
integrated circuit
circuit structure
protective material
thinning
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CN101740415A (zh
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杨固峰
邱文智
吴文进
涂宏荣
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种集成电路结构及其形成方法，即堆叠式晶片的制造方法。在一实施例中，该方法包括如下步骤：提供一晶片，具有一芯片侧与一非芯片侧，该芯片侧包括多个半导体芯片；提供多个裸片，粘合每一所述多个裸片至所述多个半导体芯片其中之一；以一保护材料包覆该晶片的该芯片侧与所述多个裸片；薄化该晶片的该非芯片侧至一预期厚度；以及切割该晶片，以使该晶片分离成各自的半导体封装结构。本发明可避免传统晶片粘合工艺的缺点。

Description

集成电路结构及其形成方法
技术领域
本发明涉及一种半导体元件的制造，尤其涉及一种应用于堆叠式晶片制造的结构及方法。
背景技术
在半导体工业中，有效降低一半导体晶片的厚度对于回应降低半导体封装结构厚度、增加芯片速度及应用于高密度制造的目标来说是一重大进展。在堆叠式晶片制造中，两个或更多其上形成有集成电路的半导体晶片彼此相连。借由对一半导体晶片相对于包含图案电路的表面进行所谓的晶背研磨(backside grinding)以降低厚度。由于薄晶片的强度不足且极易造成例如弯曲及/或翘曲的变形，因此，通常在晶片以一切割工艺分离成各自的芯片封装结构之前进行一以一铸模化合物(例如热固型环氧树脂)包覆一晶片表面的包覆步骤。之后，将这些各自的芯片封装结构粘着于一例如印刷电路板(PCB)的基板上。
然而，传统的堆叠式晶片制造工艺也有其缺点。晶片上铸模化合物脱落或分层的地方会造成晶片翘曲。晶片翘曲将不利于制造工艺，减少总工艺产率，且可能降低芯片封装结构的品质与可靠度。此外，晶片上发生铸模化合物分层的地方，晶片的芯片边缘将很容易造成破裂、剥落及/或在后续切割工艺及搬运的过程中受环境影响而腐蚀。
根据上述理由，开发一改良式的堆叠式晶片制造方法以避免传统晶片粘合工艺的缺点是有其必要。
发明内容
本发明为了解决现有技术的问题而提供一种堆叠式晶片的制造方法。在一实施例中，该方法包括如下步骤：提供一晶片，具有一芯片侧与一非芯片侧，该芯片侧包括多个半导体芯片；提供多个裸片，粘合每一所述多个裸片至所述多个半导体芯片其中之一；以一保护材料包覆该晶片的该芯片侧与所述多个裸片；薄化该晶片的该非芯片侧至一预期厚度；以及切割该晶片，以使该晶片分离成各自的半导体封装结构。
本发明还提供了一种集成电路结构，包括：至少一裸片；一半导体芯片，具有一薄化侧与一未薄化侧，该未薄化侧与该裸片粘合，该半导体芯片还包括一硅穿孔，该硅穿孔具有一与该裸片连接的第一末端以及一暴露且与该半导体芯片的该薄化侧齐平的第二末端；以及一第一保护材料，包覆该裸片。
本发明可避免传统晶片粘合工艺的缺点。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举一优选实施例，并配合所附附图，作详细说明如下：
附图说明
图1～图6为一集成电路结构在不同制造阶段过程中一实施例的剖面示意图。
图7是根据本发明的一实施例，一集成电路结构的剖面示意图。
图8是根据本发明的另一实施例，一集成电路结构的剖面示意图。
图9为一流程图，显示一集成电路结构形成方法的一实施例。
其中，附图标记说明如下：
10～集成电路结构；
20～裸片；
22～晶片；
30～裸片的前表面；
40～裸片的背表面；
50～半导体基板；
60～硅穿孔；
62～导电穿孔；
70～半导体芯片；
80～晶片的前表面；
90～晶片的背表面；
100、141～保护材料；
105～介电层；
110～焊锡凸块；
120～切割带；
132～凸块垫；
134～钝化层；
136～上导电层；
138～下导电层；
140～绝缘层；
142～重分布层；
143～基板；
200～集成电路结构形成方法；
202～提供一具有一芯片侧与一非芯片侧的晶片，芯片侧包括多个半导体芯片；
204～提供多个裸片，将每一裸片粘合至多个半导体芯片其中之一；
206～以一保护材料包覆晶片的芯片侧与多个裸片；
208～薄化晶片的非芯片侧至一预期厚度；
210～切割晶片，使晶片分离成各自的半导体封装结构。
具体实施方式
图1为一集成电路结构10在一制造阶段过程中一实施例的一剖面示意图。将裸片20粘合于一晶片22上。裸片20可包括存储芯片、射频芯片、逻辑芯片或其他芯片。每一裸片20具有一前表面30与一背表面40。每一裸片20包括半导体基板50。裸片20的背表面40也为不同半导体基板50的背表面。
晶片22包括多个半导体芯片70。晶片22包括例如硅、砷化锗、水晶晶片、蓝宝石、玻璃或其类似物的半导体晶片。半导体芯片70可包括存储芯片、射频芯片、逻辑芯片或其他芯片。在一实施例中，将每一裸片20粘合于一半导体芯片70上，或是一半导体芯片70可具有超过一个以上的裸片20粘合于其上。在一实施例中，如图7所示，切割后，集成电路结构10具有两个粘合于半导体芯片70上的裸片。在另一实施例中，如图8所示，切割后，集成电路结构10具三个粘合于半导体芯片70上的裸片。粘合于一相同半导体芯片70上的裸片20可具有相同或相异的电路设计或尺寸。
晶片22具有一前表面80与一背表面90。粘合垫(未图示)及/或其他连接结构(未图示)靠近前表面80，而背表面90为一半导体基板的背表面。形成集成电路(未图示)于晶片22的前表面80。集成电路包括有源及无源元件，例如晶体管、电阻、电容或其类似物。
较佳来说，裸片20与半导体芯片70以面对面的方式粘合。粘合方法包括一般使用的方法，例如氧化层对氧化层粘合、氧化层对硅粘合、铜对铜粘合、胶粘剂粘合或其类似方法。在一实施例中，半导体芯片70包括一或多个由前表面80向下延伸进入晶片22的硅穿孔(through-silicon via，TSV)60。硅穿孔60与裸片20连接。在一实施例中，除预先形成于半导体芯片70外，也可于一后续薄化晶片22的步骤之后形成硅穿孔60。
请参阅图2，涂布一铸模化合物或保护材料100于晶片22的前表面80与多个裸片20上。保护材料100由一热固型材料所构成，例如一高分子材料、树脂材料、聚亚酰胺、氧化硅、环氧化物、苯并环丁烯(benzocyclobutenes，BCB)、SilkTM(Dow Chemical)或其组合。为避免晶片22或一主体在研磨的过程中因研磨而造成翘曲，保护材料100较佳为在其固化之后具有一足够高的硬度与弯曲刚度。保护材料100形成于晶片22上的厚度可大于裸片20的高度，以包覆裸片20。保护材料100的厚度并不须特别限制，只要可确保研磨晶片22或一主体所需要的厚度均一性即可。然而，为了在研磨基板后得到理想的厚度均一性，保护材料100的厚度较佳为均一。
利用例如射出式铸模、压缩铸模、锡膏印刷(stencil printing)、旋转涂布或未来发展的铸模工艺涂覆保护材料100于集成电路结构10上。在涂布保护材料100后，进行一薄化工艺前，进行一固化或烘烤步骤，以固化保护材料100。在一实施例中，于一温度介于130～200℃的加热腔室中烘烤保护材料100持续10～300秒。
在固化保护材料100之后，于晶片22的非芯片侧，进行一薄化工艺。以一研磨机对晶片22的非芯片侧进行机械研磨，以降低厚度。根据实际情况，利用机械研磨可研磨晶片22至一大约50～100μm的厚度。然而，若持续借由机械研磨降低晶片22厚度，可能导致晶片损坏。因此，为进一步降低晶片22厚度，较佳为利用一工艺中不会导致损坏的方法，例如湿式化学蚀刻或化学机械研磨(CMP)。在一实施例中，薄化晶片22至一大约5～50μm的厚度。在另一实施例中，薄化晶片22至一大约50～180μm的厚度。在薄化晶片22至一预定厚度之后，若硅穿孔60已预先形成于半导体芯片70中，则硅穿孔60具有一与裸片20连接的第一末端以及一暴露且与晶片22经薄化的非芯片侧齐平的第二末端。
图3为集成电路经一薄化工艺后的一剖面示意图。形成一平坦的介电层105于晶片22经薄化的一侧上，并连接焊锡凸块110至硅穿孔60暴露的末端。若有需要，可形成一蚀刻终止层(未图示)于介电层105与半导体芯片70之间。形成金属导线/垫(未图示)于介电层105中，并电性连接至硅穿孔60。可利用一般使用的方法，例如单镶嵌工艺形成介电层105与金属导线/垫，或是借由毯覆性沉积一金属薄膜，图案化该金属薄膜，以及填入介电层105至金属导线之间。金属导线可由铜、铝、钨、银或其组合物所构成。介电层105可由氧化物、氮化物、未掺杂的硅玻璃、氟化硅玻璃、低介电常数材料或其类似物所构成。之后，形成例如焊锡凸块110的导体结构以连接硅穿孔60暴露的末端。
图4为图3一部分集成电路结构的一剖面示意图。焊接焊锡凸块110至凸块垫132的一上表面。部分凸块垫132为一钝化层134所覆盖。凸块垫132为介电层105所包围。凸块垫132与一上导电层136电性连接。上导电层136借由一绝缘层140与一下导电层138分离。下导电层138与硅穿孔60电性连接。上导电层136与下导电层138彼此借由延伸穿过绝缘层140的导电穿孔62电性连接。图4中还显示，每一凸块垫132可与重分布层(re-distributionlayer，RDL)142连接。重分布层142与上导电层136连接，而上导电层136借由导电穿孔62与下导电层138电性连接，如图4右边所示，或是无重分布层142，如图4左边所示。
如图5所示，一般在完成晶片级测试之后，会将晶片22固定于一切割带120或一裸片架上。之后，以常用的方式沿切割线切割，以将晶片分离成各自的半导体封装结构。图6显示一半导体封装结构，包含铸膜化合物或一保护材料141，以保护封装结构免于环境影响。之后，将各自半导体封装结构的焊锡凸块110粘合至一基板143的电性末端，例如一印刷电路板(PCB)。
图9为一流程图，显示一集成电路结构形成方法200的一实施例，其为图1～图6图所描述的方法。方法200开始于步骤202，提供一具有一芯片侧与一非芯片侧的晶片，芯片侧包括多个半导体芯片。步骤204，提供多个裸片，将每一裸片粘合至多个半导体芯片其中之一。步骤206，以一保护材料包覆晶片的芯片侧与多个裸片。步骤208，薄化晶片的非芯片侧至一预期厚度。步骤210，切割晶片，使晶片分离成各自的半导体封装结构。之后，将各自的半导体封装结构粘着于一例如印刷电路板(PCB)的基板上。
虽然本发明已以优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作更动与润饰，因此本发明的保护范围当视所附的权利要求书所界定的范围为准。

Claims (15)

1.一种集成电路结构的形成方法，包括如下步骤：
提供一晶片，具有一芯片侧与一非芯片侧，该芯片侧包括一上表面及多个半导体芯片；
提供多个裸片，粘合每一所述多个裸片至所述多个半导体芯片其中之一；
以一保护材料包覆该晶片的该芯片侧与所述多个裸片；
薄化该晶片的该非芯片侧至一预期厚度，其中每一所述多个半导体芯片包括一硅穿孔，该硅穿孔穿透该芯片侧的该上表面，且具有一与所述多个裸片其中之一连接的第一末端以及一暴露且与该晶片经薄化的该非芯片侧齐平的第二末端；以及
切割该晶片，以使该晶片分离成各自的半导体封装结构。
2.如权利要求1所述的集成电路结构的形成方法，其中该保护材料包括一高分子材料、氧化硅或其组合。
3.如权利要求1所述的集成电路结构的形成方法，其中该保护材料包括一树脂材料。
4.如权利要求1所述的集成电路结构的形成方法，其中该保护材料包括一聚亚酰胺、环氧化物、苯并环丁烯或其组合。
5.如权利要求1所述的集成电路结构的形成方法，其中以该保护材料包覆该晶片的该芯片侧与所述多个裸片的方法选自由射出式铸模、压缩铸模、锡膏印刷及旋转涂布所组成的族群。
6.如权利要求1所述的集成电路结构的形成方法，还包括于薄化该晶片的该非芯片侧至一预期厚度之前，烘烤该保护材料，以固化该保护材料。
7.如权利要求1所述的集成电路结构的形成方法，其中薄化该晶片的该非芯片侧至一预期厚度的方法包括机械性薄化该晶片，以及进行一湿式化学蚀刻或化学机械研磨。
8.如权利要求1所述的集成电路结构的形成方法，还包括于切割该晶片之前，提供焊锡凸块，以连接该硅穿孔的该第二末端。
9.如权利要求1所述的集成电路结构的形成方法，包括于切割该晶片之前，固定该晶片于一裸片架上。
10.一种集成电路结构，包括：
至少一裸片；
一半导体芯片，具有一薄化侧与一未薄化侧，该未薄化侧包括一上表面，该未薄化侧与该裸片粘合，该半导体芯片还包括一硅穿孔，该硅穿孔穿透该未薄化侧的该上表面，且具有一与该裸片直接连接的第一末端以及一暴露且与该半导体芯片的该薄化侧齐平的第二末端；以及
一第一保护材料，包覆该裸片。
11.如权利要求10所述的集成电路结构，还包括一焊锡凸块，连接该硅穿孔的该第二末端。
12.如权利要求11所述的集成电路结构，还包括一第二保护材料，包覆该第一保护材料、该裸片与该半导体芯片。
13.如权利要求11所述的集成电路结构，其中该第一保护材料包括一高分子材料、氧化硅或其组合。
14.如权利要求11所述的集成电路结构，其中该第一保护材料包括一树脂材料。
15.如权利要求11所述的集成电路结构，其中该第一保护材料包括一聚亚酰胺、环氧化物、苯并环丁烯或其组合。
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