CN104681531A - 封装基板及其制法 - Google Patents

封装基板及其制法 Download PDF

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CN104681531A
CN104681531A CN201310666162.4A CN201310666162A CN104681531A CN 104681531 A CN104681531 A CN 104681531A CN 201310666162 A CN201310666162 A CN 201310666162A CN 104681531 A CN104681531 A CN 104681531A
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layer
base plate
dielectric layer
making
electric contact
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CN104681531B (zh
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何祈庆
蔡瀛洲
黄圣哲
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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Abstract

一种封装基板及其制法，该封装基板包括：介电层，其具有相对的第一表面与第二表面；第一线路层，其嵌埋于该介电层的第一表面上，且该第一线路层具有多个第一电性接触垫；以及导电凸部，其设于各该第一电性接触垫上并凸出该介电层的第一表面，以于后续当电子组件欲藉由导电组件结合至该第一电性接触垫时，该导电组件与该导电凸部之间具有较多接触面(即该导电凸部的顶面与侧面)，使该导电组件与该导电凸部间的结合力提升，因而能避免发生脱落的问题。

Description

封装基板及其制法
技术领域
本发明涉及一种封装基板，尤指一种提升产品可靠度的封装基板及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。为了提高多层电路板的布线精密度，业界遂发展出一种增层技术(Build-up)，也就是在一核心板(Core board)的两表面上分别以线路增层技术交互堆栈多层的介电层及线路层，并于该介电层中开设导电盲孔(Conductive via)以供上下层线路之间电性连接。进一步地，为了满足微型化(miniaturization)的需求，即发展出无核心板(coreless)的封装技术。
图1A至图1F为现有封装基板1的制法的剖面示意图。
如图1A所示，提供一承载件10，且形成导电层100于该承载件10的上、下侧。
如图1B所示，藉由该导电层100电镀形成第一线路层11于该承载件10的上、下侧，且该第一线路层11具有多个第一电性接触垫110。
如图1C所示，形成一介电层12于该承载件10及第一线路层11上。
如图1D所示，形成第二线路层13于该介电层12上，且该第二线路层13具有多个第二电性接触垫130，并形成多个导电盲孔14于该介电层12中，以电性连接该第一与第二线路层11,13。
如图1E所示，移除该承载件10，以露出该导电层100。
如图1F所示，移除该导电层100以露出该第一线路层11，再形成第一防焊层15于该介电层12及第一线路层11上，且该第一防焊层15形成有多个第一开孔150以露出该第一电性接触垫110及其周围的介电层12表面；又形成第二防焊层16于该介电层12及第二线路层13上，且该第二防焊层16形成有多个第二开孔160以露出该第二电性接触垫130。
然而，现有封装基板1于后续制程中，如图1G所示，当电子组件9欲藉由如焊锡材的导电组件18结合至该第一电性接触垫110时，该导电组件18与该第一电性接触垫110之间的接触面仅为单一平面（即该第一电性接触垫110的顶面110a），也就是接触面积小，致使两者的结合力不佳，因而容易发生脱落的问题，导致产品的信赖性降低。
此外，于另一种制程中，移除该承载件10后，会蚀刻第一线路层11，使该第一线路层11的表面低于该介电层12的表面，即该第一线路层11凹入该介电层12的表面(凹入深度约5um)，导致该导电组件18产生润焊不良(non-wetting)的问题，使该导电组件18卡在该介电层12的表面上而无法电性连接该第一电性接触垫110。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的目的为提供一种封装基板及其制法，使该导电组件与该导电凸部间的结合力提升，因而能避免发生脱落的问题。
封装基板，包括：介电层，其具有相对的第一表面与第二表面；第一线路层，其嵌埋于该介电层的第一表面上，且该第一线路层具有多个第一电性接触垫；以及导电凸部，其设于各该第一电性接触垫上并凸出该介电层的第一表面。
前述的封装基板中，该导电凸部的材质为铜。
本发明还提供一种封装基板的制法，其包括：提供一表面形成有第一线路层的承载件，且该第一线路层具有多个第一电性接触垫；形成一介电层于该承载件及第一线路层上，该介电层具有相对的第一表面与第二表面，且该第一表面接触结合该承载件；移除该承载件；以及形成导电凸部于各该第一电性接触垫上，使各该导电凸部凸出该介电层的第一表面。
前述的制法中，该承载件表面具有导电层，该第一线路层形成于该导电层上，且该导电凸部的制程包括：形成金属层于该导电层上；以及移除部分该金属层及其下的导电层，以形成该导电凸部于各该第一电性接触垫上。
于另一方式中，该承载件表面具有导电层，该第一线路层形成于该导电层上，且该导电凸部的制程包括：形成阻层于该导电层上，并形成对应该第一电性接触垫的多个开孔于该阻层上；形成金属层于各该开孔中；以及移除该阻层，以令该金属层作为该导电凸部。
于另一方式中，该导电凸部的制程包括：形成金属层于该介电层的第一表面与第一线路层上；以及移除部分该金属层，以形成该导电凸部于各该第一电性接触垫上。
于另一方式中，该承载件表面具有金属层，且移除该承载件之后，藉由移除部分该金属层，以形成该导电凸部于各该第一电性接触垫上。
前述的封装基板及其制法中，该导电凸部的宽度小于、等于或大于该第一电性接触垫的宽度。
前述的封装基板及其制法中，该第一线路层的表面齐平或低于该介电层的第一表面。
前述的封装基板及其制法中，还包括形成绝缘保护层于该介电层的第一表面及第一线路层上，且该绝缘保护层形成有多个露出该导电凸部的开孔。
另外，前述的封装基板及其制法中，还包括形成第二线路层于该介电层的第二表面上。又包括形成导电盲孔于该介电层中，以电性连接该第一与第二线路层。另包括形成绝缘保护层于该介电层的第二表面及第二线路层上，且该绝缘保护层形成有多个露出该第二线路层的开孔。
由上可知，本发明的封装基板及其制法，藉由该导电凸部凸出该介电层的第一表面，以于后续当电子组件欲藉由导电组件结合至该第一电性接触垫时，该导电组件与该导电凸部之间具有多个接触面(即该导电凸部的顶面与侧面)，使接触面积增加，所以相较于现有技术，该导电组件与该导电凸部间的结合力提升，因而能避免发生脱落的问题，藉以有效提升产品的信赖性。
此外，即使该第一线路层的表面低于该介电层的第一表面，藉由该导电凸部凸出该介电层的第一表面的设计，该导电组件不会产生润焊不良(non-wetting)的问题，使该导电组件不会卡在该介电层的第一表面上，所以该导电组件能有效接触该导电凸部而电性连接该第一电性接触垫。
附图说明
图1A至图1F为现有封装基板的制法的剖视示意图；
图1G为现有封装基板的后续制程的不同状况的剖视示意图；
图2A至图2G为本发明封装基板的制法的剖视示意图；其中，图2F’及图2F”为图2F的其它实施例，图2G’为图2G的其它实施例；
图2H为本发明封装基板的后续制程的剖视示意图；
图3A至图3B为图2F的详细制程的剖视示意图；
图4A至图4C为图2F的详细制程的剖视示意图；以及
图5A至图5B为图2F的详细制程的剖视示意图。
符号说明
1,2           封装基板           10,20     承载件
100,200,200’ 导电层             11,21     第一线路层
110,210       第一电性接触垫     110a,27a  顶面
12,22         介电层             13,23     第二线路层
130,230,230’ 第二电性接触垫
14,24         导电盲孔           15        第一防焊层
150,250       第一开孔           16        第二防焊层
160,260       第二开孔           18,28     导电组件
22a           第一表面           22b       第二表面
220           盲孔               25        第一绝缘保护层
26            第二绝缘保护层     27,27’,27”  导电凸部
27c           侧面               30,30’,40,40’,50  金属层
41,41’,51,51’   导电层         52         阻层
520           第三开孔           9          电子组件
h             凸出高度           R,D,D’,D” 宽度。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技艺的人士的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2G为本发明封装基板2的制法的剖面示意图。
图2A及图2B显示在一承载件20表面形成第一线路层21。
该承载件20为绝缘板、陶瓷板、铜箔基板或玻璃板等。于本实施例中，该承载件20的本体表面具有金属层，以作为导电层(seedlayer)200；若该承载件20为铜箔基板，则以铜箔作为导电层。
如图2B所示，利用该导电层200电镀形成第一线路层21于该承载件20的上、下侧，且该第一线路层21具有多个第一电性接触垫210。
如图2C所示，形成一介电层22于该承载件20及第一线路层21上，且该介电层22具有相对的第一表面22a与第二表面22b，该第一表面22a接触结合该承载件20。
于本实施例中，该介电层22的材质为预浸材(prepreg)。
如图2D所示，形成第二线路层23于该介电层22的第二表面22b上，且该第二线路层23具有多个第二电性接触垫230，并形成多个导电盲孔24于该介电层22中，以电性连接该第一与第二线路层21,23。
如图2E所示，移除该承载件20，以露出该导电层200。
如图2F所示，形成如铜块的导电凸部27于各该第一电性接触垫210上，使各该导电凸部27凸出该介电层22的第一表面22a，如凸出高度h为5um。之后，移除该导电层200，保留该导电凸部27下的导电层200’。
于本实施例中，该导电凸部27的宽度D等于该第一电性接触垫210的宽度R。
于其它实施例中，如图2F’所示，该导电凸部27’的宽度D’大于该第一电性接触垫210的宽度R；如图2F”所示，该导电凸部27”的宽度D”小于该第一电性接触垫210的宽度R。
如图2G所示，形成第一绝缘保护层25于该介电层22的第一表面22a及第一线路层21上，且该第一绝缘保护层25形成有多个第一开孔250以露出该导电凸部27及其周围的第一表面22a；又形成第二绝缘保护层26于该介电层22的第二表面22b及第二线路层23上，且该第二绝缘保护层26形成有多个第二开孔260以露出该第二电性接触垫230。
于另一实施例中，如图2G’所示，于移除该导电层200时，会移除该第一电性接触垫210的部分材质，使其凹入该介电层22的第一表面22a。
本发明封装基板2于后续制程中，如图2H所示，当电子组件9欲藉由如焊锡材的导电组件28结合至该第一电性接触垫210时，由于该第一电性接触垫210上具有导电凸部27，且该导电凸部27凸出该介电层22的第一表面22a，所以该导电组件28与该导电凸部27之间具有多个接触面(即该导电凸部27的顶面27a与侧面27c)，也就是接触面积大，致使相较于现有技术，两者的结合力较佳，因而不会发生脱落的问题，藉以能提升产品的信赖性。
此外，即使该第一线路层21的表面低于该介电层22的第一表面22a，仍可藉由该导电凸部27凸出该介电层22的第一表面22a的设计，该导电组件28不会产生润焊不良(non-wetting)的问题，使该导电组件28不会卡在该介电层22的第一表面22a上，所以该导电组件28能有效接触该导电凸部27而电性连接该第一电性接触垫。
另外，有关该导电凸部27的制程的方式繁多，以下简略三种方式，但不以此为限。
图3A至图3B为该导电凸部27的制程的第一实施例。
如图3A所示，贴附或电镀形成一金属层40于该导电层200上。
于本实施例中，该导电层200可为一层铜箔。
如图3B所示，进行图案化制程，蚀刻多余的金属层40及其下的导电层200，以形成该导电凸部27(即剩余的金属层40’与导电层200’)于各该第一电性接触垫210上。
图4A至图4C为该导电凸部27的制程的第二实施例。
如图4A所示，形成一阻层52于该导电层200上，并形成对应该第一电性接触垫210的第三开孔520于该阻层52上，以外露出该导电层200的部分表面。
于本实施例中，该导电层200可为一层铜箔。
如图4B所示，电镀形成金属层50于该第三开孔520中。
如图4C所示，移除该阻层52及其下的导电层200，以令该金属层50及其下的导电层200’(即剩余的导电层200’)作为该导电凸部27而形成于各该第一电性接触垫210上。
图5A至图5B为该导电凸部27的制程的第三实施例。
如图5A所示，移除该导电层200，再形成金属层30于该介电层22的第一表面22a与第一线路层21上。
于本实施例中，可贴一层铜箔作为金属层30；或者以电镀方式形成该金属层30。
于其它实施例中，蚀刻该导电层200后，会使该第一线路层21的表面略低于该介电层22的第一表面22a，即该第一线路层21凹入该介电层22的第一表面22a。
于另一实施例中，该承载件20表面未形成导电层200，而是直接形成金属层30，致使于移除该承载件20后，露出该金属层30，如图5A所示。
如图5B所示，进行图案化制程，蚀刻多余的金属层30，以形成该导电凸部27(即剩余的金属层30’)于各该第一电性接触垫210上。
本发明提供一种封装基板2，包括：具有相对的第一表面22a与第二表面22b的一介电层22、嵌埋于该介电层22的第一表面22a上的一第一线路层21、以及多个导电凸部27,27’,27”。
所述的第一线路层21具有多个第一电性接触垫210，且其表面齐平该介电层22的第一表面22a。
所述的导电凸部27,27’,27”设于各该第一电性接触垫210上并凸出该介电层22的第一表面22a，且该导电凸部27,27’,27”的宽度D,D’,D”小于、等于或大于该第一电性接触垫210的宽度R，又该导电凸部27,27’,27”的材质为铜。
于一实施例中，所述的封装基板2还包括第一绝缘保护层25，其设于该介电层22的第一表面22a及第一线路层21上，且该第一绝缘保护层25形成有多个第一开孔250以露出该导电凸部27,27’,27”及其周围的第一表面22a。
于一实施例中，所述的封装基板2还包括第二线路层23，其设于该介电层22的第二表面22b上，且该第二线路层23具有多个第二电性接触垫230及位于该介电层22中的多个导电盲孔24，以藉由该导电盲孔24电性连接该第一与第二线路层21,23。又包括第二绝缘保护层26，其设于该介电层22的第二表面22b及第二线路层23上，且该第二绝缘保护层26形成有多个第二开孔260以露出该第二电性接触垫230。
综上所述，本发明封装基板及其制法，主要藉由该第一电性接触垫上具有导电凸部，且该导电凸部凸出该介电层的第一表面，以于后续制程中，当电子组件欲藉由如焊锡材的导电组件结合至该第一电性接触垫时，该导电组件与该导电凸部之间具有较多的接触面，使两者的结合力较佳，因而能避免发生脱落的问题，藉以提升产品的信赖性。
此外，即使该第一线路层的表面低于该介电层的第一表面，藉由该导电凸部凸出该介电层的第一表面的设计，该导电组件不会产生润焊不良的问题，所以该导电组件能有效接触该导电凸部而电性连接该第一电性接触垫，藉以提升产品的信赖性。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (19)

1.一种封装基板，包括：
介电层，其具有相对的第一表面与第二表面；
第一线路层，其嵌埋于该介电层的第一表面上，且该第一线路层具有多个第一电性接触垫；以及
导电凸部，其设于各该第一电性接触垫上并凸出该介电层的第一表面。
2.根据权利要求1所述的封装基板，其特征在于，该第一线路层的表面齐平或低于该介电层的第一表面。
3.根据权利要求1所述的封装基板，其特征在于，该基板还包括绝缘保护层，其设于该介电层的第一表面及第一线路层上，且该绝缘保护层形成有多个露出该导电凸部的开孔。
4.根据权利要求1所述的封装基板，其特征在于，该基板还包括第二线路层，其设于该介电层的第二表面上。
5.根据权利要求4所述的封装基板，其特征在于，该基板还包括多个导电盲孔，其设于该介电层中，以电性连接该第一与第二线路层。
6.根据权利要求4所述的封装基板，其特征在于，该基板还包括绝缘保护层，其设于该介电层的第二表面及第二线路层上，且该绝缘保护层形成有多个露出该第二线路层的开孔。
7.根据权利要求1所述的封装基板，其特征在于，该导电凸部的宽度小于、等于或大于该第一电性接触垫的宽度。
8.根据权利要求1所述的封装基板，其特征在于，该导电凸部的材质为铜。
9.一种封装基板的制法，其包括：
提供一表面形成有第一线路层的承载件，且该第一线路层具有多个第一电性接触垫；
形成一介电层于该承载件及第一线路层上，该介电层具有相对的第一表面与第二表面，且该第一表面接触结合该承载件；
移除该承载件；以及
形成导电凸部于各该第一电性接触垫上，使各该导电凸部凸出该介电层的第一表面。
10.根据权利要求9所述的封装基板的制法，其特征在于，该第一线路层的表面齐平或低于该介电层的第一表面。
11.根据权利要求9所述的封装基板的制法，其特征在于，该承载件表面具有导电层，该第一线路层形成于该导电层上，且该导电凸部的制程包括：
形成金属层于该导电层上；以及
移除部分该金属层及其下的导电层，以形成该导电凸部于各该第一电性接触垫上。
12.根据权利要求9所述的封装基板的制法，其特征在于，该承载件表面具有导电层，该第一线路层形成于该导电层上，且该导电凸部的制程包括：
形成阻层于该导电层上，并形成对应该第一电性接触垫的多个开孔于该阻层上；
形成金属层于各该开孔中；以及
移除该阻层，以令该金属层作为该导电凸部。
13.根据权利要求9所述的封装基板的制法，其特征在于，该导电凸部的制程包括：
形成金属层于该介电层的第一表面与第一线路层上；以及
移除部分该金属层，以形成该导电凸部于各该第一电性接触垫上。
14.根据权利要求9所述的封装基板的制法，其特征在于，该承载件表面具有金属层，且移除该承载件之后，藉由移除部分该金属层，以形成该导电凸部于各该第一电性接触垫上。
15.根据权利要求9所述的封装基板的制法，其特征在于，该制法还包括形成绝缘保护层于该介电层的第一表面及第一线路层上，且该绝缘保护层形成有多个露出该导电凸部的开孔。
16.根据权利要求9所述的封装基板的制法，其特征在于，该制法还包括形成第二线路层于该介电层的第二表面上。
17.根据权利要求16所述的封装基板的制法，其特征在于，该制法还包括形成导电盲孔于该介电层中，以电性连接该第一与第二线路层。
18.根据权利要求16所述的封装基板的制法，其特征在于，该制法还包括形成绝缘保护层于该介电层的第二表面及第二线路层上，且该绝缘保护层形成有多个露出该第二线路层的开孔。
19.根据权利要求9所述的封装基板的制法，其特征在于，该导电凸部的宽度小于、等于或大于该第一电性接触垫的宽度。
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