TW201521167A - 封裝基板及其製法 - Google Patents

封裝基板及其製法 Download PDF

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TW201521167A
TW201521167A TW102143206A TW102143206A TW201521167A TW 201521167 A TW201521167 A TW 201521167A TW 102143206 A TW102143206 A TW 102143206A TW 102143206 A TW102143206 A TW 102143206A TW 201521167 A TW201521167 A TW 201521167A
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layer
conductive
package substrate
dielectric layer
electrical contact
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TW102143206A
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TWI525769B (zh
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何祈慶
蔡瀛洲
黃聖哲
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矽品精密工業股份有限公司
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Priority to TW102143206A priority Critical patent/TWI525769B/zh
Priority to CN201310666162.4A priority patent/CN104681531B/zh
Priority to US14/104,514 priority patent/US20150144384A1/en
Publication of TW201521167A publication Critical patent/TW201521167A/zh
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Publication of TWI525769B publication Critical patent/TWI525769B/zh
Priority to US15/293,883 priority patent/US20170033037A1/en
Priority to US15/293,858 priority patent/US9899235B2/en

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Abstract

一種封裝基板，係包括：介電層，係具有相對之第一表面與第二表面；第一線路層，係嵌埋於該介電層之第一表面上，且該第一線路層具有複數第一電性接觸墊；以及導電凸部，係設於各該第一電性接觸墊上並凸出該介電層之第一表面，以於後續當電子元件欲藉由導電元件結合至該第一電性接觸墊時，該導電元件與該導電凸部之間具有較多接觸面(即該導電凸部之頂面與側面)，使該導電元件與該導電凸部間的結合力提升，因而能避免發生脫落之問題。

Description

封裝基板及其製法
本發明係有關一種封裝基板，尤指一種提升產品可靠度之封裝基板及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了提高多層電路板之佈線精密度，業界遂發展出一種增層技術(Build-up)，亦即在一核心板(Core board)之兩表面上分別以線路增層技術交互堆疊多層之介電層及線路層，並於該介電層中開設導電盲孔(Conductive via)以供上下層線路之間電性連接。進一步地，為了滿足微型化(miniaturization)的需求，係發展出無核心板(coreless)之封裝技術。
第1A至1F圖係為習知封裝基板1之製法之剖面示意圖。
如第1A圖所示，提供一承載件10，且形成導電層100於該承載件10之上、下側。
如第1B圖所示，藉由該導電層100電鍍形成第一線路層11於該承載件10之上、下側，且該第一線路層11具有複數第一電性接觸墊110。
如第1C圖所示，形成一介電層12於該承載件10及第一線路 層11上。
如第1D圖所示，形成第二線路層13於該介電層12上，且該第二線路層13具有複數第二電性接觸墊130，並形成複數導電盲孔14於該介電層12中，以電性連接該第一與第二線路層11,13。
如第1E圖所示，移除該承載件10，以露出該導電層100。
如第1F圖所示，移除該導電層100以露出該第一線路層11，再形成第一防銲層15於該介電層12及第一線路層11上，且該第一防銲層15形成有複數第一開孔150以露出該第一電性接觸墊110及其周圍之介電層12表面；又形成第二防銲層16於該介電層12及第二線路層13上，且該第二防銲層16形成有複數第二開孔160以露出該第二電性接觸墊130。
惟，習知封裝基板1於後續製程中，如第1G圖所示，當電子元件9欲藉由如銲錫材之導電元件18結合至該第一電性接觸墊110時，該導電元件18與該第一電性接觸墊110之間的接觸面僅為單一平面(即該第一電性接觸墊110之頂面110a)，亦即接觸面積小，致使兩者之結合力不佳，因而容易發生脫落之問題，導致產品之信賴性降低。
再者，於另一種製程中，移除該承載件10後，會蝕刻第一線路層11，使該第一線路層11之表面低於該介電層12之表面，即該第一線路層11凹入該介電層12之表面(凹入深度約5um)，導致該導電元件18產生潤銲不良(non-wetting)之問題，使該導電元件18卡在該介電層12之表面上而無法電性連接該第一電性接觸墊110。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲 解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種封裝基板，係包括：介電層，係具有相對之第一表面與第二表面；第一線路層，係嵌埋於該介電層之第一表面上，且該第一線路層具有複數第一電性接觸墊；以及導電凸部，係設於各該第一電性接觸墊上並凸出該介電層之第一表面。
前述之封裝基板中，該導電凸部之材質係為銅。
本發明復提供一種封裝基板之製法，係包括：提供一表面形成有第一線路層之承載件，且該第一線路層具有複數第一電性接觸墊；形成一介電層於該承載件及第一線路層上，該介電層具有相對之第一表面與第二表面，且該第一表面係接觸結合該承載件；移除該承載件；以及形成導電凸部於各該第一電性接觸墊上，使各該導電凸部係凸出該介電層之第一表面。
前述之製法中，該承載件表面具有導電層，該第一線路層形成於該導電層上，且該導電凸部之製程係包括：形成金屬層於該導電層上；以及移除部分該金屬層及其下之導電層，以形成該導電凸部於各該第一電性接觸墊上。
於另一方式中，該承載件表面具有導電層，該第一線路層形成於該導電層上，且該導電凸部之製程係包括：形成阻層於該導電層上，並形成對應該第一電性接觸墊之複數開孔於該阻層上；形成金屬層於各該開孔中；以及移除該阻層，以令該金屬層作為該導電凸部。
於另一方式中，該導電凸部之製程係包括：形成金屬層於該 介電層之第一表面與第一線路層上；以及移除部分該金屬層，以形成該導電凸部於各該第一電性接觸墊上。
於另一方式中，該承載件表面具有金屬層，且移除該承載件之後，藉由移除部分該金屬層，以形成該導電凸部於各該第一電性接觸墊上。
前述之封裝基板及其製法中，該導電凸部之寬度係小於、等於或大於該第一電性接觸墊之寬度。
前述之封裝基板及其製法中，該第一線路層之表面齊平或低於該介電層之第一表面。
前述之封裝基板及其製法中，復包括形成絕緣保護層於該介電層之第一表面及第一線路層上，且該絕緣保護層形成有複數露出該導電凸部之開孔。
另外，前述之封裝基板及其製法中，復包括形成第二線路層於該介電層之第二表面上。又包括形成導電盲孔於該介電層中，以電性連接該第一與第二線路層。另包括形成絕緣保護層於該介電層之第二表面及第二線路層上，且該絕緣保護層形成有複數露出該第二線路層之開孔。
由上可知，本發明之封裝基板及其製法，係藉由該導電凸部凸出該介電層之第一表面，以於後續當電子元件欲藉由導電元件結合至該第一電性接觸墊時，該導電元件與該導電凸部之間具有複數接觸面(即該導電凸部之頂面與側面)，使接觸面積增加，故相較於習知技術，該導電元件與該導電凸部間的結合力提升，因而能避免發生脫落之問題，藉以有效提升產品之信賴性。
再者，即使該第一線路層之表面低於該介電層之第一表面， 藉由該導電凸部凸出該介電層之第一表面的設計，該導電元件不會產生潤銲不良(non-wetting)之問題，使該導電元件不會卡在該介電層之第一表面上，故該導電元件能有效接觸該導電凸部而電性連接該第一電性接觸墊。
1,2‧‧‧封裝基板
10,20‧‧‧承載件
100,200,200’‧‧‧導電層
11,21‧‧‧第一線路層
110,210‧‧‧第一電性接觸墊
110a,27a‧‧‧頂面
12,22‧‧‧介電層
13,23‧‧‧第二線路層
130,230,230’‧‧‧第二電性接觸墊
14,24‧‧‧導電盲孔
15‧‧‧第一防銲層
150,250‧‧‧第一開孔
16‧‧‧第二防銲層
160,260‧‧‧第二開孔
18,28‧‧‧導電元件
22a‧‧‧第一表面
22b‧‧‧第二表面
220‧‧‧盲孔
25‧‧‧第一絕緣保護層
26‧‧‧第二絕緣保護層
27,27’,27”‧‧‧導電凸部
27c‧‧‧側面
30,30’,40,40’,50‧‧‧金屬層
41,41’,51,51’‧‧‧導電層
52‧‧‧阻層
520‧‧‧第三開孔
9‧‧‧電子元件
h‧‧‧凸出高度
R,D,D’,D”‧‧‧寬度
第1A至1F圖係為習知封裝基板之製法的剖視示意圖；第1G圖係為習知封裝基板之後續製程的不同狀況之剖視示意圖；第2A至2G圖係為本發明封裝基板之製法的剖視示意圖；其中，第2F’及2F”圖係為第2F圖的其它態樣，第2G’圖係為第2G圖的其它態樣；第2H圖係為本發明封裝基板之後續製程的剖視示意圖；第3A至3B圖係為第2F圖之詳細製程的剖視示意圖；第4A至4C圖係為第2F圖之詳細製程的剖視示意圖；以及第5A至5B圖係為第2F圖之詳細製程的剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落 在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明封裝基板2之製法的剖面示意圖。
第2A及2B圖係顯示在一承載件20表面形成第一線路層21。
該承載件20係為絕緣板、陶瓷板、銅箔基板或玻璃板等。於本實施例中，該承載件20之本體表面係具有金屬層，以作為導電層(seed layer)200；若該承載件20為銅箔基板，則以銅箔作為導電層。
如第2B圖所示，利用該導電層200電鍍形成第一線路層21於該承載件20之上、下側，且該第一線路層21具有複數第一電性接觸墊210。
如第2C圖所示，形成一介電層22於該承載件20及第一線路層21上，且該介電層22具有相對之第一表面22a與第二表面22b，該第一表面22a係接觸結合該承載件20。
於本實施例中，該介電層22之材質係為預浸材(prepreg)。
如第2D圖所示，形成第二線路層23於該介電層22之第二表面22b上，且該第二線路層23具有複數第二電性接觸墊230，並形成複數導電盲孔24於該介電層22中，以電性連接該第一與第二線路層21,23。
如第2E圖所示，移除該承載件20，以露出該導電層200。
如第2F圖所示，形成如銅塊之導電凸部27於各該第一電性 接觸墊210上，使各該導電凸部27係凸出該介電層22之第一表面22a，如凸出高度h為5um。之後，移除該導電層200，保留該導電凸部27下之導電層200’。
於本實施例中，該導電凸部27之寬度D等於該第一電性接觸墊210之寬度R。
於其它實施例中，如第2F’圖所示，該導電凸部27’之寬度D’大於該第一電性接觸墊210之寬度R；如第2F”圖所示，該導電凸部27”之寬度D”小於該第一電性接觸墊210之寬度R。
如第2G圖所示，形成第一絕緣保護層25於該介電層22之第一表面22a及第一線路層21上，且該第一絕緣保護層25形成有複數第一開孔250以露出該導電凸部27及其周圍之第一表面22a；又形成第二絕緣保護層26於該介電層22之第二表面22b及第二線路層23上，且該第二絕緣保護層26形成有複數第二開孔260以露出該第二電性接觸墊230。
於另一實施例中，如第2G’圖所示，於移除該導電層200時，會移除該第一電性接觸墊210之部分材質，使其凹入該介電層22之第一表面22a。
本發明封裝基板2於後續製程中，如第2H圖所示，當電子元件9欲藉由如銲錫材之導電元件28結合至該第一電性接觸墊210時，由於該第一電性接觸墊210上具有導電凸部27，且該導電凸部27凸出該介電層22之第一表面22a，故該導電元件28與該導電凸部27之間具有複數接觸面(即該導電凸部27之頂面27a與側面27c)，亦即接觸面積大，致使相較於習知技術，兩者之結合力較佳，因而不會發生脫落之問題，藉以能提升產品之信賴性。
再者，即使該第一線路層21之表面低於該介電層22之第一表面22a，仍可藉由該導電凸部27凸出該介電層22之第一表面22a的設計，該導電元件28不會產生潤銲不良(non-wetting)之問題，使該導電元件28不會卡在該介電層22之第一表面22a上，故該導電元件28能有效接觸該導電凸部27而電性連接該第一電性接觸墊。
另外，有關該導電凸部27之製程之方式繁多，以下簡略三種方式，但不以此為限。
第3A至3B圖係為該導電凸部27之製程之第一實施例。
如第3A圖所示，貼附或電鍍形成一金屬層40於該導電層200上。
於本實施例中，該導電層200可為一層銅箔。
如第3B圖所示，進行圖案化製程，係蝕刻多餘之金屬層40及其下之導電層200，以形成該導電凸部27(即剩餘之金屬層40’與導電層200’)於各該第一電性接觸墊210上。
第4A至4C圖係為該導電凸部27之製程之第二實施例。
如第4A圖所示，形成一阻層52於該導電層200上，並形成對應該第一電性接觸墊210之第三開孔520於該阻層52上，以外露出該導電層200之部分表面。
於本實施例中，該導電層200可為一層銅箔。
如第4B圖所示，電鍍形成金屬層50於該第三開孔520中。
如第4C圖所示，移除該阻層52及其下之導電層200，以令該金屬層50及其下之導電層200’(即剩餘之導電層200’)作為該導電凸部27而形成於各該第一電性接觸墊210上。
第5A至5B圖係為該導電凸部27之製程之第三實施例。
如第5A圖所示，移除該導電層200，再形成金屬層30於該介電層22之第一表面22a與第一線路層21上。
於本實施例中，可貼一層銅箔作為金屬層30；或者以電鍍方式形成該金屬層30。
於其它實施例中，蝕刻該導電層200後，會使該第一線路層21之表面略低於該介電層22之第一表面22a，即該第一線路層21凹入該介電層22之第一表面22a。
於另一實施例中，該承載件20表面未形成導電層200，而是直接形成金屬層30，致使於移除該承載件20後，係露出該金屬層30，如第5A圖所示。
如第5B圖所示，進行圖案化製程，係蝕刻多餘之金屬層30，以形成該導電凸部27(即剩餘之金屬層30’)於各該第一電性接觸墊210上。
本發明提供一種封裝基板2，係包括：具有相對之第一表面22a與第二表面22b的一介電層22、嵌埋於該介電層22之第一表面22a上之一第一線路層21、以及複數導電凸部27,27’,27”。
所述之第一線路層21係具有複數第一電性接觸墊210，且其表面齊平該介電層22之第一表面22a。
所述之導電凸部27,27’,27”係設於各該第一電性接觸墊210上並凸出該介電層22之第一表面22a，且該導電凸部27,27’,27”之寬度D,D’,D”係小於、等於或大於該第一電性接觸墊210之寬度R，又該導電凸部27,27’,27”之材質係為銅。
於一實施例中，所述之封裝基板2復包括第一絕緣保護層 25，其設於該介電層22之第一表面22a及第一線路層21上，且該第一絕緣保護層25形成有複數第一開孔250以露出該導電凸部27,27’,27”及其周圍之第一表面22a。
於一實施例中，所述之封裝基板2復包括第二線路層23，係設於該介電層22之第二表面22b上，且該第二線路層23具有複數第二電性接觸墊230及位於該介電層22中之複數導電盲孔24，以藉由該導電盲孔24電性連接該第一與第二線路層21,23。又包括第二絕緣保護層26，係設於該介電層22之第二表面22b及第二線路層23上，且該第二絕緣保護層26形成有複數第二開孔260以露出該第二電性接觸墊230。
綜上所述，本發明封裝基板及其製法，主要藉由該第一電性接觸墊上具有導電凸部，且該導電凸部凸出該介電層之第一表面，以於後續製程中，當電子元件欲藉由如銲錫材之導電元件結合至該第一電性接觸墊時，該導電元件與該導電凸部之間具有較多之接觸面，使兩者之結合力較佳，因而能避免發生脫落之問題，藉以提升產品之信賴性。
再者，即使該第一線路層之表面低於該介電層之第一表面，藉由該導電凸部凸出該介電層之第一表面的設計，該導電元件不會產生潤銲不良之問題，故該導電元件能有效接觸該導電凸部而電性連接該第一電性接觸墊，藉以提升產品之信賴性。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
200‧‧‧導電層
21‧‧‧第一線路層
210‧‧‧第一電性接觸墊
22‧‧‧介電層
22a‧‧‧第一表面
22b‧‧‧第二表面
23‧‧‧第二線路層
24‧‧‧導電盲孔
27‧‧‧導電凸部
h‧‧‧凸出高度
D,R‧‧‧寬度

Claims (19)

  1. 一種封裝基板，係包括：介電層，係具有相對之第一表面與第二表面；第一線路層，係嵌埋於該介電層之第一表面上，且該第一線路層具有複數第一電性接觸墊；以及導電凸部，係設於各該第一電性接觸墊上並凸出該介電層之第一表面。
  2. 如申請專利範圍第1項所述之封裝基板，其中，該第一線路層之表面齊平或低於該介電層之第一表面。
  3. 如申請專利範圍第1項所述之封裝基板，復包括絕緣保護層，係設於該介電層之第一表面及第一線路層上，且該絕緣保護層形成有複數露出該導電凸部之開孔。
  4. 如申請專利範圍第1項所述之封裝基板，復包括第二線路層，係設於該介電層之第二表面上。
  5. 如申請專利範圍第4項所述之封裝基板，復包括複數導電盲孔，係設於該介電層中，以電性連接該第一與第二線路層。
  6. 如申請專利範圍第4項所述之封裝基板，復包括絕緣保護層，係設於該介電層之第二表面及第二線路層上，且該絕緣保護層形成有複數露出該第二線路層之開孔。
  7. 如申請專利範圍第1項所述之封裝基板，其中，該導電凸部之寬度係小於、等於或大於該第一電性接觸墊之寬度。
  8. 如申請專利範圍第1項所述之封裝基板，其中，該導電凸部之材質係為銅。
  9. 一種封裝基板之製法，係包括： 提供一表面形成有第一線路層之承載件，且該第一線路層具有複數第一電性接觸墊；形成一介電層於該承載件及第一線路層上，該介電層具有相對之第一表面與第二表面，且該第一表面係接觸結合該承載件；移除該承載件；以及形成導電凸部於各該第一電性接觸墊上，使各該導電凸部係凸出該介電層之第一表面。
  10. 如申請專利範圍第9項所述之封裝基板之製法，其中，該第一線路層之表面齊平或低於該介電層之第一表面。
  11. 如申請專利範圍第9項所述之封裝基板之製法，其中，該承載件表面具有導電層，該第一線路層形成於該導電層上，且該導電凸部之製程係包括：形成金屬層於該導電層上；以及移除部分該金屬層及其下之導電層，以形成該導電凸部於各該第一電性接觸墊上。
  12. 如申請專利範圍第9項所述之封裝基板之製法，其中，該承載件表面具有導電層，該第一線路層形成於該導電層上，且該導電凸部之製程係包括：形成阻層於該導電層上，並形成對應該第一電性接觸墊之複數開孔於該阻層上；形成金屬層於各該開孔中；以及移除該阻層，以令該金屬層作為該導電凸部。
  13. 如申請專利範圍第9項所述之封裝基板之製法，其中，該導電 凸部之製程係包括：形成金屬層於該介電層之第一表面與第一線路層上；以及移除部分該金屬層，以形成該導電凸部於各該第一電性接觸墊上。
  14. 如申請專利範圍第9項所述之封裝基板之製法，其中，該承載件表面具有金屬層，且移除該承載件之後，藉由移除部分該金屬層，以形成該導電凸部於各該第一電性接觸墊上。
  15. 如申請專利範圍第9項所述之封裝基板之製法，復包括形成絕緣保護層於該介電層之第一表面及第一線路層上，且該絕緣保護層形成有複數露出該導電凸部之開孔。
  16. 如申請專利範圍第9項所述之封裝基板之製法，復包括形成第二線路層於該介電層之第二表面上。
  17. 如申請專利範圍第16項所述之封裝基板之製法，復包括形成導電盲孔於該介電層中，以電性連接該第一與第二線路層。
  18. 如申請專利範圍第16項所述之封裝基板之製法，復包括形成絕緣保護層於該介電層之第二表面及第二線路層上，且該絕緣保護層形成有複數露出該第二線路層之開孔。
  19. 如申請專利範圍第9項所述之封裝基板之製法，其中，該導電凸部之寬度係小於、等於或大於該第一電性接觸墊之寬度。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI529883B (zh) * 2014-05-09 2016-04-11 矽品精密工業股份有限公司 封裝堆疊結構及其製法暨無核心層式封裝基板及其製法
KR102411996B1 (ko) * 2015-05-29 2022-06-22 삼성전기주식회사 패키지 기판 및 그 제조 방법
TWI624011B (zh) * 2015-06-29 2018-05-11 矽品精密工業股份有限公司 封裝結構及其製法
US10276402B2 (en) * 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof
CN108022897A (zh) 2016-11-01 2018-05-11 财团法人工业技术研究院 封装结构及其制作方法
CN108022896A (zh) 2016-11-01 2018-05-11 财团法人工业技术研究院 一种芯片封装结构及其制作方法
CN108242407A (zh) * 2016-12-23 2018-07-03 碁鼎科技秦皇岛有限公司 封装基板、封装结构及其制作方法
TWI604542B (zh) * 2017-01-12 2017-11-01 矽品精密工業股份有限公司 封裝基板及其製法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6394819B1 (en) 1998-10-29 2002-05-28 The Whitaker Corporation Dielectric member for absorbing thermal expansion and contraction at electrical interfaces
JP3635219B2 (ja) * 1999-03-11 2005-04-06 新光電気工業株式会社 半導体装置用多層基板及びその製造方法
US6759319B2 (en) * 2001-05-17 2004-07-06 Institute Of Microelectronics Residue-free solder bumping process
TW558782B (en) * 2002-09-10 2003-10-21 Siliconware Precision Industries Co Ltd Fabrication method for strengthened flip-chip solder bump
TWI235469B (en) 2003-02-07 2005-07-01 Siliconware Precision Industries Co Ltd Thermally enhanced semiconductor package with EMI shielding
US7132303B2 (en) 2003-12-18 2006-11-07 Freescale Semiconductor, Inc. Stacked semiconductor device assembly and method for forming
JP4541763B2 (ja) * 2004-01-19 2010-09-08 新光電気工業株式会社 回路基板の製造方法
TWI256146B (en) * 2005-07-21 2006-06-01 Siliconware Precision Industries Co Ltd Sensor semiconductor device and fabrication method thereof
JP4334005B2 (ja) * 2005-12-07 2009-09-16 新光電気工業株式会社 配線基板の製造方法及び電子部品実装構造体の製造方法
TWI334643B (en) * 2007-04-11 2010-12-11 Nan Ya Printed Circuit Board Corp Solder pad and method of making the same
CN101290917B (zh) * 2007-04-17 2011-08-31 南亚电路板股份有限公司 焊接垫结构
CN101409238A (zh) * 2007-10-11 2009-04-15 全懋精密科技股份有限公司 无核层封装基板的制作方法
CN101989587A (zh) * 2009-07-30 2011-03-23 全懋精密科技股份有限公司 电路板的电性连接结构及电路板装置
CN101989593B (zh) * 2009-07-30 2012-12-12 欣兴电子股份有限公司 封装基板及其制法及封装结构
CN102054814B (zh) * 2009-11-06 2012-07-25 欣兴电子股份有限公司 无核心层封装基板及其制法
CN102054709B (zh) * 2009-11-06 2012-10-10 欣兴电子股份有限公司 封装基板的制法
CN102054710B (zh) * 2009-11-06 2013-01-16 欣兴电子股份有限公司 无核层封装基板的制法
JP2011165862A (ja) * 2010-02-09 2011-08-25 Sony Corp 半導体装置、チップ・オン・チップの実装構造、半導体装置の製造方法及びチップ・オン・チップの実装構造の形成方法
US8410604B2 (en) * 2010-10-26 2013-04-02 Xilinx, Inc. Lead-free structures in a semiconductor device
TWI495051B (zh) * 2011-07-08 2015-08-01 Unimicron Technology Corp 無核心層之封裝基板及其製法
TWI560835B (en) * 2011-11-07 2016-12-01 Siliconware Precision Industries Co Ltd Package substrate and fabrication method thereof
CN103137570B (zh) * 2011-11-29 2016-02-10 先进封装技术私人有限公司 基板结构、半导体封装元件及基板结构的制造方法
JP2013149948A (ja) * 2011-12-20 2013-08-01 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
TWI467718B (zh) * 2011-12-30 2015-01-01 Ind Tech Res Inst 凸塊結構以及電子封裝接點結構及其製造方法
TWI517274B (zh) * 2012-03-21 2016-01-11 矽品精密工業股份有限公司 晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法

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