CN106252299A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN106252299A
CN106252299A CN201510508330.6A CN201510508330A CN106252299A CN 106252299 A CN106252299 A CN 106252299A CN 201510508330 A CN201510508330 A CN 201510508330A CN 106252299 A CN106252299 A CN 106252299A
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CN
China
Prior art keywords
chip
semiconductor device
illusory
layer
active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510508330.6A
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English (en)
Inventor
施信益
施能泰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Inotera Memories Inc
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Publication date
Application filed by Inotera Memories Inc filed Critical Inotera Memories Inc
Priority to CN202110549348.6A priority Critical patent/CN113380727A/zh
Publication of CN106252299A publication Critical patent/CN106252299A/zh
Pending legal-status Critical Current

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Abstract

本发明公开了一种半导体器件，包括一中介层，具有一第一面及相对于第一面的第二面；至少一有源芯片，通过多个第一凸块安装到所述第一面的一芯片接合区域内；至少一虚设芯片，安装到所述第一面的所述芯片接合区域旁的一周边区域内；一成型模料，设置在所述第一面上，并且所述成型模料覆盖所述至少一有源芯片与所述至少一虚设芯片；以及多个焊接凸块，设置在所述第二面上。

Description

半导体器件
技术领域
本发明属于半导体封装领域，特别是涉及一种无衬底或无穿硅通孔(through silicon via,TSV)的半导体器件。
背景技术
半导体封装领域中所熟知的扇出晶圆级封装(FOWLP)，是通过位于衬底上的重布线层(RDL)，例如位于具有穿硅通孔(TSV)的衬底，将原本半导体晶粒的接垫重新布线分配到一较大的区域。
重布线层是在晶圆表面上形成介电层与金属导线的叠层，将芯片原本的输入/输出(I/O)接垫重新布线分配到一个间距较宽松的布局范围。上述重布线的制作通常使用薄膜聚合物，例如苯并环丁稀(Benzocyclobutene,BCB)、聚亚酰胺(polyimind,PI)，或其他有机聚合物作为介电层材料，再以金属化工艺，例如铝或铜，形成金属导线，将芯片周围的接垫重新布线分配成阵列状连接垫。
由于工艺繁复，具有穿硅通孔的中介层衬底成本较高，因此，使用具有穿硅通孔中介层的扇出晶圆级封装也会比较昂贵，并不利于特定的应用场合。
此外，晶圆级封装工艺中，通常会在晶圆及安装在晶圆上的芯片表面覆盖一相对较厚的成型模料。此成型模料与集成电路衬底的热膨胀系数(CTE)差异，容易导致封装翘曲变形，也使得封装整体的厚度增加。晶圆翘曲一直是本领域关注的问题。
晶圆翘曲使芯片与晶圆间的接合不易维持，使“芯片对晶圆接合”(chip towafer)的组装失败。翘曲问题在大尺寸晶圆上更是明显，特别是对于具有小间距重布线层的晶圆级半导体封装制，问题更为严重。因此，业界仍需要一个改良的晶圆级封装方法，可以解决上述现有技术的问题。
发明内容
本发明的目的在于提供一种改良的半导体器件，可减少中介层上的成型模料用量，因而改善成型后的翘曲问题。
根据本发明提供的半导体器件，包括一中介层，具有一第一面及相对于第一面的第二面；至少一有源芯片，通过多个第一凸块安装到所述第一面的一芯片接合区域内；至少一虚设芯片，安装到所述第一面的所述芯片接合区域旁的一周边区域内；一成型模料，设置在所述第一面上，并且所述成型模料覆盖所述至少一有源芯片与所述至少一虚设芯片；以及多个焊接凸块，设置在所述第二面上。
根据本发明一实施例，所述虚设芯片通过多个设置在所述周边区域内的虚设接垫上的第二凸块安装到所述第一面上。
根据本发明另一实施例，所述虚设芯片直接通过一黏着剂安装到所述第一面上。
总之，本领域的技术人员读完接下来本发明优选实施例的详细说明与附图后，均可了解本发明的目的。
附图说明
图1到图8为根据本发明一实施例使用无衬底或无穿硅通孔的中介层制作一晶圆级封装的方法的示意性剖面图，其中:
图1到图7为示意性剖面图，为本发明一实施例的晶圆级封装工艺的中间产物；
图8为俯视图，为有源芯片与虚设芯片在重布线层上的布局；
图9到图13为根据本发明另一实施例使用无衬底或无穿硅通孔的中介层制作一晶圆级封装的方法的示意性剖面图。
其中，附图标记说明如下：
10、10a 晶圆级封装
102 芯片接合区域
104 周边区域
300 载板
301 无穿硅通孔的中介层
310 钝化层
410 重布线层
412 介电层
414 金属层
430 黏着剂
500 成型模料
520 焊接凸块
415/415a/ 凸块垫
415b 虚设接垫
416/416a/416b 凸块
420a 覆晶芯片
420b 虚设芯片
具体实施方式
接下来的详细叙述须参考相关附图所示内容，用来说明可依据本发明具体实行的实施例。这些实施例提供足够的细节，可使此领域中的技术人员充分了解并具体实行本发明。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改应用在其他实施例上。
因此，接下来的详细说明并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具有同等意义者，也应属本发明涵盖的范围。
本发明实施例所参考的附图为示意图，并未按比例绘制，而相同或类似的特征通常以相同的附图标记描述。在本说明书中，“晶粒”、“半导体芯片”与“半导体晶粒”具有相同含意，可交替使用。
在本说明书中，“晶圆”与“基板”意指任何包括一暴露面，可依据本发明实施例所示在其上沉积材料，制作集成电路结构的结构物，例如重布线层。须了解的是“基板”包括半导体晶圆，但并不限于此。"基板"在工艺中也意指包括制作于其上的材料层的半导体结构物。
请参考图1到图8，为根据本发明一实施例使用无衬底或无穿硅通孔的中介层制作一晶圆级封装的方法的示意性剖面图。
如图1所示，预备一载板300。载板300例如为可卸式衬底材料，可以包括一黏着层(图未示)。载板300的上表面上包括至少一介电层或钝化层310。钝化层310可包括有机材料，例如聚亚酰胺(polyimide,PI)，或无机材料，例如氮化硅、氧化硅或类似的材料。
接着，如图2所示，在钝化层310上方形成重布线层(RDL)410。重布线层410包括至少一介电层412与至少一金属层414。介电层412可包括有机材料，例如聚亚酰胺(polyimide,PI)，或无机材料，例如氮化硅、氧化硅或类似的材料，但不限于此。金属层414可包括铝、铜、钨、钛、氮化钛或类似的材料。
根据所述实施例，金属层414可包括多个凸块垫415a和虚设接垫415b，自介电层412的上表面暴露出来。凸块垫415a设置在芯片接合区域102内，而虚设接垫415b设置在芯片接合区域102外，例如设置在芯片接合区域102的周边区域104内。
根据所述实施例，虚设接垫415b为孤立、闲置的接垫，未与重布线层410的金属导线电性连接。换句话说，当芯片封装体在操作模式时，不会有信号通过虚设接垫415b到其他地方。
如图3所示，在重布线层410上形成多个凸块416a与416b，例如微凸块，作为后续连接使用。凸块416a可直接形成在金属层414个别的凸块垫415a上。凸块416b可直接形成在金属层414个别的虚设接垫415b上。在某些实施例中，形成凸块416a与416b之前，可以在重布线层410上形成一钝化层或介电层(图未示)。
如图4所示，形成凸块416a与416b之后，个别的有源芯片420a以有源面朝下面对重布线层410，通过凸块416a安装到重布线层410上，形成“芯片对晶圆接合”的堆叠结构。这些个别的有源芯片420a为具有特定功能的有源集成电路芯片，例如绘图处理器(GPU)、中央处理器(CPU)、存储器芯片等等。
根据所述实施例，虚设芯片420b通过凸块416b安装到芯片接合区域102旁的周边区域104内。图8为有源芯片420a与虚设芯片420b在重布线层上的布局方式。虚设芯片420b可以是硅芯片、晶粒、或尺寸与有源芯片420a相似的器件，但并不限于此。须了解的是虚设芯片420b也可包括其他材料，例如金属、玻璃或陶瓷。
上述步骤完成后，可选择性的在有源芯片420a与虚设芯片420b下方填充底胶(图未示)。随后，进行热处理，使凸块416a和416b回焊。
如图5所示，晶粒接合完成后，接着在上方覆盖一成型模料500。成型模料500覆盖住安装在重布线层上的有源芯片420a与虚设芯片420b，同时也覆盖住重布线层410的上表面。成型模料500随后会通过一固化工艺使之固化。成型模料500例如为环氧树脂与二氧化硅填充剂的混和物，但并不限于此。
接着，可选择性的研磨移除部分成型模料500的上部，使有源芯片420a与虚设芯片420b的上表面暴露出来。
由于芯片接合区域102的周边区域104中大多都具有虚设芯片420b，因此可减少成形模料500的用量，降低甚至完全避免衬底或晶圆发生翘曲变形的情况。根据所述实施例，虚设芯片420b也可称之为翘曲控制虚设芯片。
如图6所示，形成成型模料500后，再将载板300剥离，使钝化层310暴露出来，形成无穿硅通孔的中介层301。例如，可利用激光剥离技术或紫外光照射技术来剥离载板300，但不限于此。
剥离载板300时，可提供另一个暂时性的载板(图未示)固定于成型模料500上方。载板300剥离完成后，接着在钝化层310形成开口，使金属层的焊接垫暴露出来，然后在个别焊接垫上形成焊接凸块或焊接球520。
随后，如图7所示，进行切割工艺，分隔出个别的晶圆级封装10。
请参考图9到图13，为根据本发明另一实施例使用无衬底或无穿硅通孔的中介层制作一晶圆级封装的方法的示意性剖面图，其中仍沿用相同的附图标记，表示相似的区域、材料层或器件。
请参考图9，如同前一个实施例，在钝化层310上方形成重布线层410。重布线层410包括至少一介电层412与至少一金属层414。介电层412可包括有机材料，例如聚亚酰胺(PI)，或无机材料，例如氮化硅、氧化硅或类似的材料，但不限于此。金属层414可包括铝、铜、钨、钛、氮化钛或类似的材料。
根据所述实施例，金属层414包括多个凸块垫415，自介电层412的上表面暴露出来。凸块垫415位于芯片接合区域102内。大致上，芯片接合区域102以外的周边区域104不具有凸块垫。重布线层410包括多个凸块416，例如微凸块，以供后续连接使用。凸块416可直接形在金属层414个别的凸块垫415上。
如图10所示，形成凸块416后，个别的有源芯片420a以有源面朝下面对重布线层410，通过凸块416安装到重布线层410上，形成“芯片对晶圆接合”的堆叠结构。可选择性的在有源芯片420a下方填充底胶(图未示)。随后，进行热处理，使凸块416回焊。
根据所述实施例，虚设芯片420b通过黏着剂430，直接固定在芯片接合区域102外的周边区域104的重布线层410的介电层412上。
如图11所示，晶粒接合完成后，接着在上方覆盖一成型模料500。成型模料500覆盖住安装在重布线层上的有源芯片420a和虚设芯片420b，同时也覆盖住重布线层410的上表面。成型模料500随后会通过一固化工艺使之固化。后续，可选择性的研磨移除部分成型模料500的上部，使有源芯片420a与虚设芯片420b的上表面暴露出来。
如图12所示，形成成型模料500后，再将载板300剥离，使钝化层310暴露出来，形成无穿硅通孔的中介层301。例如，可利用激光剥离技术或紫外光照射技术来剥离载板300，但不限于此。
剥离载板300时，可以提供另一个暂时性的载板(图未示)固定于成型模料500上方。载板300剥离完成后，接着在钝化层310形成开口，使金属层的焊接垫暴露出来，然后在个别焊接垫上形成焊接凸块或焊接球520。
随后，如图13所示，进行切割工艺，分隔出个别的晶圆级封装10a。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种半导体器件，其特征在于，包括:
一中介层，具有一第一面及相对于第一面的第二面；
至少一有源芯片，通过多个第一凸块安装到所述第一面的一芯片接合区域内；
至少一虚设芯片，安装到所述第一面的所述芯片接合区域旁的一周边区域内；
一成型模料，设置在所述第一面上，并且所述成型模料覆盖至少一所述有源芯片与至少一所述虚设芯片；以及
多个焊接凸块，设置在所述第二面上。
2.根据权利要求1所述的半导体器件，其特征在于，所述中介层包括一重布线层。
3.根据权利要求2所述的半导体器件，其特征在于，所述重布线层包括至少一介电层与至少一金属层。
4.根据权利要求1所述的半导体器件，其特征在于，所述中介层不包括一穿硅通孔。
5.根据权利要求1所述的半导体器件，其特征在于，所述有源芯片为一具有特定功能的有源集成电路芯片。
6.根据权利要求5所述的半导体器件，其特征在于，所述有源芯片包括一绘图处理器、一中央处理器，或一存储器芯片。
7.根据权利要求1所述的半导体器件，其特征在于，所述虚设芯片为一虚设硅芯片。
8.根据权利要求1所述的半导体器件，其特征在于，所述虚设芯片通过多个设置在所述周边区域的虚设接垫上的第二凸块安装到所述第一面上。
9.根据权利要求1所述的半导体器件，其特征在于，所述虚设芯片通过一黏着剂直接安装到所述第一面上。
10.根据权利要求1所述的半导体器件，其特征在于，另包括一钝化层位于所述第二面上。
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108364932A (zh) * 2017-01-26 2018-08-03 日月光半导体制造股份有限公司 半导体封装结构
CN108695267A (zh) * 2017-03-30 2018-10-23 台湾积体电路制造股份有限公司 封装结构
CN109390292A (zh) * 2017-08-11 2019-02-26 矽品精密工业股份有限公司 电子封装件及其制法
CN109585471A (zh) * 2017-09-29 2019-04-05 三星电子株式会社 半导体封装和图像传感器
CN110707049A (zh) * 2018-07-10 2020-01-17 三星电子株式会社 包括用于控制翘曲的通道的半导体芯片模块及其制造方法
WO2020172948A1 (zh) * 2019-02-27 2020-09-03 中芯集成电路（宁波）有限公司 Cmos图像传感器封装模块及其形成方法、摄像装置
CN111668178A (zh) * 2019-03-08 2020-09-15 力成科技股份有限公司 封装结构及其制作方法
CN111863633A (zh) * 2019-04-25 2020-10-30 深圳市环基实业有限公司 一种封装载板、封装体及其工艺
WO2021097814A1 (zh) * 2019-11-22 2021-05-27 华为技术有限公司 芯片封装、电子设备及芯片封装制备方法
CN113555351A (zh) * 2020-04-23 2021-10-26 瑞昱半导体股份有限公司 半导体封装
WO2024065992A1 (zh) * 2022-09-27 2024-04-04 武汉新芯集成电路制造有限公司 芯片封装方法及半导体封装结构
CN117954335A (zh) * 2024-03-22 2024-04-30 甬矽半导体(宁波)有限公司 基于重构晶圆的封装方法和基于重构晶圆的封装结构

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10043769B2 (en) 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
US9916999B2 (en) 2015-06-04 2018-03-13 Micron Technology, Inc. Methods of fabricating a semiconductor package structure including at least one redistribution layer
US9704790B1 (en) * 2016-03-14 2017-07-11 Micron Technology, Inc. Method of fabricating a wafer level package
US9922964B1 (en) * 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US10529690B2 (en) * 2016-11-14 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10163802B2 (en) * 2016-11-29 2018-12-25 Taiwan Semicondcutor Manufacturing Company, Ltd. Fan-out package having a main die and a dummy die, and method of forming
US10297471B2 (en) 2016-12-15 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out structure and method of fabricating the same
US9865567B1 (en) * 2017-02-02 2018-01-09 Xilinx, Inc. Heterogeneous integration of integrated circuit device and companion device
US10497689B2 (en) * 2017-08-04 2019-12-03 Mediatek Inc. Semiconductor package assembly and method for forming the same
US10515912B2 (en) 2017-09-24 2019-12-24 Intel Corporation Integrated circuit packages
KR101901711B1 (ko) * 2017-09-27 2018-09-27 삼성전기 주식회사 팬-아웃 반도체 패키지
US10665582B2 (en) * 2017-11-01 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor package structure
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10672820B2 (en) 2017-11-23 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonded structure
KR102450580B1 (ko) 2017-12-22 2022-10-07 삼성전자주식회사 금속 배선 하부의 절연층 구조를 갖는 반도체 장치
KR102397902B1 (ko) * 2018-01-29 2022-05-13 삼성전자주식회사 반도체 패키지
US11101260B2 (en) * 2018-02-01 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a dummy die of an integrated circuit having an embedded annular structure
US10699980B2 (en) * 2018-03-28 2020-06-30 Intel IP Corporation Fan out package with integrated peripheral devices and methods
US10510645B2 (en) * 2018-04-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Planarizing RDLs in RDL-first processes through CMP process
US11004803B2 (en) * 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
US10790210B2 (en) * 2018-07-31 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US10629507B1 (en) * 2018-11-23 2020-04-21 Dialog Semiconductor (Uk) Limited System in package (SIP)
EP3671833A1 (en) * 2018-12-20 2020-06-24 IMEC vzw A method for packaging semiconductor dies
US11380614B2 (en) 2018-12-26 2022-07-05 AP Memory Technology Corp. Circuit assembly
US11672111B2 (en) 2018-12-26 2023-06-06 Ap Memory Technology Corporation Semiconductor structure and method for manufacturing a plurality thereof
US10811402B2 (en) 2018-12-26 2020-10-20 AP Memory Technology Corp. Memory device and microelectronic package having the same
US11417628B2 (en) * 2018-12-26 2022-08-16 Ap Memory Technology Corporation Method for manufacturing semiconductor structure
US11158552B2 (en) 2018-12-26 2021-10-26 AP Memory Technology Corp. Semiconductor device and method to manufacture the same
US10861799B1 (en) * 2019-05-17 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy die placement without backside chipping
CN112185930B (zh) * 2019-07-05 2024-05-10 三星电子株式会社 具有虚设焊盘的半导体封装
KR20210005436A (ko) * 2019-07-05 2021-01-14 삼성전자주식회사 반도체 패키지
US11901333B2 (en) * 2019-10-08 2024-02-13 Intel Corporation No mold shelf package design and process flow for advanced package architectures
WO2021068221A1 (en) 2019-10-12 2021-04-15 Yangtze Memory Technologies Co., Ltd. Semiconductor devices having interposer structure and methods thereof
KR20210059417A (ko) 2019-11-15 2021-05-25 삼성전자주식회사 보강 구조물을 갖는 반도체 패키지
TWI768294B (zh) * 2019-12-31 2022-06-21 力成科技股份有限公司 封裝結構及其製造方法
US20210217707A1 (en) * 2020-01-10 2021-07-15 Mediatek Inc. Semiconductor package having re-distribution layer structure on substrate component
TWI739413B (zh) * 2020-05-04 2021-09-11 力成科技股份有限公司 半導體裝置及其製造方法
US11282756B2 (en) * 2020-08-17 2022-03-22 Taiwan Semiconductor Manufacturing Company Limited Organic interposer including stress-resistant bonding structures and methods of forming the same
US20220157777A1 (en) * 2020-11-13 2022-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package having dummy dies and method of forming the same
US11515268B2 (en) * 2021-03-05 2022-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11855003B2 (en) * 2021-05-13 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
TWI768970B (zh) 2021-06-17 2022-06-21 力晶積成電子製造股份有限公司 晶圓堆疊結構及其製造方法
US20230063692A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit packages and methods of forming the same
TWI763601B (zh) * 2021-10-13 2022-05-01 友達光電股份有限公司 封裝結構
CN117790424A (zh) * 2024-02-23 2024-03-29 甬矽半导体(宁波)有限公司 扇出型封装结构和扇出型封装结构的制备方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020060084A1 (en) * 2001-12-11 2002-05-23 Hilton Robert M. Flip-chip package with underfill dam that controls stress at chip edges
US20060249852A1 (en) * 2005-05-03 2006-11-09 Siliconware Precision Industries Co., Ltd. Flip-chip semiconductor device
JP2008300390A (ja) * 2007-05-29 2008-12-11 Renesas Technology Corp 半導体装置
US20090224401A1 (en) * 2008-03-04 2009-09-10 Elpida Memory Inc. Semiconductor device and manufacturing method thereof
CN102082102A (zh) * 2009-11-25 2011-06-01 新科金朋有限公司 形成柔性应力消除缓冲区的半导体器件和方法
US20110304016A1 (en) * 2010-06-09 2011-12-15 Shinko Electric Industries Co., Ltd. Wiring board, method of manufacturing the same, and semiconductor device
CN103117261A (zh) * 2011-11-16 2013-05-22 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN103325696A (zh) * 2012-03-21 2013-09-25 矽品精密工业股份有限公司 晶圆级半导体封装件的制法及其晶圆级封装基板的制法
CN104025288A (zh) * 2011-12-29 2014-09-03 Nepes株式会社 半导体封装及其制造方法
CN104078451A (zh) * 2013-03-29 2014-10-01 英特尔公司 用于射频无源件和天线的方法、设备和材料
CN104733402A (zh) * 2013-12-19 2015-06-24 矽品精密工业股份有限公司 半导体封装结构及其制法

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW462120B (en) * 2000-11-10 2001-11-01 Siliconware Precision Industries Co Ltd Tape carrier type semiconductor package structure
JP4217388B2 (ja) * 2001-06-26 2009-01-28 株式会社東芝 半導体チップ及び半導体モジュール
US7626829B2 (en) * 2004-10-27 2009-12-01 Ibiden Co., Ltd. Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board
TW201141328A (en) * 2005-06-13 2011-11-16 Ibiden Co Ltd Printed wiring board
US20090008777A1 (en) * 2007-07-06 2009-01-08 Advanced Chip Engineering Technology Inc. Inter-connecting structure for semiconductor device package and method of the same
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
JP2009170459A (ja) * 2008-01-10 2009-07-30 Panasonic Corp 半導体集積回路装置の設計方法、設計装置および半導体集積回路装置
JP4828559B2 (ja) * 2008-03-24 2011-11-30 新光電気工業株式会社 配線基板の製造方法及び電子装置の製造方法
KR101535223B1 (ko) * 2008-08-18 2015-07-09 삼성전자주식회사 테이프 배선 기판, 칩-온-필름 패키지 및 장치 어셈블리
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8531021B2 (en) * 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
US8778737B2 (en) * 2011-10-31 2014-07-15 International Business Machines Corporation Flattened substrate surface for substrate bonding
US8779599B2 (en) * 2011-11-16 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages including active dies and dummy dies and methods for forming the same
US9000876B2 (en) * 2012-03-13 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Inductor for post passivation interconnect
JP5977051B2 (ja) * 2012-03-21 2016-08-24 新光電気工業株式会社 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
US9685350B2 (en) * 2013-03-08 2017-06-20 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB
US8987915B1 (en) * 2013-08-29 2015-03-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9093337B2 (en) * 2013-09-27 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for controlling warpage in packaging
US9224697B1 (en) * 2013-12-09 2015-12-29 Xilinx, Inc. Multi-die integrated circuits implemented using spacer dies
JP6279717B2 (ja) * 2014-04-14 2018-02-14 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9691686B2 (en) * 2014-05-28 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor device
US9799622B2 (en) * 2014-06-18 2017-10-24 Dyi-chung Hu High density film for IC package
TWI549235B (zh) * 2014-07-03 2016-09-11 矽品精密工業股份有限公司 封裝結構及其製法與定位構形
KR102198858B1 (ko) * 2014-07-24 2021-01-05 삼성전자 주식회사 인터포저 기판을 갖는 반도체 패키지 적층 구조체
US9646955B2 (en) * 2014-09-05 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and methods of forming packages
US9786623B2 (en) * 2015-03-17 2017-10-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming PoP semiconductor device with RDL over top package
US9613931B2 (en) * 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US10043769B2 (en) 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
US9449953B1 (en) * 2015-10-08 2016-09-20 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
US9607967B1 (en) * 2015-11-04 2017-03-28 Inotera Memories, Inc. Multi-chip semiconductor package with via components and method for manufacturing the same
US9922964B1 (en) * 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US10529690B2 (en) * 2016-11-14 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10256203B2 (en) * 2017-07-27 2019-04-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and semiconductor package
US10431517B2 (en) * 2017-08-25 2019-10-01 Advanced Micro Devices, Inc. Arrangement and thermal management of 3D stacked dies
KR102397902B1 (ko) * 2018-01-29 2022-05-13 삼성전자주식회사 반도체 패키지
US10790210B2 (en) * 2018-07-31 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020060084A1 (en) * 2001-12-11 2002-05-23 Hilton Robert M. Flip-chip package with underfill dam that controls stress at chip edges
US20060249852A1 (en) * 2005-05-03 2006-11-09 Siliconware Precision Industries Co., Ltd. Flip-chip semiconductor device
JP2008300390A (ja) * 2007-05-29 2008-12-11 Renesas Technology Corp 半導体装置
US20090224401A1 (en) * 2008-03-04 2009-09-10 Elpida Memory Inc. Semiconductor device and manufacturing method thereof
CN102082102A (zh) * 2009-11-25 2011-06-01 新科金朋有限公司 形成柔性应力消除缓冲区的半导体器件和方法
US20110304016A1 (en) * 2010-06-09 2011-12-15 Shinko Electric Industries Co., Ltd. Wiring board, method of manufacturing the same, and semiconductor device
CN103117261A (zh) * 2011-11-16 2013-05-22 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN104025288A (zh) * 2011-12-29 2014-09-03 Nepes株式会社 半导体封装及其制造方法
CN103325696A (zh) * 2012-03-21 2013-09-25 矽品精密工业股份有限公司 晶圆级半导体封装件的制法及其晶圆级封装基板的制法
CN104078451A (zh) * 2013-03-29 2014-10-01 英特尔公司 用于射频无源件和天线的方法、设备和材料
CN104733402A (zh) * 2013-12-19 2015-06-24 矽品精密工业股份有限公司 半导体封装结构及其制法

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108364932A (zh) * 2017-01-26 2018-08-03 日月光半导体制造股份有限公司 半导体封装结构
US11417620B2 (en) 2017-03-30 2022-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device encapsulated by molding material attached to redestribution layer
CN108695267A (zh) * 2017-03-30 2018-10-23 台湾积体电路制造股份有限公司 封装结构
US11887952B2 (en) 2017-03-30 2024-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device encapsulated by molding material attached to redistribution layer
CN109390292A (zh) * 2017-08-11 2019-02-26 矽品精密工业股份有限公司 电子封装件及其制法
CN109585471A (zh) * 2017-09-29 2019-04-05 三星电子株式会社 半导体封装和图像传感器
CN109585471B (zh) * 2017-09-29 2023-08-29 三星电子株式会社 半导体封装和图像传感器
CN110707049A (zh) * 2018-07-10 2020-01-17 三星电子株式会社 包括用于控制翘曲的通道的半导体芯片模块及其制造方法
CN110707049B (zh) * 2018-07-10 2024-07-09 三星电子株式会社 包括用于控制翘曲的通道的半导体芯片模块及其制造方法
WO2020172948A1 (zh) * 2019-02-27 2020-09-03 中芯集成电路（宁波）有限公司 Cmos图像传感器封装模块及其形成方法、摄像装置
CN111668178A (zh) * 2019-03-08 2020-09-15 力成科技股份有限公司 封装结构及其制作方法
CN111863633B (zh) * 2019-04-25 2022-01-25 深圳市鼎华芯泰科技有限公司 一种封装载板、封装体及其工艺
CN111863633A (zh) * 2019-04-25 2020-10-30 深圳市环基实业有限公司 一种封装载板、封装体及其工艺
WO2021097814A1 (zh) * 2019-11-22 2021-05-27 华为技术有限公司 芯片封装、电子设备及芯片封装制备方法
CN113555351A (zh) * 2020-04-23 2021-10-26 瑞昱半导体股份有限公司 半导体封装
CN113555351B (zh) * 2020-04-23 2024-02-06 瑞昱半导体股份有限公司 半导体封装
WO2024065992A1 (zh) * 2022-09-27 2024-04-04 武汉新芯集成电路制造有限公司 芯片封装方法及半导体封装结构
CN117954335A (zh) * 2024-03-22 2024-04-30 甬矽半导体(宁波)有限公司 基于重构晶圆的封装方法和基于重构晶圆的封装结构
CN117954335B (zh) * 2024-03-22 2024-07-05 甬矽半导体(宁波)有限公司 基于重构晶圆的封装方法和基于重构晶圆的封装结构

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