TW202217988A - 半導體裝置及製造方法 - Google Patents

半導體裝置及製造方法 Download PDF

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TW202217988A
TW202217988A TW110108556A TW110108556A TW202217988A TW 202217988 A TW202217988 A TW 202217988A TW 110108556 A TW110108556 A TW 110108556A TW 110108556 A TW110108556 A TW 110108556A TW 202217988 A TW202217988 A TW 202217988A
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die
interface material
semiconductor die
package
semiconductor
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TW110108556A
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TWI765601B (zh
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陳志豪
王卜
鄭禮輝
盧思維
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台灣積體電路製造股份有限公司
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Abstract

提供半導體裝置及製造方法，其中自嵌入包封體內的半導體晶粒移除黏合劑，並利用介面材料自半導體裝置散熱。移除黏合劑使凹陷在鄰近於半導體的側壁處產生且凹陷被填充。

Description

半導體裝置及製造方法
由於各種電子部件（例如電晶體、二極體、電阻器、電容器等）的積體密度的不斷提高，半導體行業已經歷快速發展。在很大程度上，積體密度的提高源於最小特徵大小（minimum feature size）的迭代減小，此使得能夠將更多的部件整合至給定的面積中。隨著對日益縮小的電子裝置需求的增長，出現了對更小且更具創造性的半導體晶粒封裝技術的需求。此種封裝系統的一個實例是疊層封裝（Package-on-Package，PoP）技術。在PoP裝置中，頂部半導體封裝堆疊於底部半導體封裝頂上，以提供高積體程度及部件密度。PoP技術一般能夠使得在印刷電路板（printed circuit board，PCB）上生產具有增強的功能性及小的佔用面積（footprint）的半導體裝置。
以下揭露內容提供用於實施本發明實施例的不同特徵的諸多不同實施例或實例。以下闡述部件及排列的具體實例以簡化本揭露。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵之上或第二特徵上可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，並且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於……之下（beneath）」、「位於……下方（below）」、「下部的（lower）」、「位於……上方（above）」、「上部的（upper）」及類似用語等空間相對性用語來闡述圖中所示的一個組件或特徵與另一（其他）組件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。裝置可具有其他定向（旋轉90度或處於其他定向），並且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
現將針對特定的結構及方法來闡述實施例，其中介面材料（interface material）被用來在積體扇出型（integrated fan out，InFO）封裝內提供介面。然而，本文中所述的實施例並不旨在限制於所闡述的實施例且所述實施例可以例如積體扇出型大規模積體結構（integrated fan-out large scale integration structure，InFO-LSI）、積體扇出型多晶片結構（integrated fan out multichip structure，InFO-M）、基底上晶圓上晶片（chip on wafer on substrate，CoWoS）結構或積體電路上系統（system on integrated circuit，SoIC）結構等任何適合的結構及方法來實施。所有此種實施例皆完全旨在包括於所述實施例的範圍內。
圖1示出根據一些實施例的積體電路晶粒50的剖視圖。積體電路晶粒50將在隨後的處理中被封裝以形成積體電路封裝。積體電路晶粒50可為邏輯晶粒（例如中央處理單元（central processing unit，CPU）、圖形處理單元（graphics processing unit，GPU）、系統晶片（system-on-a-chip，SoC）、應用處理器（application processor，AP）、微控制器等）、記憶體晶粒（例如動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒等）、電源管理晶粒（例如電源管理積體電路（power management integrated circuit，PMIC）晶粒）、射頻（radio frequency，RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、訊號處理晶粒（例如數位訊號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如類比前端（analog front-end，AFE）晶粒）、類似物或其組合。
積體電路晶粒50可形成於晶圓中，所述晶圓可包括在隨後的步驟中被單體化以形成多個積體電路晶粒的不同裝置區。積體電路晶粒50可根據適用的製造製程進行處理以形成積體電路。舉例而言，積體電路晶粒50包括半導體基底52（例如經摻雜或未經摻雜的矽）或者絕緣體上半導體（semiconductor-on-insulator，SOI）基底的主動層。半導體基底52可包含：其他半導體材料（例如鍺）、化合物半導體（包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦）、合金半導體（包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP）、或其組合。亦可使用例如多層式基底（multi-layered substrate）或梯度基底（gradient substrate）等其他基底。半導體基底52具有有時稱為前側的主動表面（例如圖1中面朝上的表面）及有時稱為背側的非主動表面（例如圖1中面朝下的表面）。
半導體基底52的前表面處可形成有裝置（以電晶體為代表）54。裝置54可為主動裝置（例如電晶體、二極體等）、電容器、電阻器等。半導體基底52的前表面之上有層間介電質（inter-layer dielectric，ILD）56。ILD 56環繞且可覆蓋裝置54。ILD 56可包括由例如磷矽酸鹽玻璃（Phospho-Silicate Glass，PSG）、硼矽酸鹽玻璃（Boro-Silicate Glass，BSG）、摻雜硼的磷矽酸鹽玻璃（Boron-Doped Phospho-Silicate Glass，BPSG）、未經摻雜的矽酸鹽玻璃（undoped Silicate Glass，USG）或類似物等材料形成的一或多個介電層。
導電插塞58延伸穿過ILD 56，以對裝置54進行電性耦合及物理耦合。舉例而言，當裝置54是電晶體時，導電插塞58可對電晶體的閘極及源極/汲極區進行耦合。導電插塞58可由鎢、鈷、鎳、銅、銀、金、鋁、類似物或其組合形成。ILD 56及導電插塞58之上有內連線結構60。內連線結構60對裝置54進行內連以形成積體電路。內連線結構60可由例如ILD 56上的介電層中的金屬化圖案形成。金屬化圖案包括形成於一或多個低介電常數（low-k）介電層中的金屬線及通孔。內連線結構60的金屬化圖案藉由導電插塞58電性耦合至裝置54。
積體電路晶粒50更包括進行外部連接的接墊62，例如鋁墊。接墊62位於積體電路晶粒50的主動側上，例如位於內連線結構60中及/或內連線結構60上。積體電路晶粒50上（例如內連線結構60及接墊62的部分上）有一或多個鈍化膜64。開口穿過鈍化膜64延伸至接墊62。例如導電柱（例如由如銅等金屬形成）等晶粒連接件66延伸穿過鈍化膜64中的開口，並且物理耦合至及電性耦合至接墊62中相應的接墊62。晶粒連接件66可藉由例如鍍覆或類似製程形成。晶粒連接件66對積體電路晶粒50的相應的積體電路進行電性耦合。
可選地，接墊62上可設置有焊料區（例如焊球或焊料凸塊）。焊球可用於對積體電路晶粒50執行晶片探針（chip probe，CP）測試。可對積體電路晶粒50執行CP測試，以判斷積體電路晶粒50是否是已知良好晶粒（known good die，KGD）。因此，只有積體電路晶粒50（其為KGD）經歷隨後的處理並被封裝，並且未通過CP測試的晶粒未被封裝。在測試之後，可在隨後的處理步驟中移除焊料區。
積體電路晶粒50的主動側上（例如鈍化膜64及晶粒連接件66上）可有（或可沒有）介電層68。介電層68在側向上包封晶粒連接件66，並且介電層68與積體電路晶粒50在側向上相連。介電層68可先掩埋晶粒連接件66，而使介電層68的最頂表面位於晶粒連接件66的最頂表面上方。在晶粒連接件66上設置有焊料區的一些實施例中，介電層68亦可掩埋焊料區。作為另一選擇，可在形成介電層68之前移除焊料區。
介電層68可為聚合物（例如聚苯並噁唑（polybenzoxazole，PBO）、聚醯亞胺、苯並環丁烯（benzocyclobutene，BCB）等）、氮化物（例如氮化矽或類似物）、氧化物（例如氧化矽、PSG、BSG、BPSG等）、類似物或其組合。介電層68可例如藉由旋轉塗佈（spin coating）、疊層、化學氣相沉積（chemical vapor deposition，CVD）或類似製程形成。在一些實施例中，在積體電路晶粒50的形成期間，晶粒連接件66藉由介電層68暴露出。在一些實施例中，晶粒連接件66保持被掩埋並在封裝積體電路晶粒50的後續的製程期間被暴露出。暴露出晶粒連接件66時可移除晶粒連接件66上可能存在的任何焊料區。
在一些實施例中，積體電路晶粒50是包括多個半導體基底52的堆疊裝置。舉例而言，積體電路晶粒50可為包括多個記憶體晶粒的記憶體裝置，例如混合記憶體立方（hybrid memory cube，HMC）模組、高頻寬記憶體（high bandwidth memory，HBM）模組或類似物。在此種實施例中，積體電路晶粒50包括藉由基底穿孔（through-substrate via，TSV）進行內連的多個半導體基底52。半導體基底52中的每一者可（或可不）具有內連線結構60。
圖2至圖20示出根據一些實施例的用於形成第一封裝部件100的製程期間的中間步驟的剖視圖。示出第一封裝區100A及第二封裝區100B，並且積體電路晶粒50中的一或多者被封裝以在封裝區100A及100B中的每一者中形成積體電路封裝。積體電路封裝亦可稱為積體扇出型（InFO）封裝。
在圖2中，提供載體基底102，並且在載體基底102上形成離型層104。載體基底102可為玻璃載體基底、陶瓷載體基底或類似物。載體基底102可為晶圓，而使得可在載體基底102上同時形成多個封裝。
離型層104可由聚合物系材料形成，離型層104可與載體基底102一起被自將在隨後的步驟中形成的上覆結構移除。在一些實施例中，離型層104為當受熱時會失去其黏合性質的環氧系熱離型材料，例如光熱轉換（light-to-heat-conversion，LTHC）離型塗層。在其他實施例中，離型層104可為當曝露於紫外（ultra-violet，UV）光時會失去其黏合性質的UV膠。離型層104可以液體形式被點膠並被固化，可為疊層至載體基底102上的疊層膜（laminate film）或者可為類似物。離型層104的頂表面可被整平且可具有高的平坦程度。
可選地，可在離型層104上形成背側重佈線結構（未單獨示出）。在所示的實施例中，背側重佈線結構包括介電層、金屬化圖案（有時稱為重佈線層或重佈線（redistribution line））及介電層。在一些實施例中，在離型層104上形成不具有金屬化圖案的介電層來代替背側重佈線結構。
可在離型層104上形成介電層。介電層的底表面可與離型層104的頂表面接觸。在一些實施例中，介電層由例如聚苯並噁唑（PBO）、聚醯亞胺、苯並環丁烯（BCB）或類似物等聚合物形成。在其他實施例中，介電層由以下形成：氮化物（例如氮化矽）、氧化物（例如氧化矽、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（BSG）、摻雜硼的磷矽酸鹽玻璃（BPSG）等）或者類似物。可藉由例如旋轉塗佈、CVD、疊層、類似製程或其組合等任何可接受的沉積製程形成介電層。
可在介電層上形成金屬化圖案。作為形成金屬化圖案的實例，在介電層之上形成晶種層（seed layer）。在一些實施例中，晶種層是金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積（physical vapor deposition，PVD）或類似製程形成晶種層。然後，在晶種層上形成光阻（未示出）並圖案化光阻。可藉由旋轉塗佈或類似製程形成光阻，並可將光阻曝露於光以用於圖案化。光阻的圖案對應於金屬化圖案。圖案化步驟會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及晶種層的被暴露出的部分上形成導電材料。可藉由例如電鍍或無電鍍覆等鍍覆或者類似製程形成導電材料。導電材料可包括例如銅、鈦、鎢、鋁或類似物等金屬。然後，移除光阻及晶種層的上面未形成導電材料的部分。可藉由例如使用氧電漿或類似物的可接受的灰化製程（ashing process）或剝除製程（stripping process）移除光阻。一旦光阻被移除，便例如藉由使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）移除晶種層的被暴露出的部分。晶種層的其餘部分與導電材料形成金屬化圖案。
可在金屬化圖案及介電層上形成介電層。在一些實施例中，介電層由聚合物形成，所述聚合物可為例如PBO、聚醯亞胺、BCB或類似物等可使用微影罩幕來圖案化的感光性材料。在其他實施例中，介電層由以下形成：氮化物（例如氮化矽）、氧化物，（例如氧化矽、PSG、BSG、BPSG）或類似物。可藉由旋轉塗佈、疊層、CVD、類似製程或其組合形成介電層。然後，對介電層進行圖案化以形成暴露出金屬化圖案的部分的開口。可藉由可接受的製程（例如當介電層是感光性材料時，藉由將介電層曝露於光，或者藉由使用例如非等向性蝕刻進行蝕刻）來執行圖案化步驟。若介電層是感光性材料，則介電層可在曝光後顯影。
在一些實施例中，背側重佈線結構可包括任意數目的介電層及金屬化圖案。若欲形成更多的介電層及金屬化圖案，則可重複進行以上所述的步驟及製程。金屬化圖案可包括一或多個導電組件。可在金屬化圖案的形成期間藉由在下伏介電層的表面之上及下伏介電層的開口中形成晶種層以及金屬化圖案的導電材料來形成導電組件，藉此對各種導線進行內連及電性耦合。
在圖3中，在離型層104上形成穿孔116或在背側重佈線結構（若存在）上形成穿孔116。作為形成穿孔116的實例，在離型層104之上形成晶種層（未示出）。在一些實施例中，晶種層是金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD或類似製程形成晶種層。在晶種層上形成光阻並圖案化光阻。可藉由旋轉塗佈或類似製程形成光阻，並可將光阻曝露於光以用於圖案化。光阻的圖案對應於導通孔。圖案化步驟會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及晶種層的被暴露出的部分上形成導電材料。可藉由例如電鍍或無電鍍覆等鍍覆或者類似製程形成導電材料。導電材料可包括例如銅、鈦、鎢、鋁或類似物等金屬。移除光阻及晶種層的上面未形成導電材料的部分。可藉由例如使用氧電漿或類似的可接受的灰化製程或剝除製程移除光阻。一旦光阻被移除，便例如藉由使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）移除晶種層的被暴露出的部分。晶種層的其餘部分與導電材料形成穿孔116。
在圖4A中，藉由黏合劑118將積體電路晶粒50（例如第一積體電路晶粒50A及第二積體電路晶粒50B）黏合至離型層104。封裝區100A及100B中的每一者中黏合有所期望的類型及數量的積體電路晶粒50。在所示的實施例中，多個積體電路晶粒50被黏合成彼此鄰近，包括位於第一封裝區100A及第二封裝區100B中的每一者中的第一積體電路晶粒50A及第二積體電路晶粒50B。第一積體電路晶粒50A可為邏輯裝置，例如中央處理單元（CPU）、圖形處理單元（GPU）、系統晶片（SoC）、微控制器或類似物。第二積體電路晶粒50B可為記憶體裝置，例如動態隨機存取記憶體（DRAM）晶粒、靜態隨機存取記憶體（SRAM）晶粒、混合記憶體立方（HMC）模組、高頻寬記憶體（HBM）模組或類似物。在一些實施例中，積體電路晶粒50A與50B可為相同類型的晶粒，例如SoC晶粒。第一積體電路晶粒50A與第二積體電路晶粒50B可在相同技術節點的製程中形成或可在不同技術節點的製程中形成。舉例而言，第一積體電路晶粒50A可屬於較第二積體電路晶粒50B更先進的製程節點。積體電路晶粒50A與50B可具有不同的尺寸（例如不同的高度及/或表面積）或可具有相同的尺寸（例如相同的高度及/或表面積）。第一封裝區100A及第二封裝區100B中可用於穿孔116的空間可能受到限制，當積體電路晶粒50包括例如SoC等具有大的佔用面積（footprint）的裝置時尤為如此。
黏合劑118位於積體電路晶粒50的背側上，並且將積體電路晶粒50黏合至載體基底102。黏合劑118可為任何適合的黏合劑、環氧樹脂、晶粒貼合膜（die attach film，DAF）或類似物。可將黏合劑118施加至積體電路晶粒50的背側，若未利用背側重佈線結構，則可將黏合劑118施加於載體基底102的表面之上，或者若適用，則可將黏合劑118塗覆至背側重佈線結構的上表面。舉例而言，可在進行單體化以分離積體電路晶粒50之前，將黏合劑118塗覆至積體電路晶粒50的背側。
圖4B示出圖4A中標記為114的虛線框的放大圖。可看出，在將黏合劑118放置至表面（例如積體電路晶粒50或離型層104）上之後且在放置積體電路晶粒50之後，黏合劑118被壓縮並延伸超過積體電路晶粒50的外部側壁（outside sidewall），以形成延伸部121。在實施例中，黏合劑118的延伸部121可延伸在約1微米（µm）與約30 µm之間的第一距離D 1。另外，不位於積體電路晶粒50之下的黏合劑118可具有大於位於積體電路晶粒50之下的黏合劑118的高度的第一高度H 1，例如具有在約1 µm與約30 µm之間的第一高度H 1。然而，可利用任何適合的高度。
在圖5中，在各種部件上及周圍形成包封體120，並且包封體120與延伸部121物理接觸。在形成之後，包封體120包封穿孔116及積體電路晶粒50。包封體120可為模製化合物、環氧樹脂或類似物。可藉由壓縮模製、轉移模製或類似製程塗覆包封體120，並且可在載體基底102之上形成包封體120，而使穿孔116及/或積體電路晶粒50被掩埋或被覆蓋。在積體電路晶粒50之間的間隙區中進一步形成包封體120。可以液體或半液體形式塗覆包封體120，隨後對包封體120進行固化。
在圖6中，對包封體120執行平坦化製程，以暴露出穿孔116及晶粒連接件66。平坦化製程亦可移除穿孔116、介電層68及/或晶粒連接件66的材料，直至暴露出晶粒連接件66及穿孔116為止。在平坦化製程之後，穿孔116的頂表面、晶粒連接件66的頂表面、介電層68的頂表面及包封體120的頂表面在製程變化內實質上共面。平坦化製程可為例如化學機械研磨（chemical-mechanical polish，CMP）、研磨製程（grinding process）或類似製程。在一些實施例中，舉例而言，若穿孔116及/或晶粒連接件66已被暴露出，則可省略平坦化。
在圖7至圖10中，在包封體120、穿孔116及積體電路晶粒50之上形成前側重佈線結構122（參見圖10）。前側重佈線結構122包括介電層124、128、132及136以及金屬化圖案126、130及134。金屬化圖案亦可稱為重佈線層或重佈線線。前側重佈線結構122被示為具有三層金屬化圖案的實例。可在前側重佈線結構122中形成更多或更少的介電層及金屬化圖案。若欲形成更少的介電層及金屬化圖案，則可省略下文論述的步驟及製程。若欲形成更多的介電層及金屬化圖案，則可重複進行下文論述的步驟及製程。
在圖7中，在包封體120、穿孔116及晶粒連接件66上沉積介電層124。在一些實施例中，介電層124由例如PBO、聚醯亞胺、BCB或類似物等可使用微影罩幕來圖案化的感光性材料形成。可藉由旋轉塗佈、疊層、CVD、類似製程或其組合來形成介電層124。然後，對介電層124進行圖案化。圖案化步驟會形成暴露出穿孔116及晶粒連接件66的部分的開口。可藉由可接受的製程（例如當介電層124是感光性材料時，藉由將介電層124曝露於光並顯影，或者藉由使用例如非等向性蝕刻進行蝕刻）來進行圖案化。
然後形成金屬化圖案126。金屬化圖案126包括沿著介電層124的主表面延伸且延伸穿過介電層124以物理耦合至及電性耦合至穿孔116及積體電路晶粒50的導電組件。作為形成金屬化圖案126的實例，在介電層124之上且在延伸穿過介電層124的開口中形成晶種層。在一些實施例中，晶種層是金屬層，其可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD或類似製程形成晶種層。然後，在晶種層上形成光阻且圖案化光阻。可藉由旋轉塗佈或類似製程形成光阻，並可將光阻曝露於光以用於圖案化。光阻的圖案對應於金屬化圖案126。圖案化步驟會形成穿過光阻的開口以暴露出晶種層。然後，在光阻的開口中及晶種層的被暴露出的部分上形成導電材料。可藉由例如電鍍或無電鍍覆等鍍覆或者類似製程形成導電材料。導電材料可包括例如銅、鈦、鎢、鋁或類似物等金屬。導電材料與晶種層的下伏部分的組合形成金屬化圖案126。移除光阻以及晶種層的上面未形成導電材料的部分。可藉由例如使用氧電漿或類似物的可接受的灰化製程或剝除製程移除光阻。一旦光阻被移除，便例如藉由使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）移除晶種層的被暴露出的部分。
在圖8中，在金屬化圖案126及介電層124上沉積介電層128。可以與介電層124相似的方式形成介電層128且介電層128可由與介電層124相似的材料形成。
然後形成金屬化圖案130。金屬化圖案130包括位於介電層128的主表面上且沿著所述主表面延伸的部分。金屬化圖案130更包括延伸穿過介電層128以物理耦合及電性耦合至金屬化圖案126的部分。可以與金屬化圖案126相似的方式形成金屬化圖案130且金屬化圖案130可由與金屬化圖案126相似的材料形成。在一些實施例中，金屬化圖案130具有與金屬化圖案126不同的尺寸。舉例而言，金屬化圖案130的導線及/或通孔可寬於或厚於金屬化圖案126的導線及/或通孔。此外，可將金屬化圖案130形成為較金屬化圖案126大的節距。
在圖9中，在金屬化圖案130及介電層128上沉積介電層132。可以與介電層124相似的方式形成介電層132且介電層132可由與介電層124相似的材料形成。
然後，形成金屬化圖案134。金屬化圖案134包括位於介電層132的主表面上且沿著所述主表面延伸的部分。金屬化圖案134更包括延伸穿過介電層132以物理耦合及電性耦合至金屬化圖案130的部分。可以與金屬化圖案126相似的方式形成金屬化圖案134且金屬化圖案134可由與金屬化圖案126相似的材料形成。金屬化圖案134是前側重佈線結構122的最頂金屬化圖案。因此，前側重佈線結構122的所有中間金屬化圖案（例如金屬化圖案126及130）設置於金屬化圖案134與積體電路晶粒50之間。在一些實施例中，金屬化圖案134具有與金屬化圖案126及130不同的尺寸。舉例而言，金屬化圖案134的導線及/或通孔可寬於或厚於金屬化圖案126及130的導線及/或通孔。此外，可將金屬化圖案134形成為較金屬化圖案130大的節距。
在圖10中，在金屬化圖案134及介電層132上沉積介電層136。可以與介電層124相似的方式形成介電層136且介電層136可由與介電層124相同的材料形成。介電層136是前側重佈線結構122的最頂介電層。因此，前側重佈線結構122的所有金屬化圖案（例如金屬化圖案126、130及134）設置於介電層136與積體電路晶粒50之間。此外，前側重佈線結構122的所有中間介電層（例如介電層124、128、132）設置於介電層136與積體電路晶粒50之間。
在圖11中，形成凸塊下金屬（underbump metallization，UBM）138以用於與前側重佈線結構122進行外部連接。UBM 138具有位於介電層136的主表面上且沿著所述主表面延伸的凸塊部分，並且具有延伸穿過介電層136以物理耦合及電性耦合至金屬化圖案134的通孔部分。因此，UBM 138電性耦合至穿孔116及積體電路晶粒50。UBM 138可由與金屬化圖案126相同的材料形成。在一些實施例中，UBM 138具有與金屬化圖案126、130及134不同的尺寸。
在圖12中，在UBM 138上形成導電連接件150。導電連接件150可為球柵陣列（ball grid array，BGA）連接件、焊球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、無電鍍鎳鈀浸金（electroless nickel-electroless palladium-immersion gold，ENEPIG）形成的凸塊或類似物。導電連接件150可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合等導電材料。在一些實施例中，藉由先透過蒸鍍、電鍍、印刷、焊料轉移、植球或類似製程形成焊料層來形成導電連接件150。一旦在所述結構上形成焊料層，便可執行回焊，以便將所述材料造型成所期望的凸塊形狀。在另一實施例中，導電連接件150包括藉由濺鍍、印刷、電鍍、無電鍍覆、CVD或類似製程形成的金屬柱（例如銅柱）。金屬柱可不含焊料，並且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似物或其組合，並且可藉由鍍覆製程形成金屬頂蓋層。
在圖13中，執行載體基底剝離，以將載體基底102拆離（或「剝離」）。根據一些實施例，剝離包括將例如雷射光或UV光等光投射於離型層104上，使得型層104在光的熱量下分解，並且載體基底102及離型層104可被移除。然後，將所述結構上下翻轉並放置於膠帶（tape）（未示出）上。
在圖14A中，執行清潔製程（在圖14A中由標記為141的波浪線表示），以確保離型層104的任何其餘部分均被完全移除，並移除黏合劑118。在實施例中，可使用電漿清潔製程、濕式蝕刻製程、該些製程的組合或類似製程來執行清潔製程141。然而，可執行任何適合的清潔步驟。
一旦離型層104被完全移除，便移除黏合劑118，以暴露出積體電路晶粒50的背表面，藉此移除在其他情況下可能會限制散熱效率的材料。在實施例中，可使用乾式蝕刻製程（例如電漿蝕刻製程）或濕式蝕刻製程來移除黏合劑118。在其中利用濕式蝕刻製程的實施例中，將溶劑或蝕刻劑（例如二甲基亞碸（dimethyl sulfoxide，DMSO）、四甲基氫氧化銨（tetramethylammonium hydroxide，TMAH）、該些材料的組合或類似物）塗覆至黏合劑118。一旦物理接觸，溶劑或蝕刻劑便被用來物理地或化學地移除黏合劑118的材料。然而，可利用任何適合的製程來移除黏合劑118。
另外，可使包封體120凹陷，以暴露出穿孔116的側壁。在實施例中，可藉由清潔製程141或用於移除黏合劑118的製程中的一或多者來使包封體120凹陷。在另一實施例中，可在例如濕式蝕刻製程或乾式蝕刻製程等單獨的蝕刻製程中使包封體120凹陷。
圖14B示出圖14A中標記為123的虛線的放大圖。如可在圖14B中看出，藉由移除黏合劑118，黏合劑118的延伸部121亦被移除。因此，在黏合劑118的延伸部121的位置及形狀中形成第一凹陷125，並且第一凹陷125將具有與黏合劑118的延伸部121相似的形狀及大小（例如第一高度H 1及第一距離D 1）。然而，可利用任何適合的大小及形狀。
圖14C示出圖14A中標記為131的虛線的放大圖。如可在圖14C中看出，在用於移除離型層104的清潔製程141及對黏合劑118的移除之後，積體電路晶粒50、包封體120及穿孔116中的每一者可具有遠離前側重佈線結構122延伸的不同高度。舉例而言，積體電路晶粒50可具有在約20 µm與約700 µm之間的第二高度H 2，包封體120可具有大於第二高度H 2的第三高度H 3（例如具有在約25 µm與約705 µm之間的第三高度H 3），穿孔116可具有大於第三高度H 3的第四高度H 4（例如具有在約30 µm與約710 µm之間的第四高度H 4）。然而，可利用任何適合的尺寸。
圖15示出在積體電路晶粒50之上但不在穿孔116之上放置介面材料127，藉此將積體電路晶粒50與上覆的結構（未在圖15中示出，但在下文中例示及闡述）連接。在實施例中，介面材料127可為預成型膜（pre-formed film），其是高度可壓縮的（highly compressible）、具有高黏合力且具有高導熱係數。舉例而言，在一些實施例中，預成型膜可具有在約15瓦/開*米（W/k*m）與約60 W/k*m之間（例如大於約20 W/k*m）的導熱係數、在約250牛頓/毫米（N/mm）與約2500 N/mm之間的剛性、在約0.5牛頓*毫米（N*mm）與約10 N*mm之間的黏性以及在約0.01百萬帕（MPa）與約5.0 MPa之間的拉伸強度。然而，可利用任何適合的參數。
在特定實施例中，介面材料127是例如鉛錫系焊料（PbSn）、無鉛焊料、銦、碳複合材料、石墨、奈米碳管或其他適合的導熱材料等材料。可使用疊層製程、拾取及放置製程（pick and place process）、該些製程的組合或類似製程將作為膜的介面材料127放置至在約40 µm與約300 µm之間的初始厚度，並且不沿著積體電路晶粒50的背側使用黏合材料（例如晶粒貼合材料或聚合物緩衝層）。然而，可利用任何適合的放置方式及任何適合的厚度。
另外，如圖15中所示，介面材料127可具有大於積體電路晶粒50的第二寬度W 2的第一寬度W 1。因此，在此實施例中，介面材料127在第一凹陷125之上延伸且覆蓋第一凹陷125。舉例而言，在其中積體電路晶粒50具有在約2毫米（mm）與約55 mm之間的第二寬度W 2的實施例中，介面材料127具有在約2.5 mm與約55.5 mm之間的第一寬度W 1。然而，可利用任何適合的尺寸。
圖16示出用於接觸穿孔116的導電連接件152的形成。在一些實施例中，導電連接件152包含焊劑（flux），並且是在焊劑浸漬製程（flux dipping process）中形成。在一些實施例中，導電連接件152包含例如焊膏、銀膏或類似物等導電膏，並且是在印刷製程中進行點膠。在一些實施例中，以與導電連接件150相似的方式形成導電連接件152，並且導電連接件152可由與導電連接件150相似的材料形成。另外，在一些實施例中，可在導電連接件152的形成期間形成金屬間化合物（intermetal compound，IMC）。
圖16另外示出根據一些實施例的裝置堆疊的形成及實施。裝置堆疊由在第一封裝部件100中形成的積體電路封裝形成。裝置堆疊亦可稱為疊層封裝（PoP）結構。在圖16中，將第二封裝部件200耦合至第一封裝部件100。將第二封裝部件200中的一者耦合於封裝區100A及100B中的每一者中，以在第一封裝部件100的每一區中形成積體電路裝置堆疊。
第二封裝部件200包括例如基底202以及耦合至基底202的一或多個堆疊晶粒210（例如210A與210B）。儘管示出一組堆疊晶粒210（210A與210B），然而在其他實施例中，可將多個堆疊晶粒210（各自具有一或多個堆疊晶粒）設置成並排地耦合至基底202的同一表面。基底202可由例如矽、鍺、金剛石或類似物等半導體材料製成。在一些實施例中，亦可使用例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、該些材料的組合及類似物等化合物材料。另外，基底202可為絕緣體上矽（silicon-on-insulator，SOI）基底。一般而言，SOI基底包括由例如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺（silicon germanium on insulator，SGOI）或其組合等半導體材料構成的層。在一個替代性實施例中，基底202是基於例如玻璃纖維加強型樹脂芯體等絕緣芯體。一種示例性芯體材料是例如FR4等玻璃纖維樹脂。芯體材料的替代品包括雙馬來醯亞胺-三嗪（bismaleimide-triazine，BT）樹脂，或者作為另一選擇包括其他印刷電路板（PCB）材料或膜。可對基底202使用例如味之素疊層膜（Ajinomoto build-up film，ABF）等疊層膜或者其他疊層體。
基底202可包括主動裝置及被動裝置（未示出）。可使用各種各樣的裝置（例如電晶體、電容器、電阻器、該些的組合及類似物）來產生第二封裝部件200的設計的結構要求及功能要求。可使用任何適合的方法來形成所述裝置。
基底202亦可包括金屬化層（未示出）及導通孔208。可在主動裝置及被動裝置之上形成金屬化層，並且將金屬化層設計成連接各種裝置以形成功能電路系統。金屬化層可由介電材料（例如低k介電材料）與導電材料（例如銅）構成的交替層形成，其中通孔對導電材料層進行內連，並且可藉由任何適合的製程（例如沉積、鑲嵌、雙鑲嵌（dual damascene）或類似製程）形成所述金屬化層。在一些實施例中，基底202實質上不含主動裝置及被動裝置。
基底202可在基底202的第一側上具有接合接墊204以耦合至堆疊晶粒210，並且在基底202的第二側上具有接合接墊206以耦合至導電連接件152，所述第二側與基底202的第一側相對。在一些實施例中，藉由向基底202的第一側及第二側上的介電層（未示出）中形成凹陷（未示出）來形成接合接墊204及206。可將凹陷形成為使接合接墊204及206能夠嵌入至介電層中。在其他實施例中，由於接合接墊204及206可形成於介電層上，因此省略了凹陷。在一些實施例中，接合接墊204及206包括由銅、鈦、鎳、金、鈀、類似物或其組合製成的薄晶種層（未示出）。可在薄晶種層之上沉積接合接墊204及206的導電材料。可藉由電化學鍍覆製程、化學鍍覆製程、CVD、原子層沉積（atomic layer deposition，ALD）、PVD、類似製程或其組合形成導電材料。在實施例中，接合接墊204及206的導電材料是銅、鎢、鋁、銀、金、類似物或其組合。
在一些實施例中，接合接墊204及接合接墊206是UBM，所述UBM包括三層導電材料，例如一層鈦、一層銅及一層鎳。可利用材料及層的其他排列形式（例如為鉻/鉻-銅合金/銅/金的排列形式、為鈦/鈦鎢/銅的排列形式或為銅/鎳/金的排列形式）來形成接合接墊204及206。可用於接合接墊204及206的任何適合的材料或材料層均完全旨在包含於本文的範圍內。在一些實施例中，導通孔208延伸穿過基底202，並且將接合接墊204中的至少一者耦合至接合接墊206中的至少一者。
儘管可使用例如導電凸塊等其他連接方式，然而在所示的實施例中，藉由導線接合（wire bond）212將堆疊晶粒210耦合至基底202。在實施例中，堆疊晶粒210是堆疊記憶體晶粒。舉例而言，堆疊晶粒210可為記憶體晶粒，例如低功率（low-power，LP）雙倍資料速率（double data rate，DDR）記憶體模組（例如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似記憶體模組）。
可藉由模製材料214來包封堆疊晶粒210及導線接合212。可例如使用壓縮模製在堆疊晶粒210及導線接合212上模製模製材料214。在一些實施例中，模製材料214是模製化合物、聚合物、環氧樹脂、氧化矽填料材料、類似物或其組合。可執行固化製程來固化模製材料214，固化製程可為熱固化、UV固化、類似製程或其組合。
在一些實施例中，將堆疊晶粒210及導線接合212掩埋於模製材料214中，並且在固化模製材料214之後，執行平坦化步驟（例如研磨）以移除模製材料214的過量部分且為第二封裝部件200提供實質上平坦的表面。
在形成第二封裝部件200之後，藉由導電連接件152、接合接墊206及背側重佈線結構的金屬化圖案將第二封裝部件200機械接合至及電性接合至第一封裝部件100。在一些實施例中，可藉由導線接合212、接合接墊204及206、導通孔208、導電連接件152、背側重佈線結構、穿孔116及前側重佈線結構122將堆疊晶粒210耦合至積體電路晶粒50A及50B。
在一些實施例中，在基底202的與堆疊晶粒210相對的一側上形成阻焊劑（未示出）。可在阻焊劑的開口中設置導電連接件152，以電性耦合至及機械耦合至基底202中的導電特徵（例如接合接墊206）。可使用阻焊劑（solder resist）來保護基底202的區域免受外部損傷。
在一些實施例中，導電連接件152在被回焊之前具有形成於其上的環氧焊劑（未示出），其中在將第二封裝部件200貼合至第一封裝部件100之後，環氧焊劑的至少一些環氧部分保留下來。
在將第二封裝部件200接合至第一封裝部件100之後，自介面材料127的初始沉積厚度壓縮介面材料127。在一些實施例中，在接合之後，介面材料127已被壓縮至具有在約20 µm與約200 µm之間的第五高度H 5。因此，介面材料127可被壓縮至少5 µm。另外，介面材料127的厚度（例如第五高度H 5）與積體電路晶粒50的厚度（例如第二高度H 2）的組合較包封體120的厚度（例如第三高度H 3）大約0.5 µm至約50 µm。然而，可利用任何適合的厚度。
另外，即使介面材料127將被壓縮至具有第五高度H 5，然而介面材料127在壓縮之後仍將維持其側壁。具體而言，介面材料127將具有鋒利的垂直（或接近垂直）側壁。
藉由利用具有此種可壓縮性的介面材料127，可減輕凸塊接頭表現差的問題。具體而言，藉由使用可壓縮的介面材料127，介面材料127不會妨礙導電連接件152的放置及接合。因此，將出現更少的缺陷。
在一些實施例中，在第一封裝部件100與第二封裝部件200之間形成環繞導電連接件152的底部填充膠133。底部填充膠133可減少應力並保護由對導電連接件152的回焊產生的接頭。可在貼合第二封裝部件200之後藉由毛細流動製程（capillary flow process）形成底部填充膠133，或者可在貼合第二封裝部件200之前藉由適合的沉積方法形成底部填充膠133。
另外，在一些實施例中，底部填充膠133會另外填充經由移除黏合劑118的延伸部121而形成的第一凹陷125。舉例而言，在放置介面材料127之後，第一凹陷125的一部分可被暴露出（例如在圖16中所看不到的視角中），並且在放置底部填充膠133期間，底部填充膠133會流到第一凹陷125中。
在圖17中，藉由沿著例如位於第一封裝區100A與第二封裝區100B之間的切割道區進行鋸切來執行單體化製程。鋸切步驟會將第一封裝區100A與第二封裝區100B單體化。所得的單體化的裝置堆疊來自第一封裝區100A或第二封裝區100B中的一者。在一些實施例中，在將第二封裝部件200耦合至第一封裝部件100之後執行單體化製程。在其他實施例（未示出）中，在將第二封裝部件200耦合至第一封裝部件100之前（例如在剝離載體基底102且形成導電連接件152之後）執行單體化製程。
然後，可使用導電連接件150將每一單體化的第一封裝部件100安裝至封裝基底300。封裝基底300包括基底芯體302及位於基底芯體302之上的接合接墊304。基底芯體302可由例如矽、鍺、金剛石或類似物等半導體材料製成。作為另一選擇，亦可使用例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、該些材料的組合及類似物等化合物材料。另外，基底芯體302可為SOI基底。一般而言，SOI基底包括由例如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合等半導體材料構成的層。在一個替代性實施例中，基底芯體302是基於例如玻璃纖維加強型樹脂芯體等絕緣芯體。一種示例性芯體材料是例如FR4等玻璃纖維樹脂。芯體材料的替代品包括雙馬來醯亞胺-三嗪BT樹脂，或者作為另一選擇包括其他PCB材料或膜。可對基底芯體302使用例如ABF等疊層膜或其他疊層體。
基底芯體302可包括主動裝置及被動裝置（未示出）。可使用各種各樣的裝置（例如電晶體、電容器、電阻器、該些的組合及類似物）來產生裝置堆疊的設計的結構要求及功能要求。可使用任何適合的方法來形成所述裝置。
基底芯體302亦可包括金屬化層及通孔（未示出），其中接合接墊304物理耦合至及/或電性耦合至金屬化層及通孔。可在主動裝置及被動裝置之上形成金屬化層，並且將金屬化層設計成連接各種裝置以形成功能電路系統。金屬化層可由介電材料（例如低k介電材料）與導電材料（例如銅）構成的交替層形成，其中通孔對導電材料層進行內連，並且可藉由任何適合的製程（例如沉積、鑲嵌、雙鑲嵌或類似製程）形成金屬化層。在一些實施例中，基底芯體302實質上不含主動裝置及被動裝置。
在一些實施例中，對導電連接件150進行回焊以將第一封裝部件100貼合至接合接墊304。導電連接件150將封裝基底300（包括基底芯體302中的金屬化層）電性耦合至及/或物理耦合至第一封裝部件100。在一些實施例中，在基底芯體302上形成阻焊劑306。可在阻焊劑306的開口中設置導電連接件150，以電性耦合至及機械耦合至接合接墊304。可使用阻焊劑306來保護基底202的區域免受外部損傷。
導電連接件150在被回焊之前可具有形成於其上的環氧焊劑（未示出），其中在將第一封裝部件100貼合至封裝基底300之後，環氧焊劑的至少一些環氧部分保留下來。此保留下來的環氧部分可充當底部填充膠，以減少應力並保護由對導電連接件150進行回焊產生的接頭。在一些實施例中，可在第一封裝部件100與封裝基底300之間形成環繞導電連接件150的底部填充膠308。可在貼合第一封裝部件100之後藉由毛細流動製程形成底部填充膠308，或者可在貼合第一封裝部件100之前藉由適合的沉積方法形成底部填充膠308。
在一些實施例中，亦可將被動裝置（例如表面安裝裝置（surface mount device，SMD）（未示出））貼合至第一封裝部件100（例如貼合至UBM 138）或貼合至封裝基底300（例如貼合至接合接墊304）。舉例而言，可將被動裝置接合至第一封裝部件100或封裝基底300的與導電連接件150相同的表面。可在將第一封裝部件100安裝於封裝基底300上之前將被動裝置貼合至第一封裝部件100，或者可在將第一封裝部件100安裝於封裝基底300上之前或之後將被動裝置貼合至封裝基底300。
可在其他裝置堆疊中實施第一封裝部件100。舉例而言，示出PoP結構，但亦可在覆晶球柵陣列（Flip Chip Ball Grid Array，FCBGA）封裝中實施第一封裝部件100。在此種實施例中，將第一封裝部件100安裝至例如封裝基底300等基底，但省略第二封裝部件200。可將蓋（lid）或散熱器替代地貼合至第一封裝部件100。當省略第二封裝部件200時，亦可省略背側重佈線結構及穿孔116。
亦可包括其他特徵及製程。舉例而言，可包括測試結構以幫助對三維（three-dimensional，3D）封裝或三維積體電路（three-dimensional integrated circuit，3DIC）裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或基底上形成的測試接墊（test pad），以便能夠對3D封裝或3DIC進行測試、使用探針及/或探針卡（probe card）以及進行類似操作。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可與包含對已知良好晶粒（known good die）進行中間驗證的測試方法結合使用以提高良率並降低成本。
藉由利用本文中呈現的材料及製程，介面材料提供更佳的整體結構及製程。具體而言，藉由使用具有更高導熱係數的材料，在操作期間可自晶粒散出更多的熱量。另外，藉由使用具有高剛性及拉伸強度的材料，可達成熱傳遞而不損失對裝置的結構支撐。
圖18示出其中介面材料127所具有的尺寸小於積體電路晶粒50的另一實施例。舉例而言，在其中積體電路晶粒50具有第二寬度W 2的實施例中，可將介面材料127形成為及/或放置成具有在約1.5 µm與約54.5 µm之間的第三寬度W 3。然而，可利用任何適合的尺寸。
藉由形成小於積體電路晶粒50的介面材料127，第一凹陷125被完全暴露出且未被介面材料127覆蓋。因此，在點膠及放置底部填充膠133期間，底部填充膠將流至第一凹陷125中並完全填充第一凹陷125。另外，所使用的介面材料127的材料減少，而使總成本減少。
圖19示出其中介面材料127所具有的尺寸等於積體電路晶粒50的另一實施例。舉例而言，在其中積體電路晶粒50具有第二寬度W 2的實施例中，可將介面材料127形成為及/或放置成亦具有第二寬度W 2。然而，可利用任何適合的尺寸。
藉由形成等於積體電路晶粒50的介面材料127，並且與以上針對圖18所述的實施例相似，在放置介面材料127之後，第一凹陷125被完全暴露出。因此，在點底部填充膠133期間，確保第一凹陷125被底部填充膠133所填充。另外，所使用的介面材料127的材料減少，而使總成本減少。
圖20示出其中介面材料127不是積體電路晶粒50中的每一者之上的單一連續材料而是包括介面材料127的多個不連續區段129的又一實施例。在實施例中，可將介面材料127分隔成二個或更多個區段，例如圖20中所示的三個區段，其中區段129中的每一者具有在約0.1 mm與約55 mm之間的第四寬度W 4，並且可彼此分隔開在約5 µm與約500 µm之間的第二距離D 2。在其他實施例中，區段129中的每一者具有彼此不同的尺寸。然而，可利用任何適合的距離及寬度。
藉由利用多個不連續區段129，積體電路晶粒50的特定各別區段可成為目標。舉例而言，若已知積體電路晶粒50的某些區段相對於積體電路晶粒50的其餘區段而言是熱點（hot spot），則可將所述多個不連續區段129放置於熱點之上，以便提供更佳的散熱路徑。
圖21示出其中介面材料127被用於實際填充第一凹陷125的又一實施例。在此種實施例中，介面材料127的流動性（fluidity）提高，以使得當施加介面材料127時，介面材料127的一部分會流至第一凹陷125中並會環繞半導體基底52的部分。在實施例中，介面材料127的流動性可藉由壓力或溫度來提高。然而，可利用任何適合的方法。
圖22A至圖22D示出其中介面材料127被用於基底上晶圓上晶片（CoWoS）封裝2200內的另一實施例。先參照圖22A，其中示出貼合至第一中介層2203的半導體晶粒2201（具有底部填充膠）。在實施例中，半導體晶粒2201可為例如邏輯晶粒、DRAM晶粒、SRAM晶粒、中央處理單元晶粒、輸入/輸出（input/output，I/O）晶粒、該些的組合或類似物等半導體裝置。另外，儘管半導體晶粒2201可為相同類型的裝置（例如二者均為DRAM晶粒），其亦可為不同類型的晶粒（例如一者可為邏輯晶粒，而另一者可為例如高頻寬記憶體（HBM）晶粒等DRAM晶粒）。半導體晶粒2201亦可包括由多個晶粒構成的堆疊。可利用半導體晶粒的任何適合的組合及任何數目的半導體晶粒，並且所有此種數目、組合及功能皆完全旨在包括於所述實施例的範圍內。
接下來，參照第一中介層2203，第一中介層2203可包括具有基底穿孔（TSV）的中介層基底。在此實施例中，中介層基底可為例如經摻雜或未經摻雜的矽基底或者絕緣體上矽（SOI）基底的主動層。然而，中介層基底亦可為玻璃基底、陶瓷基底、聚合物基底或可提供適合的保護及/或內連線功能的任何其他基底。作為另一選擇，可對中介層基底使用該些及任何其他適合的材料。
在一些實施例中，中介層基底可包括例如電阻器、電容器、訊號分配電路系統、該些的組合或類似物等電性組件。該些電性組件可為主動的、被動的或其組合。在其他實施例中，中介層基底中不含主動電性組件及被動電性組件二者。所有此種組合皆完全旨在包括於所述實施例的範圍內。
半導體晶粒2201可接合至第一中介層2203且其間可放置底部填充膠。另外，為保護所述結構，半導體晶粒2201可被包封於第一中介層2203之上。
第一中介層2203可接合至第三基底2205（例如其間具有底部填充膠），以形成基底上晶圓上晶片（CoWoS）結構。在實施例中，第三基底2205可為印刷電路板，例如被形成為由例如雙馬來醯亞胺三嗪（BT）、FR-4、ABF或類似物等聚合物材料形成的多個薄層（或疊層體）的堆疊的疊層基底。然而，作為另一選擇，可利用例如矽中介層、矽基底、有機基底、陶瓷基底或類似物等任何其他適合的基底，並且提供支撐及連接性的所有此種重佈線基底皆完全旨在包括於所述實施例的範圍內。
圖22A另外示出，一旦將CoWoS封裝2200放於一起，便可將介面材料127放置於半導體晶粒2201上。在實施例中，介面材料127可如上放置（例如使用疊層方法）至第一厚度。然而，可利用放置介面材料127的任何適合的方法。
圖22B示出介面材料127已被點膠後黏合劑2207的放置。在一些實施例中，黏合劑2207是包含懸浮於矽脂（silicone grease）中的銀、鎳或鋁顆粒的金屬基底散熱膏。在其他實施例中，可應用填充有例如氧化鈹、氮化鋁、氧化鋁或氧化鋅等陶瓷粉末的非導電陶瓷基底膏。在其他實施例中，黏合劑2207不再是具有與凝膠或油膏相似的稠度（consistency）的膏，而是可為固體材料。在此實施例中，黏合劑2207可為導熱固體材料的薄片材。在特定實施例中，為固體的黏合劑2207可為由銦、鎳、銀、鋁、該些的組合及合金或類似物構成的薄片材，或者其他導熱固體材料。亦可利用任何適合的導熱材料，並且所有此種材料皆完全旨在包含於所述實施例的範圍內。
圖22C示出將蓋2209放置於介面材料127之上並利用黏合劑2207保持定位。在實施例中，蓋2209可包含銅、鋁、其他金屬、合金、其組合或具有高導電性及高導熱係數的其他材料。在一些實施例中，蓋2209被用來幫助分散自CoWoS結構2200所產生的熱量。
圖22D示出，一旦將蓋2209放置於介面材料127之上，便可將蓋2209密封至CoWoS結構2200。在一個實施例中，可使用熱能夾持方法（heat clamping method）來密封蓋2209，由此施加壓力及熱量以便將蓋2209密封至所述結構。然而，可利用密封蓋2209的任何適合的方法。
藉由利用本文中所述的材料及方法，所述散熱材料可用於增加自半導體晶粒（例如沿著積體扇出型封裝的背側）的散熱量。另外，藉由使用所述的方法及材料，可在不降低裝置整體結構完整性的條件下達成增加散熱量。因此，可達成更高效且結構上無損的裝置。
在實施例中，一種半導體裝置包括：包封半導體晶粒及穿孔的包封體，其中所述包封體沿著暴露出所述半導體晶粒的側壁的至少一部分的凹陷具有彎曲側壁、位於所述半導體晶粒之上的介面材料、以及位於所述介面材料周圍的底部填充材料。在實施例中，所述介面材料具有第一寬度，並且所述半導體晶粒具有小於所述第一寬度的第二寬度。在實施例中，所述介面材料具有第一寬度，並且所述半導體晶粒具有大於所述第一寬度的第二寬度。在實施例中，所述介面材料具有第一寬度，並且所述半導體晶粒具有所述第一寬度。在實施例中，所述介面材料填充所述凹陷。在實施例中，所述底部填充材料填充所述凹陷。在實施例中，所述介面材料具有在約15 W/k*m與約23 W/k*m之間的導熱係數、具有在約250 N/mm與約2500 N/mm之間的剛性且具有在約0.5 N*mm與約10 N*mm之間的黏性。
根據另一實施例，一種半導體裝置包括：在第一封裝與半導體晶粒之間延伸的介面材料，所述第一封裝藉由穿孔電性連接至所述半導體晶粒，所述穿孔所具有的高度大於所述半導體晶粒、環繞所述穿孔及所述半導體晶粒的包封體，所述包封體具有與所述半導體晶粒的側壁介接的彎曲表面、以及環繞所述介面材料且在所述第一封裝與所述包封體之間延伸的底部填充材料。在實施例中，所述底部填充材料與所述彎曲表面物理接觸。在實施例中，所述介面材料與所述彎曲表面物理接觸。在實施例中，所述包封體具有第一厚度，並且所述半導體晶粒具有小於所述第一厚度的第二厚度。在實施例中，所述介面材料具有在約15 W/k*m與約23 W/k*m之間的導熱係數。在實施例中，所述介面材料上覆於所述半導體晶粒的所述側壁之上。在實施例中，所述介面材料包括不連續區段。
根據又一實施例，一種製造半導體裝置的方法包括：鄰近於穿孔放置半導體晶粒，其中在所述放置所述半導體晶粒之後，黏合劑覆蓋所述半導體晶粒的側壁的至少一部分、在所述半導體晶粒與所述穿孔之間放置包封體，並且所述包封體與所述黏合劑物理接觸、移除所述黏合劑、在所述半導體晶粒之上但不在所述穿孔之上放置介面材料、與所述介面材料物理接觸地放置封裝，其中所述放置所述封裝會使所述介面材料壓縮、以及在所述封裝與所述半導體晶粒之間放置底部填充膠。在實施例中，所述方法更包括在放置所述半導體晶粒之前將所述黏合劑疊層至所述半導體晶粒。在實施例中，放置所述封裝會使所述介面材料壓縮至少20微米。在實施例中，放置所述底部填充膠會覆蓋所述半導體晶粒的所述側壁的所述部分。在實施例中，放置所述介面材料會覆蓋所述半導體晶粒的所述側壁的所述部分。在實施例中，所述黏合劑利用濕式蝕刻製程移除。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各態樣。熟習此項技術者應理解，他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，此種等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
50:積體電路晶粒 50A:積體電路晶粒/第一積體電路晶粒 50B:積體電路晶粒/第二積體電路晶粒 52:半導體基底 54:裝置 56:層間介電質（ILD） 58:導電插塞 60:內連線結構 62:接墊 64:鈍化膜 66:晶粒連接件 68、132:介電層 100:第一封裝部件 100A:封裝區/第一封裝區 100B:封裝區/第二封裝區 102:載體基底 104:離型層 114:虛線框 116:穿孔 118、2207:黏合劑 120:包封體 121:延伸部 122:前側重佈線結構 123、131:虛線 124、128、136:介電層 125:第一凹陷 126、130、134:金屬化圖案 127:介面材料 129:區段/不連續區段 133、308:底部填充膠 138:凸塊下金屬（UBM） 141:清潔製程 150、152:導電連接件 200:第二封裝部件 202:基底 204、206、304:接合接墊 208:導通孔 210A、210B:堆疊晶粒 212:導線接合 214:模製材料 300:封裝基底 302:基底芯體 306:阻焊劑 2200:基底上晶圓上晶片（CoWoS）封裝/CoWoS結構 2201:半導體晶粒 2203:第一中介層 2205:第三基底 2209:蓋 D 1:第一距離 D 2:第二距離 H 1:第一高度 H 2:第二高度 H 3:第三高度 H 4:第四高度 H 5:第五高度 W 1:第一寬度 W 2:第二寬度 W 3:第三寬度 W 4:第四寬度
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1示出根據一些實施例的積體電路晶粒的剖視圖。 圖2示出根據實施例的載體基底上的黏合層。 圖3示出根據實施例的穿孔的形成。 圖4A至圖4B示出根據實施例的積體電路晶粒的放置。 圖5示出根據實施例的包封體。 圖6示出根據實施例的包封體的平坦化。 圖7至圖10示出根據實施例的重佈線結構的形成。 圖11示出根據實施例的凸塊下金屬的放置。 圖12示出根據實施例的導電連接件的形成。 圖13示出根據實施例的載體基底的移除。 圖14A至圖14C示出根據實施例的黏合劑的移除。 圖15示出根據實施例的介面材料的放置。 圖16示出根據實施例的封裝的放置。 圖17示出根據實施例的單體化。 圖18示出根據實施例的其中介面材料小於半導體晶粒的實施例。 圖19示出根據實施例的其中介面材料等於半導體晶粒的實施例。 圖20示出根據實施例的其中介面材料包括不連續區段的實施例。 圖21示出根據實施例的其中介面材料填充凹陷的實施例。 圖22A至圖22D示出根據實施例的其中介面材料被用於基底上晶圓上晶片的配置的實施例。
100:第一封裝部件
127:介面材料
133、308:底部填充膠
138:凸塊下金屬(UBM)
150:導電連接件
200:第二封裝部件
300:封裝基底
302:基底芯體
304:接合接墊
306:阻焊劑

Claims (20)

  1. 一種半導體裝置，包括： 包封體，包封半導體晶粒及穿孔，其中所述包封體具有彎曲側壁，其中所述半導體晶粒的側壁的鄰近於所述彎曲側壁的一部分被暴露出； 介面材料，位於所述半導體晶粒之上；以及 底部填充材料，位於所述介面材料周圍。
  2. 如請求項1所述的半導體裝置，其中所述介面材料具有第一寬度，並且所述半導體晶粒具有小於所述第一寬度的第二寬度。
  3. 如請求項1所述的半導體裝置，其中所述介面材料具有第一寬度，並且所述半導體晶粒具有大於所述第一寬度的第二寬度。
  4. 如請求項1所述的半導體裝置，其中所述介面材料具有第一寬度，並且所述半導體晶粒具有所述第一寬度。
  5. 如請求項1所述的半導體裝置，其中所述介面材料填充所述彎曲側壁與所述半導體晶粒的所述側壁之間的區域。
  6. 如請求項1所述的半導體裝置，其中所述底部填充材料填充所述彎曲側壁與所述半導體晶粒的所述側壁之間的區域。
  7. 如請求項1所述的半導體裝置，其中所述介面材料具有在約15 W/K*m與約23 W/K*m之間的導熱係數、具有在約250 N/mm與約2500 N/mm之間的剛性且具有在約0.5 N*mm與約10 N*mm之間的黏性。
  8. 一種半導體裝置，包括： 介面材料，在第一封裝與半導體晶粒之間延伸，所述第一封裝藉由穿孔電性連接至所述半導體晶粒，所述穿孔所具有的高度大於所述半導體晶粒； 包封體，環繞所述穿孔及所述半導體晶粒，所述包封體具有與所述半導體晶粒的側壁介接的彎曲表面；以及 底部填充材料，環繞所述介面材料且在所述第一封裝與所述包封體之間延伸。
  9. 如請求項8所述的半導體裝置，其中所述底部填充材料與所述彎曲表面物理接觸。
  10. 如請求項8所述的半導體裝置，其中所述介面材料與所述彎曲表面物理接觸。
  11. 如請求項8所述的半導體裝置，其中所述包封體具有第一厚度，並且所述半導體晶粒具有小於所述第一厚度的第二厚度。
  12. 如請求項8所述的半導體裝置，其中所述介面材料具有在約15 W/K*m與約23 W/K*m之間的導熱係數。
  13. 如請求項8所述的半導體裝置，其中所述介面材料上覆於所述半導體晶粒的所述側壁之上。
  14. 如請求項8所述的半導體裝置，其中所述介面材料包括不連續區段。
  15. 一種製造半導體裝置的方法，所述方法包括： 鄰近於穿孔放置半導體晶粒，其中在放置所述半導體晶粒之後，黏合劑覆蓋所述半導體晶粒的側壁的至少一部分； 在所述半導體晶粒與所述穿孔之間放置包封體，並且所述包封體與所述黏合劑物理接觸； 移除所述黏合劑； 在所述半導體晶粒之上但不在所述穿孔之上放置介面材料； 與所述介面材料物理接觸地放置封裝，其中放置所述封裝使所述介面材料壓縮；以及 在所述封裝與所述半導體晶粒之間放置底部填充膠。
  16. 如請求項15所述的方法，更包括： 在放置所述半導體晶粒之前，將所述黏合劑疊層至所述半導體晶粒。
  17. 如請求項15所述的方法，其中放置所述封裝使所述介面材料壓縮至少20微米。
  18. 如請求項15所述的方法，其中放置所述底部填充膠會覆蓋所述半導體晶粒的所述側壁的所述部分。
  19. 如請求項15所述的方法，其中放置所述介面材料會覆蓋所述半導體晶粒的所述側壁的所述部分。
  20. 如請求項15所述的方法，其中所述黏合劑利用濕式蝕刻製程移除。
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