CN114038842A - 半导体器件和制造方法 - Google Patents

半导体器件和制造方法 Download PDF

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Publication number
CN114038842A
CN114038842A CN202110545334.7A CN202110545334A CN114038842A CN 114038842 A CN114038842 A CN 114038842A CN 202110545334 A CN202110545334 A CN 202110545334A CN 114038842 A CN114038842 A CN 114038842A
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Prior art keywords
die
semiconductor die
interface material
semiconductor
integrated circuit
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CN202110545334.7A
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Inventor
陈志豪
王卜
郑礼辉
卢思维
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN114038842A publication Critical patent/CN114038842A/zh
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Abstract

提供了一种半导体器件以及制造方法，其中，从嵌入在密封剂内的半导体管芯去除粘合剂，并且利用界面材料从半导体器件去除热量。粘合剂的去除留下邻接半导体的侧壁的凹进，并且填充凹进。

Description

半导体器件和制造方法
技术领域
本申请的实施例涉及半导体器件和制造方法。
背景技术
由于各种电子组件(例如晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体工业经历了快速的增长。大多数情况下，集成密度的提高可以从迭代减小最小特征尺寸、从而允许更多组件集成至给定区域中来获得。随着对缩小的电子器件的需求的增长，已经出现了对更小并且更具创造性的半导体管芯的封装技术的需求。这种封装系统的一个示例是封装上封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部，以提供高级别的集成度和组件密度。PoP技术通常能够在印刷电路板(PCB)上生产具有增强的功能和小的占位面积的半导体器件。
发明内容
本申请的实施例提供了一种半导体器件，包括：密封剂，密封半导体管芯和贯穿通孔，其中，所述密封剂具有弯曲的侧壁，其中，邻接所述弯曲的侧壁的所述半导体管芯的侧壁的部分暴露出来；界面材料，位于所述半导体管芯上方；以及底部填充材料，位于所述界面材料周围。
本申请的实施例提供了一种半导体器件，包括：界面材料，在第一封装件和半导体管芯之间延伸，所述第一封装件通过贯穿通孔电连接至所述半导体管芯，所述贯穿通孔具有大于所述半导体管芯的高度；密封剂，围绕所述贯穿通孔和所述半导体管芯，所述密封剂具有与所述半导体管芯的侧壁交界的弯曲的表面；以及底部填充材料，围绕所述界面材料，并且在所述第一封装件和所述密封剂之间延伸。
本申请的实施例还提供一种制造半导体器件的方法，所述方法包括：放置半导体管芯使得邻接贯穿通孔，其中，在所述放置所述半导体管芯之后，粘合剂覆盖所述半导体管芯的侧壁的至少一部分；放置密封剂使得位于所述半导体管芯和所述贯穿通孔之间，并且与所述粘合剂物理接触；去除所述粘合剂；放置界面材料使得位于所述半导体管芯上方，但是并不位于所述贯穿通孔上方；放置封装件使得与所述界面材料物理接触，其中，所述放置所述封装件使得压缩所述界面材料；以及放置底部填充物使得位于所述封装件和所述半导体管芯之间。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的集成电路管芯的截面图；
图2示出了根据一个实施例的载体衬底上的粘合层；
图3示出了根据一个实施例的贯穿通孔的形成；
图4A-图4B示出了根据一个实施例的集成电路管芯的布置；
图5示出了根据一个实施例的密封剂；
图6示出了根据一个实施例的密封剂的平坦化；
图7-图10示出了根据一个实施例的再分布结构的形成；
图11示出了根据一个实施例的凸块下金属化件的布置；
图12示出了根据一个实施例的导电连接器的形成；
图13示出了根据一个实施例的载体衬底的去除；
图14A-图14C示出了根据一个实施例的粘合剂的去除；
图15示出了根据一个实施例的界面材料的布置；
图16示出了根据一个实施例的封装件的布置；
图17示出了根据一个实施例的单个化；
图18示出了根据一个实施例的其中界面材料小于半导体管芯的实施例；
图19示出了根据一个实施例的其中界面材料等于半导体管芯的实施例；
图20示出了根据一个实施例的其中界面材料包括非连续部分的实施例；
图21示出了根据一个实施例的其中界面材料填充凹进的实施例；
图22A-图22D示出了根据一个实施例的其中界面材料应用于衬底上晶圆上芯片配置中的实施例。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。另外，本发明可以在各个实例中重复参考数字和/或字母。该重复是出于简化和清楚的目的，其本身并不指示所讨论的各种实施例和/或结构之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以容易地描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
现在将参考特定结构和方法来描述实施例，其中，利用界面材料在集成扇出封装内提供界面。但是，本文描述的实施例并不旨在限制所描述的实施例，实施例可以以任何合适的结构和方法来实施，例如以集成扇出大规模集成结构(InFO-LSI)、集成扇出多芯片结构(InFO-M)、衬底上晶圆上芯片(CoWoS)结构、或者集成电路上系统(SoIC)结构来实施。所有这些实施例完全旨在包括在实施例的范围内。
图1示出了根据一些实施例的集成电路管芯50的截面图。集成电路管芯50将在随后的处理中进行封装，以形成集成电路封装件。集成电路管芯50可以是逻辑管芯(例如中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、应用处理器(AP)、微控制器等)、存储器管芯(例如动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如数字信号处理(DSP)管芯)、前端管芯(例如模拟前端(AFE)管芯)等、或其组合。
集成电路管芯50可以形成在晶圆中，其可以包括在后续步骤中进行单个化、以形成多个集成电路管芯的不同的器件区。集成电路管芯50可以根据适用的制造工艺进行处理，以形成集成电路。例如，集成电路管芯50包括诸如掺杂或者未掺杂的硅的半导体衬底52，或者绝缘体上半导体(SOI)衬底的有源层。半导体衬底52可以包括其他半导体材料，例如：锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP；或其组合。也可以使用其他衬底，例如多层衬底或者梯度衬底。半导体衬底52具有：有源表面(例如在图1中面向上的表面)，有时称为正面；以及无源表面(例如在图1中面向下的表面)，有时称为背面。
器件(由晶体管表示)54可以形成在半导体衬底52的正面。器件54可以是有源器件(例如晶体管、二极管等)、电容器、电阻器等。层间电介质(ILD)56位于半导体衬底52的正面上方。ILD56围绕并且可以覆盖器件54。ILD56可以包括一个或者多个通过诸如磷硅玻璃(PSG)、硼硅玻璃(BSG)、硼掺杂磷硅玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)等的材料形成的介电层。
导电插塞58延伸穿过ILD 56，以电地和物理地连接器件54。例如，当器件54是晶体管时，导电插塞58可以连接晶体管的栅极和源极/漏极区。导电插塞58可以通过钨、钴、镍、铜、银、金、铝等、或其组合来形成。互连结构60位于ILD 56和导电插塞58上方。互连结构60互连器件54，以形成集成电路。互连结构60可以通过例如位于ILD 56上的介电层中的金属化图案来形成。金属化图案包括形成在一个或者多个低k介电层中的金属导线和通孔。互连结构60的金属化图案通过导电插塞58电连接至器件54。
集成电路管芯50进一步包括通过其进行外部连接的焊盘62，例如铝焊盘。焊盘62位于集成电路管芯50的有源侧上，例如位于互连结构60之内和/或之上。一个或者多个钝化膜64位于集成电路管芯50上，例如位于互连结构60和焊盘62的部分上。开口穿过钝化膜64延伸至焊盘62。诸如导电柱(例如通过诸如铜的金属形成)的管芯连接器66延伸穿过钝化膜64中的开口，并且物理地和电地连接至焊盘62中的相应的一个。管芯连接器66可以通过例如镀敷等来形成。管芯连接器66电连接集成电路管芯50的相应的集成电路。
可选地，焊料区(例如焊料球或者焊料块)可以设置在焊盘62上。焊料球可以用于在集成电路管芯50上实施芯片探针(CP)测试。CP测试可以实施在集成电路管芯50上，以确定集成电路管芯50是否是已知的良好管芯(KGD)。因此，仅其为KGD的集成电路管芯50经历后续处理并且进行封装，而未通过CP测试的管芯不进行封装。测试之后，可以在随后的处理步骤中去除焊料区。
介电层68可以(或者可以不)位于集成电路管芯50的有源侧上，例如位于钝化膜64和管芯连接器66上。介电层68横向地密封管芯连接器66，并且介电层68与集成电路管芯50横向地毗连。首先，介电层68可以掩埋管芯连接器66，从而介电层68的最顶面位于管芯连接器66的最顶面上方。在将焊料区设置在管芯连接器66上的实施例中，介电层68也可以掩埋焊料区。可替代地，可以在形成介电层68之前去除焊料区。
介电层68可以是：聚合物，例如PBO、聚酰亚胺、BCB等；氮化物，例如氮化硅等；氧化物，例如氧化硅、PSG、BSG、BPSG等；等等；或其组合。介电层68可以例如通过旋涂、层压、化学气相沉积(CVD)等来形成。在一些实施例中，管芯连接器66在集成电路管芯50的形成期间通过介电层68暴露。在一些实施例中，管芯连接器66保持掩埋，并且在随后的用于封装集成电路管芯50的工艺期间暴露。暴露管芯连接器66可以去除可能存在于管芯连接器66上的任何焊料区。
在一些实施例中，集成电路管芯50是包括多个半导体衬底52的堆叠器件。例如，集成电路管芯50可以是存储器器件，例如混合存储器数据集(HMC)模块、高带宽存储器(HBM)模块等，其包括多个存储器管芯。在这样的实施例中，集成电路管芯50包括通过贯穿衬底通孔(TSV)互连的多个半导体衬底52。每个半导体衬底52可以(或者可以不)具有互连结构60。
图2至图20示出了根据一些实施例的在用于形成第一封装组件100的工艺期间的中间步骤的截面图。示出了第一封装区100A和第二封装区100B，并且一个或者多个集成电路管芯50进行封装，以在每个封装区100A和100B中形成集成电路封装件。集成电路封装件也可以称为集成扇出(InFO)封装件。
在图2中，提供了载体衬底102，并且剥离层104形成在载体衬底102上。载体衬底102可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底102可以是晶圆，从而多个封装件可以同时地形成在载体衬底102上。
剥离层104可以通过聚合物基的材料形成，其可以与载体衬底102一起从将会在后续步骤中形成的上覆结构去除。在一些实施例中，剥离层104是环氧基的热剥离材料，其在受热时会失去其粘合特性，例如光热转换(LTHC)剥离涂层。在其他实施例中，剥离层104可以是紫外线(UV)胶，其在暴露于UV光时会失去其粘合特性。剥离层104可以以液体的形式进行分配，并且进行固化，可以是层压至载体衬底102上的层压膜，或者可以是类似物。剥离层104的顶面可以是水平的，并且可以具有高度的平面度。
可选地，背面再分布结构(未单独示出)可以形成在剥离层104上。在所示的实施例中，背面再分布结构包括介电层、金属化图案(有时称为再分布层或者再分布线)、和介电层。在一些实施例中，在剥离层104上形成的是不具有金属化图案的介电层，而不是背面再分布结构。
介电层可以形成在剥离层104上。介电层的底面可以接触剥离层104的顶面。在一些实施例中，介电层通过诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物来形成。在其他实施例中，介电层通过以下材料来形成：氮化物，例如氮化硅；氧化物，例如氧化硅、磷硅玻璃(PSG)、硼硅玻璃(BSG)、掺硼磷硅玻璃(BPSG)等；等等。介电层可以通过任何可接受的沉积工艺来形成，例如通过旋涂、CVD、层压等、或其组合来形成。
金属化图案可以形成在介电层上。作为形成金属化图案的示例，晶种层形成在介电层上方。在一些实施例中，晶种层是金属层，其可以是单层，或者是包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层，和位于钛层上方的铜层。晶种层可以使用例如物理气相沉积(PVD)等来形成。然后光刻胶(未示出)形成并且图案化在晶种层上。光刻胶可以通过旋涂等来形成，并且可以暴露至光，用以进行图案化。光刻胶的图案对应于金属化图案。图案化可以形成穿过光刻胶以暴露出晶种层的开口。导电材料形成在光刻胶的开口中和晶种层的暴露部分上。导电材料可以通过诸如电镀或者化学镀等的镀敷来形成。导电材料可以包括金属，例如铜、钛、钨、铝等。然后，去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或者剥离工艺，例如使用氧等离子体等，来去除光刻胶。一旦去除了光刻胶，就去除了晶种层的暴露部分，例如通过使用可接受的蚀刻工艺，例如通过湿蚀刻或者干蚀刻。晶种层和导电材料的所剩部分形成金属化图案。
介电层可以形成在金属化图案和介电层上。在一些实施例中，介电层通过聚合物形成，其可以是光敏材料，例如PBO、聚酰亚胺、BCB等，其可以使用光刻掩模来图案化。在其他实施例中，介电层通过以下材料形成：氮化物，例如氮化硅；氧化物，例如氧化硅、PSG、BSG、BPSG；等等。介电层可以通过旋涂、层压、CVD等、或其组合来形成。然后介电层进行图案化，以形成暴露金属化图案的部分的开口。图案化可以通过可接受的工艺来形成，例如当介电层是光敏材料时通过将介电层暴露至光来形成，或者通过使用例如各向异性蚀刻进行蚀刻来形成。如果介电层是光敏材料，则介电层可以在曝光后进行显影。
在一些实施例中，背面再分布结构可以包括任意数量的介电层和金属化图案。如果要形成更多的介电层和金属化图案，则可以重复以上所讨论的步骤和工艺。金属化图案可以包括一个或者多个导电元件。可以通过在下面的介电层的表面上方和下面的介电层的开口中形成晶种层和金属化图案的导电材料，从而互连和电连接各种导线，来在金属化图案的形成期间形成导电元件。
在图3中，贯穿通孔116形成在剥离层104或者背面再分布结构(如果存在的话)上。作为形成贯穿通孔116的示例，晶种层(未示出)形成在剥离层104上方。在一些实施例中，晶种层是金属层，其可以是单层，或者是包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层包括钛层，和位于钛层上方的铜层。晶种层可以使用例如PVD等来形成。光刻胶形成并且图案化在晶种层上。光刻胶可以通过旋涂等形成，并且可以暴露至光，用以进行图案化。光刻胶的图案对应于导电通孔。图案化可以形成穿过光刻胶以暴露出晶种层的开口。导电材料形成在光刻胶的开口中和晶种层的暴露部分上。导电材料可以通过诸如电镀或者化学镀等的镀敷来形成。导电材料可以包括金属，例如铜、钛、钨、铝等。去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或者剥离工艺，例如使用氧等离子体等，来去除光刻胶。一旦去除了光刻胶，就去除了晶种层的暴露部分，例如通过使用可接受的蚀刻工艺，例如通过湿蚀刻或者干蚀刻。晶种层和导电材料的所剩部分形成贯穿通孔116。
在图4A中，集成电路管芯50(例如第一集成电路管芯50A和第二集成电路管芯50B)通过粘合剂118粘合至剥离层104。所需类型和数量的集成电路管芯50粘合在封装区100A和100B中的每一者中。在所示的实施例中，多个集成电路管芯50彼此相邻地粘合，包括位于第一封装区100A和第二封装区100B的每一者中的第一集成电路管芯50A和第二集成电路管芯50B。第一集成电路管芯50A可以是逻辑器件，例如中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、微控制器等。第二集成电路管芯50B可以是存储器器件，例如动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯、混合存储器数据集(HMC)模块、高带宽存储器(HBM)模块等。在一些实施例中，集成电路管芯50A和50B可以是相同类型的管芯，例如SoC管芯。第一集成电路管芯50A和第二集成电路管芯50B可以在相同技术节点的工艺中形成，或者可以在不同技术节点的工艺中形成。例如，与第二集成电路管芯50B相比，第一集成电路管芯50A可以是在更高级的工艺节点中形成。集成电路管芯50A和50B可以具有不同的尺寸(例如不同的高度和/或表面积)，或者可以具有相同的尺寸(例如相同的高度和/或表面积)。在第一封装区100A和第二封装区100B中用于贯穿通孔116的空间可能是有限的，特别是当集成电路管芯50包括具有大占位面积的器件(例如SoC)时。
粘合剂118位于集成电路管芯50的背面上，并且将集成电路管芯50粘合至载体衬底102。粘合剂118可以是任何合适的粘合剂、环氧树脂、管芯连接膜(DAF)等。粘合剂118可以施加至集成电路管芯50的背面，如果不使用背面再分布结构，则可以施加在载体衬底102的表面上方，或者，如果使用背面再分布结构，则可以施加至背面再分布结构的上表面。例如，可以在单个化以使集成电路管芯50分隔开之前，将粘合剂118施加至集成电路管芯50的背面。
图4B示出了图4A中标记为114的虚线框的特写视图。可以看出，在将粘合剂118放置在表面(例如集成电路管芯50或者剥离层104)上之后，并且在将集成电路管芯50放置之后，粘合剂118进行压缩并且延伸超过集成电路管芯50的外侧壁，从而形成延伸部121。在一个实施例中，粘合剂118的延伸部121可以延伸在约1μm和约30μm之间的第一距离D1。另外，未位于集成电路管芯50下方的粘合剂118可以具有大于位于集成电路管芯50下方的粘合剂118的高度的第一高度H1，例如具有在约1μm和约30μm之间的第一高度H1。但是，可以利用任何合适的高度。
在图5中，密封剂120形成在各个部件之上和周围，并且与延伸部121物理接触。在形成之后，密封剂120密封贯穿通孔116和集成电路管芯50。密封剂120可以是模制化合物、环氧树脂等。密封剂120可以通过压缩模制、传递模制等来施加，并且可以形成在载体衬底102上方，从而掩埋或者覆盖贯穿通孔116和/或集成电路管芯50。密封剂120进一步形成在集成电路管芯50之间的间隙区域中。密封剂120可以以液体或者半液体形式进行施加，然后随后进行固化。
在图6中，平坦化工艺实施在密封剂120上，以暴露出贯穿通孔116和管芯连接器66。平坦化工艺还可以去除贯穿通孔116、介电层68、和/或管芯连接器66的材料，直至暴露出管芯连接器66和贯穿通孔116。在工艺变化内，在平坦化工艺之后，贯穿通孔116、管芯连接器66、介电层68、和密封剂120的顶面基本上共面。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果贯穿通孔116和/或管芯连接器66已经暴露，则可以省略平坦化。
在图7至图10中，正面再分布结构122(参见图10)形成在密封剂120、贯穿通孔116、和集成电路管芯50上方。正面再分布结构122包括介电层124、128、132、和136，以及金属化图案126、130、和134。金属化图案也可以称为再分布层或者再分布线。正面再分布结构122示出为具有三层金属化图案的示例。更多或者更少的介电层和金属化图案可以形成在正面再分布结构122中。如果要形成更少的介电层和金属化图案，则可以省略下面讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复下面讨论的步骤和工艺。
在图7中，介电层124沉积在密封剂120、贯穿通孔116、和管芯连接器66上。在一些实施例中，介电层124通过诸如PBO、聚酰亚胺、BCB等的光敏材料来形成，其可以使用光刻掩模进行图案化。介电层124可以通过旋涂、层压、CVD等、或其组合来形成。然后，介电层124进行图案化。图案化可以形成暴露出贯穿通孔116和管芯连接器66的部分的开口。图案化可以通过可接受的工艺来形成，例如当介电层124是光敏材料时通过将介电层124暴露并且显影至光来形成，或者通过使用例如各向异性蚀刻进行蚀刻来形成。
然后形成金属化图案126。金属化图案126包括沿着介电层124的主表面延伸并且延伸穿过介电层124以物理地和电地连接至贯穿通孔116和集成电路管芯50的导电元件。作为形成金属化图案126的示例，晶种层形成在介电层124上方和延伸穿过介电层124的开口中。在一些实施例中，晶种层是金属层，其可以是单层，或者是包括由不同的材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层，和位于钛层上方的铜层。晶种层可以使用例如PVD等来形成。然后，光刻胶形成并且图案化在晶种层上。光刻胶可以通过旋涂等来形成，并且可以暴露至光，用以进行图案化。光刻胶的图案对应于金属化图案126。图案化可以形成穿过光刻胶以暴露出晶种层的开口。然后，导电材料可以形成在光刻胶的开口中和晶种层的暴露部分上。导电材料可以通过诸如电镀或者化学镀等的镀敷来形成。导电材料可以包括金属，例如铜、钛、钨、铝等。导电材料和下面的晶种层部分的组合形成金属化图案126。去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或者剥离工艺，例如使用氧等离子体等，来去除光刻胶。一旦去除了光刻胶，就去除了晶种层的暴露部分，例如通过使用可接受的蚀刻工艺，例如通过湿蚀刻或者干蚀刻。
在图8中，介电层128沉积在金属化图案126和介电层124上。介电层128可以以与介电层124类似的方式来形成，并且可以通过与介电层124类似的材料来形成。
然后形成金属化图案130。金属化图案130包括位于介电层128的主表面上、并且沿着介电层128的主表面延伸的部分。金属化图案130还包括延伸穿过介电层128以物理地和电地连接金属化图案126的部分。金属化图案130可以以与金属化图案126类似的方式和通过与金属化图案126类似的材料来形成。在一些实施例中，金属化图案130具有与金属化图案126不同的尺寸。例如，金属化图案130的导线和/或通孔可以比金属化图案126的导线和/或通孔更宽或者更厚。另外，金属化图案130可以形成为比金属化图案126具有更大的间距。
在图9中，介电层132沉积在金属化图案130和介电层128上。介电层132可以以与介电层124类似的方式来形成，并且可以通过与介电层124类似的材料来形成。
然后形成金属化图案134。金属化图案134包括位于介电层132的主表面上、并且沿着介电层132的主表面延伸的部分。金属化图案134还包括延伸穿过介电层132以物理地和电地连接金属化图案130的部分。金属化图案134可以以与金属化图案126类似的方式和通过与金属化图案126类似的材料来形成。金属化图案134是正面再分布结构122的最顶部金属化图案。于是，正面再分布结构122的所有中间金属化图案(例如金属化图案126和130)设置在金属化图案134和集成电路管芯50之间。在一些实施例中，金属化图案134具有与金属化图案126和130不同的尺寸。例如，金属化图案134的导线和/或通孔可以比金属化图案126和130的导线和/或通孔更宽或者更厚。另外，金属化图案134可以形成为比金属化图案130具有更大的间距。
在图10中，介电层136沉积在金属化图案134和介电层132上。介电层136可以以与介电层124类似的方式来形成，并且可以通过与介电层124相同的材料来形成。介电层136是正面再分布结构122的最顶部介电层。于是，正面再分布结构122的所有金属化图案(例如金属化图案126、130、和134)设置在介电层136和集成电路管芯50之间。另外，正面再分布结构122的所有中间介电层(例如介电层124、128、132)都设置在介电层136和集成电路管芯50之间。
在图11中，形成凸块下金属化件(UBM)138，用于外部连接至正面再分布结构122。UBM138具有位于介电层136的主表面上并且沿着介电层136的主表面延伸的凸块部分，以及具有延伸穿过介电层136以物理地和电地连接金属化图案134的通孔部分。结果，UBM 138电连接至贯穿通孔116和集成电路管芯50。UBM138可以通过与金属化图案126相同的材料形成。在一些实施例中，UBM 138具有与金属化图案126、130、和134不同的尺寸。
在图12中，导电连接器150形成在UBM 138上。导电连接器150可以是球栅阵列(BGA)连接器、焊料球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍化学钯浸金技术(ENEPIG)形成的凸块等。导电连接器150可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等、或其组合的导电材料。在一些实施例中，导电连接器150通过首先通过蒸发、电镀、印刷、焊料转移、焊球放置等形成焊料层来形成。一旦一层焊料形成在结构上，就可以实施回流，以使材料成形为所需的凸块形状。在另一个实施例中，导电连接器150包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(例如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，金属覆盖层形成在金属柱的顶部上。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等、或其组合，并且可以通过镀敷工艺形成。
在图13中，实施载体衬底去接合，以分离(或者“去接合”)载体衬底102。根据一些实施例，去接合包括在剥离层104上投射诸如激光或者UV光的光，使得剥离层104在光的热量下分解，从而可以去除载体衬底102和剥离层104。然后将结构翻转并且放置在胶带(未显示)上。
在图14A中，实施清洁工艺(在图14A中由标记为141的波浪线表示)，以确保将剥离层104的所有剩余部分完全去除，并且将粘合剂118去除。在一个实施例中，清洁工艺141可以使用等离子体清洁工艺、湿蚀刻工艺、其组合等来实施。但是，可以实施任何合适的清洁。
一旦已经完全去除剥离层104，就去除粘合剂118，以暴露出集成电路管芯50的背面，从而去除可能限制散热效率的材料。在一个实施例中，粘合剂118可以使用干蚀刻工艺(例如等离子体蚀刻工艺)或者湿蚀刻工艺来去除。在使用湿蚀刻工艺的实施例中，将诸如二甲基亚砜(DMSO)、TMAH、其组合等的溶剂或者蚀刻剂施加至粘合剂118。一旦物理接触，则溶剂或者蚀刻剂可以用于物理地或者化学地去除粘合剂118的材料。但是，可以使用任何合适的方法去除粘合剂118。
另外，密封剂120可以凹进，以暴露出贯穿通孔116的侧壁。在一个实施例中，密封剂120可以通过一个或者多个清洁工艺141或者用于去除粘合剂118的工艺来凹进。在另一个实施例中，密封剂120可以在诸如湿蚀刻或者干蚀刻工艺的单独的蚀刻工艺中来凹进。
图14B示出了图14A中标记为123的虚线框的特写视图。如图14B中可见，通过去除粘合剂118，也去除了粘合剂118的延伸部121。于是，第一凹进125形成在粘合剂118的延伸部121的位置和形状中，并且第一凹进125将具有与粘合剂118的延伸部121类似的形状和尺寸(例如第一高度H1和第一距离D1)。但是，可以使用任何合适的尺寸和形状。
图14C示出了图14A中标记为131的虚线框的特写视图。如图14C中可见，在用以去除剥离层104的清洁工艺141和粘合剂118的去除之后，集成电路管芯50、密封剂120、和贯穿通孔116中的每一者可以具有背离正面再分布结构122延伸的不同的高度。例如，集成电路管芯50可以具有在约20μm和约700μm之间的第二高度H2；密封剂120可以具有大于第二高度H2的第三高度H3，例如具有在约25μm和约705μm之间的第三高度H3；贯穿通孔116可以具有大于第三高度H3的第四高度H4，例如具有在约30μm和约710μm之间的第四高度H4。但是，可以使用任何合适的尺寸。
图15示出了位于集成电路管芯50上方、但不位于贯穿通孔116上方、从而将集成电路管芯50与上覆结构(图15中未示出，但在下文中示出和描述)相连接的界面材料127的放置。在一个实施例中，界面材料127可以是高度可压缩、具有高粘合力、并且具有高导热率的预成型膜。例如，在一些实施例中，预成型膜可以具有的导热率为在约15W/k*m和约60W/K*m之间，例如大于约20W/K*m；其刚度为在约250N/mm和约2500N/mm之间；粘性为在约0.5N*mm和约10N*mm之间；拉伸强度为在约0.01MPa和约5.0MPa之间。但是，可以利用任何合适的参数。
在特定实施例中，界面材料127是诸如铅锡基焊料(PbSn)、无铅焊料、铟、碳复合材料、石墨、碳纳米管、或者其他合适的导热材料的材料。作为薄膜，界面材料127可以使用层压工艺、拾取和放置工艺、其组合等，放置成初始厚度在约40μm和约300μm之间，并且沿着集成电路管芯50的背面未使用粘合材料(例如管芯连接材料或者聚合物缓冲层)。但是，可以使用任何合适的放置和任何合适的厚度。
另外，如图15所示，界面材料127所具有的第一宽度W1大于集成电路管芯50的第二宽度W2。于是，在该实施例中，界面材料127在第一凹进125上方延伸，并且覆盖第一凹进125。例如，在集成电路管芯50具有在约2mm和约55mm之间的第二宽度W2的实施例中，界面材料127具有在约2.5mm和约55.5mm之间的第一宽度W1。但是，可以使用任何合适的尺寸。
图16示出了形成导电连接器152，用以接触贯穿通孔116。在一些实施例中，导电连接器152包括助熔剂，并且在助熔剂浸渍工艺中形成。在一些实施例中，导电连接器152包括诸如焊料浆料、银浆料等的导电浆料，并且在印刷工艺中进行分配。在一些实施例中，导电连接器152以与导电连接器150类似的方式来形成，并且可以通过与导电连接器150类似的材料来形成。另外，在一些实施例中，可以在导电连接器152的形成期间形成金属间化合物(IMC)。
图16另外示出了根据一些实施例的器件堆叠件的形成和实施。器件堆叠件通过形成在第一封装组件100中的集成电路封装件形成。器件堆叠件也可以称为封装上封装(PoP)结构。在图16中，第二封装组件200连接至第一封装组件100。第二封装组件200中的每一者连接在封装区100A和100B中的每一者中，以在第一封装组件100的每个区域中形成集成电路器件堆叠件。
第二封装组件200包括例如衬底202和连接至衬底202的一个或者多个堆叠管芯210(例如210A和210B)。虽然示出了一组堆叠管芯210(210A和210B)，但是在其他实施例中，可以将多个堆叠管芯210(每个具有一个或者多个堆叠管芯)设置成并排连接至衬底202的同一表面。衬底202可以通过诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化砷化镓、磷化镓铟、其组合等的化合物材料。另外，衬底202可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，例如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)、或其组合。在一个可替代的实施例中，衬底202基于诸如玻璃纤维增强树脂芯的绝缘芯。一种示例性芯材料是玻璃纤维树脂，例如FR4。可替代的芯材料包括双马来酰亚胺三嗪(BT)树脂，或者可替代地，其他印刷电路板(PCB)材料或者薄膜。诸如味之素(Ajinomoto)堆积膜(ABF)的堆积膜或者其他叠层可以用于衬底202。
衬底202可以包括有源器件和无源器件(未示出)。可以使用诸如晶体管、电容器、电阻器、其组合等的多种器件，来产生用于第二封装组件200的设计的结构和功能需求。可以使用任何合适的方法来形成器件。
衬底202还可以包括金属化层(未示出)和导电通孔208。金属化层可以形成在有源器件和无源器件上方，并且设计为连接各种器件以形成功能电路。金属化层可以通过介电材料(例如低k介电材料)和导电材料(例如铜)的交替层来形成，其中通孔互连导电材料层，并且可以通过任何合适的工艺(例如沉积、镶嵌、双重镶嵌等)来形成。在一些实施例中，衬底202基本上没有有源器件和无源器件。
衬底202可以具有位于衬底202的第一侧上以连接至堆叠管芯210的接合焊盘204，和位于衬底202的第二侧上以连接至导电连接器152的接合焊盘206，衬底202的第二侧与第一侧相对。在一些实施例中，接合焊盘204和206通过形成进入至衬底202的第一侧和第二侧上的介电层(未示出)中的凹进(未示出)来形成。凹进可以形成为使得接合焊盘204和206嵌入至介电层中。在其他实施例中，由于接合焊盘204和206可以形成在介电层上，因此可以省略凹进。在一些实施例中，接合焊盘204和206包括通过铜、钛、镍、金、钯等、或其组合制成的薄晶种层(未示出)。接合焊盘204和206的导电材料可以沉积在薄晶种层上方。导电材料可以通过电化学镀工艺、化学镀工艺、CVD、原子层沉积(ALD)、PVD等、或其组合来形成。在一个实施例中，接合焊盘204和206的导电材料是铜、钨、铝、银、金等、或其组合。
在一些实施例中，接合焊盘204和接合焊盘206是UBM，其包括三层导电材料，例如钛层、铜层、和镍层。材料和层的其他布置，例如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置、或者铜/镍/金的布置，可以用于接合焊盘204和206的形成。可以用于接合焊盘204和206的任何合适的材料或者材料层可以完全旨在包括在本申请的范围内。在一些实施例中，导电通孔208延伸穿过衬底202，并且将接合焊盘204中的至少一个连接至接合焊盘206中的至少一个。
在所示的实施例中，堆叠管芯210通过导线接合212连接至衬底202，虽然可以使用其他连接，例如导电凸块。在一个实施例中，堆叠管芯210是堆叠的存储器管芯。例如，堆叠管芯210可以是存储器管芯，例如低功率(LP)双倍数据速率(DDR)存储器模块，例如LPDDR1、LPDDR2、LPDDR3、LPDDR4、类似的存储器模块。
可以通过模制材料214密封堆叠管芯210和导线接合212。模制材料214可以例如使用压缩模制而模制在堆叠管芯210和导线接合212上。在一些实施例中，模制材料214是模制化合物、聚合物、环氧树脂、氧化硅填充材料等、或其组合。可以实施固化工艺，以固化模制材料214；固化工艺可以是热固化、UV固化等、或其组合。
在一些实施例中，堆叠管芯210和导线接合212可以掩埋在模制材料214中，并且在模制材料214固化之后，实施诸如研磨的平坦化步骤，以去除模制材料214的多余部分，并且提供用于第二封装组件200的基本平坦的表面。
在形成第二封装组件200之后，第二封装组件200通过导电连接器152、接合焊盘206、和背面再分布结构的金属化图案，而机械地和电地接合至第一封装组件100。在一些实施例中，堆叠管芯210可以通过导线接合212、接合焊盘204和206、导电通孔208、导电连接器152、背面再分布结构、贯穿通孔116、和正面再分布结构122，接合至集成电路管芯50A和50B。
在一些实施例中，阻焊剂(未示出)形成在衬底202的与堆叠管芯210相对的一侧上。导电连接器152可以设置在阻焊剂中的开口中，以电地和机械地连接至衬底202中的导电部件(例如接合焊盘206)。阻焊剂可以用于保护衬底202的区域免受外部损坏。
在一些实施例中，导电连接器152可以在其回流之前在其上形成有环氧焊剂(未示出)，其中环氧焊剂的环氧部分中的至少一些保留到第二封装组件200连接至第一封装组件100之后。
在第二封装组件200接合至第一封装组件100之后，界面材料127从其初始沉积厚度进行压缩。在一些实施例中，在接合之后，界面材料127已经压缩为具有在约20μm和约200μm之间的第五高度H5。于是，界面材料127可以压缩至少5μm。另外，界面材料127的厚度(例如第五高度H5)和集成电路管芯50的厚度(例如第二高度H2)的组合大于在约0.5μm和约50μm之间的密封剂120的厚度(例如第三高度H3)。但是，可以使用任何合适的厚度。
另外，即使界面材料127将会压缩为具有第五高度H5，界面材料127在压缩之后仍将保持其侧壁。特别地，界面材料127将具有尖锐的、垂直的(或者几乎垂直的)侧壁。
通过使用具有这种可压缩性的界面材料127，可以减轻关于不良的凸块接合性能的问题。特别地，通过使用可压缩的界面材料127，使得界面材料127不妨碍导电连接器152的放置和接合。于是，只会出现较少的缺陷。
在一些实施例中，底部填充物133形成在第一封装组件100和第二封装组件200之间，其围绕导电连接器152。底部填充物133可以减小应力，并且保护由导电连接器152的回流而得到的接头。底部填充物133可以在第二封装组件200连接之后通过毛细管流动工艺形成，或者可以在第二封装组件200连接之前通过合适的沉积方法形成。
另外，在一些实施例中，底部填充物133将另外填充通过去除粘合剂118的延伸部121而形成的第一凹进125。例如，在放置界面材料127之后，可以暴露第一凹进125的部分(例如在图16中不可见的视图中)，从而底部填充物133将在底部填充物133的放置期间流入第一凹进125中。
在图17中，通过沿着例如第一封装区100A和第二封装区100B之间的划线区域进行锯切，来实施单个化工艺。锯切使得第一封装区100A从第二封装区100B单个化。所得的单个化的器件堆叠件来自第一封装区100A或者第二封装区100B中的一者。在一些实施例中，在第二封装组件200连接至第一封装组件100之后，实施单个化工艺。在其他实施例(未示出)中，在第二封装组件200连接至第一封装组件100之前，例如在将载体衬底102去接合和形成导电连接器152之后，实施单个化工艺。
然后，可以使用导电连接器150，将每个单个化的第一封装组件100安装至封装衬底300。封装衬底300包括衬底芯302和位于衬底芯302上方的接合焊盘304。衬底芯302可以通过诸如硅、锗、金刚石等的半导体材料制成。可替代地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化砷化镓、磷化铟镓、其组合等的化合物材料。另外，衬底芯302可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI、或其组合的半导体材料层。在一个可替代的实施例中，衬底芯302基于诸如玻璃纤维增强树脂芯的绝缘芯。一种示例性芯材料是玻璃纤维树脂，例如FR4。可替代的芯材料包括双马来酰亚胺三嗪BT树脂，或者可替代地，其他PCB材料或者薄膜。诸如ABF的堆积膜或者其他层压材料可以用于衬底芯302。
衬底芯302可以包括有源器件和无源器件(未示出)。可以使用诸如晶体管、电容器、电阻器、其组合等的多种器件来产生用于器件堆叠件的设计的结构和功能需求。可以使用任何合适的方法来形成器件。
衬底芯302还可以包括金属化层和通孔(未示出)，其中接合焊盘304物理地和/或电地连接至金属化层和通孔。金属化层可以形成在有源器件和无源器件上方，并且设计成连接各种器件以形成功能电路。金属化层可以通过介电材料(例如低k介电材料)和导电材料(例如铜)的交替层来形成，其中通孔互连导电材料层，并且可以通过任何合适的工艺(例如沉积、镶嵌、双重镶嵌等)来形成。在一些实施例中，衬底芯302基本上没有有源器件和无源器件。
在一些实施例中，导电连接器150进行回流，以将第一封装组件100连接至接合焊盘304。导电连接器150电地和/或物理地将包括衬底芯302中的金属化层的封装衬底300连接至第一封装组件100。在一些实施例中，阻焊剂306形成在衬底芯302上。导电连接器150可以设置在阻焊剂306中的开口中，以电地和机械地连接至接合焊盘304。阻焊剂306可以用于保护衬底202的区域免受外部损坏。
导电连接器150可以在其回流之前在其上形成有环氧焊剂(未示出)，其中环氧焊剂的环氧部分中的至少一些保留到第一封装组件100连接至封装衬底300之后。该保留的环氧树脂部分可以充当底部填充物，以减少应力，并且保护由于回流导电连接器150而得到的接头。在一些实施例中，底部填充物308可以形成在第一封装组件100和封装衬底300之间，并且围绕导电连接器150。底部填充物308可以在连接第一封装组件100之后通过毛细管流动工艺形成，或者可以在连接第一封装组件100之前通过合适的沉积方法形成。
在一些实施例中，无源器件(例如表面安装器件(SMD)，未示出)也可以连接至第一封装组件100(例如至UBM 138)，或者连接至封装衬底300(例如至接合焊盘304)。例如，无源器件可以与导电连接器150接合至第一封装组件100或者封装衬底300的相同表面。无源器件可以在将第一封装组件100安装在封装衬底300上之前连接至第一封装组件100，或者可以在将第一封装组件100安装在封装衬底300上之前或者之后连接至封装衬底300。
第一封装组件100可以实现在其他器件堆叠件中。例如，示出了PoP结构，但是第一封装组件100也可以以倒装芯片球栅阵列(FCBGA)封装件来实现。在这样的实施例中，第一封装组件100安装至诸如封装衬底300的衬底，但是第二封装组件200省略。替代地，可以将盖部或者散热器连接至第一封装组件100。当第二封装组件200省略时，背面再分布结构和贯穿通孔116也可以省略。
还可以包括其他部件和工艺。例如，可以包括测试结构，以辅助3D封装件或者3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或者衬底上的测试焊盘，其允许使用探针和/或探针卡等对3D封装或者3DIC进行测试。验证测试可以在中间结构以及最终结构上实施。另外，本文公开的结构和方法可以与结合了已知良好的管芯的中间验证的测试方法结合使用，以增加产量并且降低成本。
通过利用本文提出的材料和工艺，界面材料提供了更好的整体结构和工艺。特别地，通过使用具有较高导热率的材料，可以在操作期间从管芯去除更多的热量。另外，通过使用具有高刚度和拉伸强度的材料，可以实现热传递而不会损失用于器件的结构支撑。
图18示出了另一个实施例，其中界面材料127具有小于集成电路管芯50的尺寸。例如，在其中集成电路管芯50具有第二宽度W2的实施例中，界面材料127可以形成为和/或放置为具有在约1.5μm和约54.5μm之间的第三宽度W3。但是，可以使用任何合适的尺寸。
通过形成小于集成电路管芯50的界面材料127，第一凹进125完全暴露并且未由界面材料127覆盖。于是，在分配和放置底部填充物133期间，底部填充物将会流入并且完全填充第一凹进125。另外，可以使用界面材料127的较少材料，从而获得较低的总成本。
图19示出了另一个实施例，其中界面材料127具有等于集成电路管芯50的尺寸。例如，在其中集成电路管芯50具有第二宽度W2的实施例中，界面材料127可以形成为和/或放置为也具有第二宽度W2。但是，可以使用任何合适的尺寸。
通过形成等于集成电路管芯50的界面材料127，并且类似于以上关于图18所描述的实施例，在放置界面材料127之后，第一凹进125完全暴露。于是，在分配底部填充物133期间，第一凹进125确保由底部填充物133填充。另外，可以使用界面材料127的较少的材料，从而获得较低的总成本。
图20示出了又一个实施例，其中，界面材料127不是位于每个集成电路管芯50上方的单个连续材料，而是包括界面材料127的多个非连续部分129。在一个实施例中，界面材料127可以分成两个或者更多个部分，例如图20中所示的三个部分，其中每个部分129具有在约0.1mm和约55mm之间的第四宽度W4，并且可以以在约5μm和约500μm之间的第二距离D2彼此间隔开。在其他实施例中，每个部分129具有彼此不同的尺寸。但是，可以使用任何合适的距离和宽度。
通过使用多个非连续部分129，可以将集成电路管芯50的特定单个部分作为目标。例如，如果集成电路管芯50的某些部分已知是相对于集成电路管芯50的其余部分的热点，则多个非连续部分129可以放置在热点上方，以提供用于散热的更好的路径。
图21示出了又一个实施例，其中界面材料127用于实际填充第一凹进125。在这样的实施例中，界面材料127的流动性提高为使得当施加界面材料127时，界面材料127的一部分将会流入第一凹进125中，并且将会围绕半导体衬底52的部分。在一个实施例中，界面材料127的流动性可以通过压力或者温度来提高。但是，可以使用任何合适的方法。
图22A-图22D示出了另一实施例，其中界面材料127使用在衬底上晶圆上芯片(CoWoS)封装件2200内。首先看图22A，示出了连接至第一插件2203的半导体管芯2201(具有底部填充物)。在一个实施例中，半导体管芯2201可以是半导体器件，例如逻辑管芯、DRAM管芯、SRAM管芯、中央处理单元管芯、I/O管芯、其组合等。另外，虽然半导体管芯2201可以是相同类型的器件(例如都是DRAM管芯)，但是其也可以是不同类型的管芯(例如，一个可以是逻辑管芯，而另一个可以是诸如高带宽存储器(HBM)管芯的DRAM管芯)。半导体管芯2201还可以包括多个管芯的堆叠。可以使用半导体管芯的任何合适的组合，以及半导体管芯的任何数目，并且所有这样的数目、组合、和功能都完全旨在包括在实施例的范围内。
接下来看第一插件2203，第一插件2203可以包括具有贯穿衬底通孔(TSV)的插件衬底。在该实施例中，插件衬底可以是例如掺杂的或者未掺杂的硅衬底，或者是绝缘体上硅(SOI)衬底的有源层。但是，插件衬底也可以是玻璃衬底、陶瓷衬底、聚合物衬底、或者可以提供合适的保护和/或互连功能的任何其他衬底。这些和任何其他合适的材料可以可替代地用于插件衬底。
在一些实施例中，插件衬底可以包括电元件，例如电阻器、电容器、信号分布电路、其组合等。这些电元件可以是有源的、无源的、或其组合。在其他实施例中，插件衬底中没有有源的和无源的电元件。所有这些组合完全旨在包括在实施例的范围内。
半导体管芯2201可以接合至第一插件2203，并且底部填充物可以放置在两者之间。另外，为了保护该结构，半导体管芯2201可以密封在第一插件2203上方。
第一插件2203可以接合至第三衬底2205(利用例如两者之间的底部填充物)，以形成衬底上晶圆上芯片(CoWoS)结构。在一个实施例中，第三衬底2205可以是印刷电路板，例如形成为诸如双马来酰亚胺三嗪(BT)、FR-4、ABF等聚合物材料的多个薄层(或者层压体)的堆叠件的层压衬底。但是，可以可替代地使用任何其他合适的衬底，例如硅插件、硅衬底、有机衬底、陶瓷衬底等，并且所有这些提供支持和连接性的再分布衬底完全旨在包括在实施例的范围内。
图22A另外示出，一旦CoWoS封装件2200已经放置在一起，界面材料127就可以放置在半导体管芯2201上。在一个实施例中，界面材料127可以如以上所描述的(例如使用层压方法)放置成第一厚度。但是，可以使用放置界面材料127的任何合适的方法。
图22B示出了在已经分配了界面材料127之后的粘合剂2207的放置。在一些实施例中，粘合剂2207是金属基的导热浆料，其包含悬浮在硅脂中的银、镍、或者铝颗粒。在其他实施例中，可以施加填充有陶瓷粉末(例如氧化铍、氮化铝、氧化铝、或者氧化锌)的非导电陶瓷基浆料。在其他实施例中，粘合剂2207可以是固体材料，而不是具有类似于凝胶或者油脂的稠度的浆料。在该实施例中，粘合剂2207可以是导热固体材料的薄片。在特定实施例中，其为固体的粘合剂2207可以是铟、镍、银、铝、其组合和合金等、或者其他导热固体材料的薄片。也可以使用任何合适的导热材料，并且所有这样的材料完全旨在包括在实施例的范围内。
图22C示出了位于界面材料127上方、并且用粘合剂2207保持位置的盖部2209的放置。在一个实施例中，盖部2209可以包括铜、铝、其他金属、合金、其组合、或者高电导率和导热率的其他材料。在一些实施例中，盖部2209用来帮助分散从CoWoS结构2200产生的热量。
图22D示出，一旦将盖部2209放置在界面材料127上方，就可以将盖部2209密封至CoWoS结构2200。在一个实施例中，盖部2209可以使用热夹紧方法来密封，从而施加压力和热量，以将盖部2209密封至所述结构。但是，可以使用任何合适的密封盖部2209的方法。
通过利用本文描述的材料和方法，可以使用热材料来提高从半导体管芯(例如沿着集成扇出封装件的背面)的散热。另外，通过使用所描述的方法和材料，可以实现提高散热，但无需承受器件的整体结构完整性降低。于是，可以实现更加有效和结构合理的器件。
在一个实施例中，一种半导体器件包括：密封剂，密封半导体管芯和贯穿通孔，其中，密封剂具有沿着凹进的弯曲的侧壁，其暴露出半导体管芯的侧壁的至少一部分；界面材料，位于半导体管芯上方；以及底部填充材料，位于界面材料周围。在一个实施例中，界面材料具有第一宽度，并且半导体管芯具有小于第一宽度的第二宽度。在一个实施例中，界面材料具有第一宽度，并且半导体管芯具有大于第一宽度的第二宽度。在一个实施例中，界面材料具有第一宽度，并且半导体管芯具有第一宽度。在一个实施例中，界面材料填充凹进。在一个实施例中，底部填充材料填充凹进。在一个实施例中，界面材料具有在约15W/K*m和约23W/K*m之间的导热率，具有在约250N/mm和约2500N/mm之间的刚度，并且具有在约0.5N*mm和约10N*mm之间的粘性。
根据另一个实施例，半导体器件包括：界面材料，在第一封装件和半导体管芯之间延伸，第一封装件通过贯穿通孔电连接至半导体管芯，贯穿通孔具有大于半导体管芯的高度；密封剂，围绕贯穿通孔和半导体管芯，密封剂具有与半导体管芯的侧壁交界的弯曲的表面；底部填充材料，围绕界面材料，并且在第一封装件和密封剂之间延伸。在一个实施例中，底部填充物与弯曲的表面物理接触。在一个实施例中，界面材料与弯曲的表面物理接触。在一个实施例中，密封剂具有第一厚度，并且半导体管芯具有小于第一厚度的第二厚度。在一个实施例中，界面材料具有在约15W/K*m和约23W/K*m之间的导热率。在一个实施例中，界面材料覆盖半导体管芯的侧壁。在一个实施例中，界面材料包括非连续部分。
根据又一个实施例，一种制造半导体器件的方法，包括：放置半导体管芯使得邻接贯穿通孔，其中，在放置半导体管芯之后，粘合剂覆盖半导体管芯的侧壁的至少一部分；放置密封剂使得位于半导体管芯和贯穿通孔之间，并且与粘合剂物理接触；去除粘合剂；放置界面材料使得位于半导体管芯上方，但是并不位于贯穿通孔上方；放置封装件使得与界面材料物理接触，其中，放置封装件使得压缩界面材料；以及放置底部填充物使得位于封装件和半导体管芯之间。在一个实施例中，该方法还包括在放置半导体管芯之前，将粘合剂层压至半导体管芯。在一个实施例中，放置封装件使得压缩界面材料至少20μm。在一个实施例中，放置底部填充物使得覆盖半导体管芯的侧壁的部分。在一个实施例中，放置界面材料使得覆盖半导体管芯的侧壁的部分。在一个实施例中，粘合剂通过湿蚀刻工艺去除。
本申请的实施例提供了一种半导体器件，包括：密封剂，密封半导体管芯和贯穿通孔，其中，所述密封剂具有弯曲的侧壁，其中，邻接所述弯曲的侧壁的所述半导体管芯的侧壁的部分暴露出来；界面材料，位于所述半导体管芯上方；以及底部填充材料，位于所述界面材料周围。在一些实施例中，界面材料具有第一宽度，并且所述半导体管芯具有小于所述第一宽度的第二宽度。在一些实施例中，界面材料具有第一宽度，并且所述半导体管芯具有大于所述第一宽度的第二宽度。在一些实施例中，界面材料具有第一宽度，并且所述半导体管芯具有所述第一宽度。在一些实施例中，界面材料填充所述弯曲的侧壁和所述半导体管芯的所述侧壁的所述侧壁之间的区域。在一些实施例中，底部填充材料填充所述弯曲的侧壁和所述半导体管芯的所述侧壁的所述侧壁之间的区域。在一些实施例中，界面材料具有在约15W/K*m和约23W/K*m之间的导热率，具有在约250N/mm和约2500N/mm之间的刚度，并且具有在约0.5N*mm和约10N*mm之间的粘性。
本申请的实施例提供了一种半导体器件，包括：界面材料，在第一封装件和半导体管芯之间延伸，所述第一封装件通过贯穿通孔电连接至所述半导体管芯，所述贯穿通孔具有大于所述半导体管芯的高度；密封剂，围绕所述贯穿通孔和所述半导体管芯，所述密封剂具有与所述半导体管芯的侧壁交界的弯曲的表面；以及底部填充材料，围绕所述界面材料，并且在所述第一封装件和所述密封剂之间延伸。在一些实施例中，底部填充物与所述弯曲的表面物理接触。在一些实施例中，界面材料与所述弯曲的表面物理接触。在一些实施例中，密封剂具有第一厚度，并且所述半导体管芯具有小于所述第一厚度的第二厚度。在一些实施例中，界面材料具有在约15W/K*m和约23W/K*m之间的导热率。在一些实施例中，界面材料覆盖所述半导体管芯的所述侧壁。在一些实施例中，界面材料包括非连续部分。
本申请的实施例还提供一种制造半导体器件的方法，所述方法包括：放置半导体管芯使得邻接贯穿通孔，其中，在所述放置所述半导体管芯之后，粘合剂覆盖所述半导体管芯的侧壁的至少一部分；放置密封剂使得位于所述半导体管芯和所述贯穿通孔之间，并且与所述粘合剂物理接触；去除所述粘合剂；放置界面材料使得位于所述半导体管芯上方，但是并不位于所述贯穿通孔上方；放置封装件使得与所述界面材料物理接触，其中，所述放置所述封装件使得压缩所述界面材料；以及放置底部填充物使得位于所述封装件和所述半导体管芯之间。在一些实施例中，还包括：在所述放置所述半导体管芯之前，将所述粘合剂层压至所述半导体管芯。在一些实施例中，放置所述封装件使得压缩所述界面材料至少20μm。在一些实施例中，放置所述底部填充物使得覆盖所述半导体管芯的所述侧壁的所述部分。在一些实施例中，放置所述界面材料使得覆盖所述半导体管芯的所述侧壁的所述部分。在一些实施例中，粘合剂通过湿蚀刻工艺去除。
前面概述了若干实施例的特征，使得本领域的技术人员可以更好地理解本公开的各个方面。本领域的技术人员应该理解，他们可以容易地使用本公开作为用于设计或修改用于执行与本公开相同或类似的目的和/或实现相同或类似优点的其他工艺和结构的基础。本领域的技术人员还应该意识到，这种等效结构不背离本公开的精神和范围，并且可以进行各种改变、替换和变更而不背离本公开的精神和范围。

Claims (10)

1.一种半导体器件，包括：
密封剂，密封半导体管芯和贯穿通孔，其中，所述密封剂具有弯曲的侧壁，其中，邻接所述弯曲的侧壁的所述半导体管芯的侧壁的部分暴露出来；
界面材料，位于所述半导体管芯上方；以及
底部填充材料，位于所述界面材料周围。
2.根据权利要求1所述的半导体器件，其中，所述界面材料具有第一宽度，并且所述半导体管芯具有小于所述第一宽度的第二宽度。
3.根据权利要求1所述的半导体器件，其中，所述界面材料具有第一宽度，并且所述半导体管芯具有大于所述第一宽度的第二宽度。
4.根据权利要求1所述的半导体器件，其中，所述界面材料具有第一宽度，并且所述半导体管芯具有所述第一宽度。
5.根据权利要求1所述的半导体器件，其中，所述界面材料填充所述弯曲的侧壁和所述半导体管芯的所述侧壁的所述侧壁之间的区域。
6.根据权利要求1所述的半导体器件，其中，所述底部填充材料填充所述弯曲的侧壁和所述半导体管芯的所述侧壁的所述侧壁之间的区域。
7.根据权利要求1所述的半导体器件，其中，所述界面材料具有在约15W/K*m和约23W/K*m之间的导热率，具有在约250N/mm和约2500N/mm之间的刚度，并且具有在约0.5N*mm和约10N*mm之间的粘性。
8.一种半导体器件，包括：
界面材料，在第一封装件和半导体管芯之间延伸，所述第一封装件通过贯穿通孔电连接至所述半导体管芯，所述贯穿通孔具有大于所述半导体管芯的高度；
密封剂，围绕所述贯穿通孔和所述半导体管芯，所述密封剂具有与所述半导体管芯的侧壁交界的弯曲的表面；以及
底部填充材料，围绕所述界面材料，并且在所述第一封装件和所述密封剂之间延伸。
9.根据权利要求8所述的半导体器件，其中，所述底部填充物与所述弯曲的表面物理接触。
10.一种制造半导体器件的方法，所述方法包括：
放置半导体管芯使得邻接贯穿通孔，其中，在所述放置所述半导体管芯之后，粘合剂覆盖所述半导体管芯的侧壁的至少一部分；
放置密封剂使得位于所述半导体管芯和所述贯穿通孔之间，并且与所述粘合剂物理接触；
去除所述粘合剂；
放置界面材料使得位于所述半导体管芯上方，但是并不位于所述贯穿通孔上方；
放置封装件使得与所述界面材料物理接触，其中，所述放置所述封装件使得压缩所述界面材料；以及
放置底部填充物使得位于所述封装件和所述半导体管芯之间。
CN202110545334.7A 2020-10-19 2021-05-19 半导体器件和制造方法 Pending CN114038842A (zh)

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