CN109390292A - 电子封装件及其制法 - Google Patents
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Abstract
一种电子封装件及其制法,其设置至少一电子元件与至少一调整件于一承载件上,且该调整件位于对应该电子元件的至少任两侧面的位置,再形成封装层于该承载件上以包覆该电子元件与调整件,之后移除该承载件,以通过该调整件的设置而减少该封装层的使用量,进而降低该电子封装件发生翘曲的机率。
Description
技术领域
本发明有关一种半导体结构,尤指一种半导体封装结构及其制法。
背景技术
随着电子产业的蓬勃发展,电子产品也逐渐迈向多功能、高性能的趋势。为了满足半导体封装件微型化(miniaturization)的封装需求,扇出(Fan-Out)型的线路结构应用越来越普及,进而发展出晶圆级封装(Wafer Level Packaging,简称WLP)的技术,此技术经常使用封装胶体(molding compound)包覆晶片,再制作扇出型的线路重布层(Redistribution layer,简称RDL),以电性连接该晶片。
如图1A至图1D,其为现有晶圆级半导体封装件1的制法的剖面示意图。
如图1A所示,提供一具有热化离型胶层(thermal release tape)11的承载件10。
接着,置放多个半导体元件12于该热化离型胶层11上,且该些半导体元件12具有相对的主动面12a与非主动面12b,其中,该主动面12a具有多个电极垫120,并以该主动面12a黏着于该热化离型胶层11上。
如图1B所示,以模压(molding)方式形成一封装胶体13于该热化离型胶层11上,以包覆该半导体元件12。
如图1C所示,进行烘烤制程以硬化该封装胶体13,且同时该热化离型胶层11因受热后会失去黏性,再一并移除该热化离型胶层11与该承载件10,以外露该半导体元件12的主动面12a。
如图1D所示,进行扇出型的线路重布层(RDL)制程,其形成一线路部14于该封装胶体13与该半导体元件12的主动面12a上,令该线路部14电性连接该半导体元件12的电极垫120。接着,形成一绝缘保护层15于该线路部14上,且该绝缘保护层15外露该线路部14的部分表面,以供结合如焊锡凸块的导电元件16。之后进行切单制程。
然而,当晶片设计越来越薄而晶圆尺寸越做越大时,若将晶片布设成重置构造(reconstruction)(也就是晶圆切单后,将晶片重新排设成长条状或晶圆状,如图1A所示)后制作扇出型线路结构,该封装胶体13在平面(xy轴)方向展开的面积将越来越大,致使热膨胀系数(Coefficient of thermal expansion,简称CTE)乘上大面积而放大的收缩/膨胀值也相对增加,造成封装结构容易产生翘曲(warpage)问题。
具体地,现有半导体封装件1的制法中,由于该半导体元件12与该封装胶体13热膨胀系数(CTE)不匹配(mismatch),因而容易发生热应力不均匀的情况,致使热循环(thermalcycle)时,造成该封装胶体13翘曲,如图1D’所示,致使该线路部14与该半导体元件12的电极垫120间的对位产生偏移。故而,当该承载件10的尺寸越大时,各该半导体元件12间的位置公差亦随之加大,而当翘曲过大时,将使该线路部14无法与该电极垫120连接,也就是对该线路部14与该半导体元件12间的电性连接造成极大影响,甚至造成导电元件16损坏(如图1D’所示的破裂处),因而造成良率过低及产品可靠度不佳等问题。
因此,如何克服上述现有技术的种种问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失,本发明提供一种电子封装件及其制法,能降低电子封装件发生翘曲的机率。
本发明的电子封装件,包括:封装层;电子元件,其具有多个侧面且嵌埋于该封装层中;以及调整件,其嵌埋于该封装层中并与该电子元件分离设置,其中,该调整件对应位于该电子元件的至少二侧面之处,且该调整件的外形呈中空形、类L形或类I字形。
本发明亦提供一种电子封装件的制法,包括:设置至少一电子元件与至少一调整件于一承载件上,其中,该调整件位于对应该电子元件的至少任两侧面的位置;进行预烤;于该预烤后静置;形成封装层于该承载件上以包覆该调整件与该电子元件;以及移除该承载件。
前述的制法中,还包括于移除该承载件后,进行切单制程,且该调整件与该电子元件仍保留于该封装层中。
前述的制法中,该调整件的外形呈中空形、类L形或类I字形。
前述的电子封装件及其制法中,形成该调整件的材质为硅或玻璃。
另外,前述的电子封装件及其制法中,还包括形成一线路部于该封装层与该电子元件上,且该线路部电性连接该电子元件。该线路部包含相叠的至少一介电层与至少一线路层,且该线路层电性连接该电子元件。
由上可知,本发明的电子封装件及其制法,通过形成该封装层之前,先设置该调整件,以减少该封装层的使用量,通过当CTE较高的该封装层的使用量越少时,该电子封装件发生翘曲的机率也相对变小,因而能避免良率过低及产品可靠度不佳等问题。
附图说明
图1A至图1D为现有半导体封装件的制法的剖面示意图;
图1D’为现有半导体封装件于制程中发生翘曲问题的示意图;
图2A至图2E为本发明的电子封装件的制法的剖面示意图;
图2E’为图2E的另一实施例;以及
图3A至图3C为对应图2A的单一置放区的不同实施例的平面上视图。
符号说明:
1 半导体封装件
10,20 承载件
11 热化离型胶层
12 半导体元件
12a,22a 主动面
12b,22b 非主动面
120,220 电极垫
13 封装胶体
14,24 线路部
15,25 绝缘保护层
16,26 导电元件
2 电子封装件
200 载板
201 离型层
202 黏着层
21 调整件
22 电子元件
22c 侧面
23,23’ 封装层
23a 表面
240 介电层
241 线路层
242 导电盲孔
A 置放区
k 破裂处
S 切割路径。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”及“一”等的用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当亦视为本发明可实施的范畴。
图2A至图2E为本发明的电子封装件2的制法的剖面示意图。
如图2A所示,设置多个电子元件22于一承载件20上,例如将该些电子元件22排列成晶圆(wafer)布设状态的重置构造(reconstruction),且设置至少一调整件21于该承载件20上,且令该调整件21位于该电子元件22的周围而未遮盖该电子元件22。
于本实施例中,该承载件20可依需求选择胶带、晶圆型基板(Wafer formsubstrate)或一般面板型基板(Panel form substrate)。该承载件20可包括例如晶圆、硅板等的半导体材或玻璃材的圆形暂时性载板200,该载板200上依序形成有一离型层201与一黏着层202,并以黏着层202结合该些电子元件22与该调整件21,其中,该承载件20定义有多个置放区A,且该黏着层202例如为热化离型胶层(thermal release tape)。于该承载件20具有胶材,当该电子元件22与调整件21设置于承载件20,时,可进行预烤,使该电子元件22与调整件21更稳固黏着于该承载件20上,且于预烤后,还可静置一段时间,使原本下压黏固于该承载件20的该电子元件22与调整件21恢复高度,而不下陷于该承载件20的表面,以得到更佳的平整度。
此外,该电子元件22为主动元件、被动元件或其二者组合,其中,该主动元件为例如晶片,而该被动元件为例如电阻、电容及电感。具体地,将晶圆切割后所得的晶片作为电子元件22,再将该些电子元件22重新排列于该承载件20的置放区A上,其中,该电子元件22具有相对的主动面22a与非主动面22b及多个邻接该主动面22a与非主动面22b的侧面22c,该主动面22a上具有多个电极垫220,且该电子元件22以其主动面22a结合该黏着层202。
又,于置放该些电子元件22时,同时置放该调整件21于该置放区A并位于电子元件22的周围而未遮盖该电子元件22的非主动面22b,以减少后续封装材的使用量。具体地,该调整件21的外形及其与晶片的相对位置可依需求设计,例如位于该电子元件22的至少任两侧的位置,如图3A所示的环状或中空形、图3B所示的连续线状或类L形、图3C所示的分离线状或类I字形等,故该调整件21的构造种类繁多,并不限于上述。
另外,该调整件21的结构特性需要不易变形(即不可变形性或高强度),且其热膨胀系数(CTE)需接近该电子元件22(或硅材)的热膨胀系数,故该调整件21可为硅块(dummysilicon)、玻璃等构造,且该调整件21的CTE不高于10(in 10-6/K20℃)。
如图2B所示,形成一封装层23于该承载件20的黏着层202上,以包覆该调整件21与该些电子元件22。
于本实施例中,形成该封装层23的材质为聚酰亚胺(polyimide,简称PI)、干膜(dry film)、环氧树脂(epoxy)、或如液态封装胶体(liquid molding compound)、移转模造胶体(transfer molding compound)等的封装材。
此外,该封装层23为压合制程用的薄膜,或者,该封装层23亦可例如模压制程用的封装胶体或印刷制程用的胶材等。例如,于模压制程前,可先进行预烘烤(pre bake)制程,再进行涂胶(dispensing)作业以将该封装层23涂布于该些电子元件22上,再以模具将该封装层23压制出所需的外观。因此,有关该封装层23的材质或形成方式并无特别限制。
又,该电子元件22的主动面22a与该封装层23的表面23a为共平面。
如图2C所示,移除该承载件20,以露出该电子元件22的主动面22a与该调整件21。
于本实施例中,以机械方式或以移除离型层方式移除该载板200。例如,进行烘烤制程以硬化该封装层23,而同时该黏着层202因受热后会失去黏性,故可移除该黏着层202与该载板200及其上的离型层201。
如图2D所示,将排列成晶圆(wafer)布设状态的重置构造(reconstruction)的多个电子元件22翻面,进行扇出(Fan-Out)型线路重布层(RDL)制程,即形成一线路部24于该封装层23与该些电子元件22上,且令该线路部24电性连接该电子元件22。
于本实施例中,该RDL制程可采用一层介电材上形成一层导电材的方式进行扇出(Fan-Out)型线路结构的制作,使该线路部24包含相叠的至少一线路层241与至少一介电层240,该介电层240形成于该封装层23上,且该线路层241通过形成于该介电层240中的多个导电盲孔242电性连接该电子元件22的电极垫220。应可理解地,于其它实施例中,该线路部24可为多层线路的结构,其包含多个介电层240及多个形成于该介电层240上的线路层241。
此外,形成该介电层240的材质为聚亚酰胺(Polyimide,简称PI)、苯并环丁烯(Benezocy-clobutene,简称BCB)、聚对二唑苯(Polybenzoxazole,简称PBO)或有机聚合物(Polymer)。
又,形成该线路层241的材质为铜、金、合金、银、铝或其它合适导电材等。
另外,可形成多个如焊锡凸块的导电元件26于该线路部24上,且该些导电元件26电性连接该线路层241。进一步,为了增强整体结构强度,可于形成该些导电元件26后,涂布或模压一绝缘保护层25于该线路部24上,且该绝缘保护层25外露该些导电元件26。例如,形成该绝缘保护层25的材质可为薄膜(film)材、如液态封装胶体或移转模造胶体等的封装材。
如图2E所示,进行切单制程,沿图2D所示的切割路径S(即对应该置放区A的边缘)进行切割以获取多个个电子封装件2。
于本实施例中,为了增加散热效果或提供系统厂较佳的机构布件空间,可通过薄化制程,于图2B的制程中移除部分该封装层23,使该电子元件22的非主动面22b外露于该封装层23’,如图2E’所示的该电子元件22的非主动面22b与该封装层23’的外表面共平面。应可理解地,该调整件21亦可外露于该封装层23’的外表面,如图2E’所示的该调整件21的端部与该封装层23’的外表面共平面。
本发明的制法主要通过形成该封装层23之前,先设置CTE接近该电子元件22(或硅晶片)的该调整件21,以减少该封装层23的使用量,故当CTE较高的该封装层23的使用量越少时,该电子封装件2发生翘曲的机率也相对变小。
另外,通过该调整件21抑制该封装层23与电子元件22之间因CTE不匹配所造成的翘曲,也就是该封装层23内的应力可分散至该调整件21,以改善该封装层23的翘曲程度,且可针对不同的电子封装件2,调整该调整件21的尺寸或排列方式以最佳化翘曲数值,故相较于现有技术,本发明的制法能降低该电子封装件2或该封装层23发生翘曲的问题。
因此,当该承载件20的尺寸越大时,该电子封装件2或该封装层23的翘曲程度不会随之加大,故于制作具有扇出型线路结构的线路部24时,该导电盲孔242与该电子元件22间的电性连接能有效对接,因而能避免如导电元件26损坏所造成的良率过低及产品可靠度不佳等问题,以降低成本及提高产能。
本发明亦提供一种电子封装件2,包括:封装层23,23’、嵌埋于该封装层23,23’中的电子元件22、以及嵌埋于该封装层23,23’中并与该电子元件22分离设置的调整件21。
所述的电子元件22具有多个侧面22c,使该调整件21对应位于该电子元件22的至少二侧面22c之处。
所述的调整件21的外形为中空形、类L形或类I字形。
于一实施例中,形成该调整件21的材质接近该电子元件22,例如为硅或玻璃。
于一实施例中,所述的电子封装件2还包括一线路部24,其形成于该封装层23,23’与该电子元件22上,且该线路部24电性连接该电子元件22。例如,该线路部24包含相叠的至少一介电层240与至少一线路层241,且该线路层241电性连接该电子元件22。
综上所述,本发明的电子封装件及其制法,通过该调整件的设计,以减少该封装层的使用量,因而降低发生翘曲的机率,故能避免良率过低及产品可靠度不佳等问题,以降低成本及提高产能。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何所属领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (11)
1.一种电子封装件,其特征为,该电子封装件包括:
封装层;
电子元件,其具有多个侧面且嵌埋于该封装层中;以及
调整件,其嵌埋于该封装层中并与该电子元件分离设置,其中,该调整件对应位于该电子元件的至少二侧面之处,且该调整件的外形呈中空形、类L形或类I字形。
2.根据权利要求1所述的电子封装件,其特征为,形成该调整件的材质为硅或玻璃。
3.根据权利要求1所述的电子封装件,其特征为,该电子封装件还包括形成于该封装层与该电子元件上且电性连接该电子元件的线路部。
4.根据权利要求3所述的电子封装件,其特征为,该线路部包含相叠的至少一介电层与至少一线路层,且该线路层电性连接该电子元件。
5.一种电子封装件的制法,其特征为,该制法包括:
设置至少一电子元件与至少一调整件于一承载件上,其中,该调整件位于对应该电子元件的至少任两侧面的位置;
进行预烤;
于该预烤后静置;
形成封装层于该承载件上以包覆该调整件与该电子元件;以及
移除该承载件。
6.根据权利要求5所述的电子封装件的制法,其特征为,该调整件的外形呈中空形、类L形或类I字形。
7.根据权利要求5所述的电子封装件的制法,其特征为,形成该调整件的材质为硅或玻璃。
8.根据权利要求5所述的电子封装件的制法,其特征为,该制法还包括形成一线路部于该封装层与该电子元件上,且令该线路部电性连接该电子元件。
9.根据权利要求8所述的电子封装件的制法,其特征为,该线路部包含相叠的至少一介电层与至少一线路层,且该线路层电性连接该电子元件。
10.根据权利要求8所述的电子封装件的制法,其特征为,该制法还包括设置导电元件于该线路部上。
11.根据权利要求5所述的电子封装件的制法,其特征为,该制法还包括于移除该承载件后,进行切单制程,且该调整件与该电子元件仍保留于该封装层中。
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