CN109585471A - 半导体封装和图像传感器 - Google Patents

半导体封装和图像传感器 Download PDF

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Publication number
CN109585471A
CN109585471A CN201811107072.0A CN201811107072A CN109585471A CN 109585471 A CN109585471 A CN 109585471A CN 201811107072 A CN201811107072 A CN 201811107072A CN 109585471 A CN109585471 A CN 109585471A
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area
region
bonding layer
chip
semiconductor packages
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CN109585471B (zh
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沈钟辅
赵汊济
韩相旭
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明构思涉及一种半导体封装和图像传感器。一种半导体封装包括：封装基板；设置在封装基板上的图像传感器；以及接合层，其设置在封装基板与图像传感器之间并包括第一区域和第二区域，第二区域具有比第一区域的弹性模量低的弹性模量，并设置在第一区域的周边。

Description

半导体封装和图像传感器
技术领域
本发明构思涉及半导体封装和图像传感器。
背景技术
图像传感器是接收光并产生电信号的基于半导体的传感器，并且可以包括具有多个像素的像素阵列和用于驱动像素阵列的电路。除用于拍摄静止或运动图像的照相机之外，这样的图像传感器已广泛应用于智能电话、平板PC、膝上型计算机、电视机等。近来，已经积极地进行了用于将图像传感器有效地安装在诸如智能电话、平板PC、膝上型计算机等的设备上以及安装在照相机中的各种封装技术的研究。
发明内容
本发明构思的一方面可以提供有效地减轻施加到图像传感器的应力的半导体封装。
根据本发明构思的一方面，一种半导体封装包括封装基板、设置在封装基板上的图像传感器、以及设置在封装基板与图像传感器之间的接合层，其中接合层包括第一区域和第二区域，其中第二区域具有比第一区域的弹性模量低的弹性模量，以及其中第二区域设置在第一区域的周边。
根据本发明构思的一方面，一种半导体封装包括：封装基板；图像传感器，其包括存储区域、堆叠在存储区域上的逻辑电路区域、以及堆叠在逻辑电路区域上的像素阵列区域，其中存储区域具有通过第一芯片接合层附接到逻辑电路区域的存储芯片以及通过第二芯片接合层附接到逻辑电路区域的虚设芯片，其中第二芯片接合层具有与第一芯片接合层的弹性模量不同的弹性模量；以及接合层，其设置在封装基板与图像传感器之间，其中接合层将封装基板和图像传感器彼此附接，并具有拥有不同弹性模量的第一区域和第二区域。
根据本发明构思的一方面，一种图像传感器包括：具有多个像素的像素阵列区域；设置在像素阵列区域下方的逻辑电路区域；设置在逻辑电路区域下方的存储区域，其中存储区域具有电连接到逻辑电路区域中包括的电路元件的至少一部分的存储芯片和与存储芯片相邻设置的虚设芯片；以及芯片接合层，其具有将存储芯片和逻辑电路区域彼此附接的第一芯片接合层、以及将虚设芯片和逻辑电路区域彼此附接的第二芯片接合层，其中第二芯片接合层具有比第一芯片接合层的弹性模量低的弹性模量。
附图说明
本公开的以上及另外的方面、特征和另外的优点将由以下结合附图的详细描述被更清楚地理解，附图中：
图1是示出根据一示例实施方式的半导体封装的透视图；
图2是示出根据一示例实施方式的半导体封装的剖视图；
图3至图6是提供以示出根据示例实施方式的半导体封装的视图；
图7是示意性地示出根据一示例实施方式的图像传感器的透视图；
图8是示出根据一示例实施方式的图像传感器的剖视图；
图9是示出根据一示例实施方式的半导体封装的剖视图；
图10至图15是提供以示出根据一示例实施方式的制造半导体封装的工艺的视图；以及
图16是示出包括根据一示例实施方式的半导体封装的电子设备的框图。
具体实施方式
本发明构思的优点和特征以及实现它们的方法将由以下参照附图更详细地描述的示例性实施方式明显。然而，应注意，本发明构思不限于以下示例性实施方式，并且可以以各种形式实现。因此，提供示例性实施方式仅是为了公开本发明构思，并且让本领域技术人员了解本发明构思的分类。
在本说明书中，将理解，当一元件被称为“与”另一元件、层或区域“接触”或者“在”另一元件、层或区域“上”时，它能直接与所述另一元件、层或区域接触或在所述另一元件、层或区域上，或者也可以存在居间元件、层或区域。在附图中，为了图示的清楚，元件的厚度被夸大。
本说明书中使用的术语仅是为了描述具体实施方式的目的，并且不旨在成为本发明的限制。当在本说明书中使用时，单数形式“一”和“该”旨在还包括复数形式，除非上下文清楚地另行指示。还将理解，当在本说明书中使用时，术语“包括”和/或“包含”指明所陈述的特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或更多个另外的特征、整体、步骤、操作、元件、部件和/或其组的存在或添加。当在此使用时，术语“和/或”包括相关所列项目中的一个或更多个的任何及所有组合。
此外，虽然术语“第一”和“第二”可以用于描述本发明构思的各种实施方式中的各种构件、部件、区域、层和/或部分，但是这些构件、部件、区域、层和/或部分不限于这些术语。这些术语仅用于将一个构件、部件、区域、层或部分与另一构件、部件、区域、层或部分区分开。因此，在一实施方式中被称为第一构件、第一部件、第一区域、第一层或第一部分的构件、部件、区域、层或部分可以在另一实施方式中被称为第二构件、第二部件、第二区域、第二层或第二部分。
除非另外定义，否则这里使用的所有术语(包括技术术语和科学术语)具有与本发明构思所属领域的普通技术人员通常理解的相同的含义。还将理解，诸如通用词典中定义的术语的术语应被解释为具有与在相关领域的背景下它们的含义相一致的含义，并且将不在理想化的或过度形式化的意义上被解释，除非在此明确地如此定义。
这里说明和示出的本发明构思的方面的示例性实施方式包括它们的互补对应物。在整个说明书中，相同的附图标记或相同的附图符号表示相同的元件。
在下文中，将参照附图描述本发明构思的示例实施方式。
图1是示出根据一示例实施方式的半导体封装的透视图。
参照图1，根据一示例实施方式的半导体封装1可以包括拍摄对象的图像以生成图像数据的图像传感器。半导体封装1可以包括光学部分2、容纳光学部分2的外壳3、图像传感器或类似物、连接到图像传感器的电路板4、图像处理器5、连接器6等。半导体封装1的外覆盖件可以以与图1所示的示例实施方式不同的方式修改。
光学部分2可以包括用于收集光以拍摄对象的图像的至少一个透镜。图像传感器可以通过移动光学部分2中包括的透镜而聚焦对象的图像，并且透镜可以通过容纳在外壳3内的自动聚焦(AF)致动器而移动。
图像传感器设置在光学部分2下方，并且可以安装在连接到电路板4的封装基板的上部。图像传感器可以包括多个光电器件、将多个光电器件中的电荷转换成电信号的像素电路、利用由像素电路产生的电信号产生图像数据的逻辑电路等。在一示例实施方式中，图像传感器可以包括连接到逻辑电路并存储图像数据的存储芯片。
图像处理器5可以包括用于与例如应用处理器(AP)、闪速存储器等的其它外部器件通信的接口、图像信号处理单元等。图像处理器5可以安装在电路板4上并且可以电连接到外壳3内部的图像传感器。此外，图像处理器5通过连接器6与中央处理单元(CPU)或诸如应用处理器(AP)、闪速存储器、显示驱动器件等的外部设备发送和接收信号。
图2是示出根据一示例实施方式的半导体封装的剖视图。
参照图2，根据一示例实施方式的半导体封装10可以包括封装基板11、提供在封装基板11上的图像传感器12、允许图像传感器12和封装基板11彼此附接的接合层15。图像传感器12可以通过引线16电连接到提供在封装基板11中的电路图案，并且保持件17可以提供在图像传感器12的侧表面上。红外(IR)滤光器18和光学部分19可以设置在保持件17的上部中。
参照图2，由封装基板11、保持件17和IR滤光器18围绕的空间可以被提供，并且图像传感器12可以设置在该空间中。允许图像传感器12附接到封装基板11的上表面的接合层15可以包括由不同材料形成的第一区域13和第二区域14。
在一示例实施方式中，第一区域13和第二区域14可以具有不同的弹性模量。用于将第一区域13的弹性模量与第二区域14的弹性模量进行比较的概念可以是杨氏模量，并且可以是指示当相反的力在轴线上施加到物体时该物体沿该轴线变形的程度的参数。在一示例实施方式中，第一区域13可以具有比第二区域14的弹性模量相对高的弹性模量。
第一区域13可以部分地或完全地被第二区域14围绕。换言之，第二区域14可以设置在第一区域13的周边，从而部分地或完全地围绕或者部分地或完全地包围第一区域13的周边。因此，由于第一区域13具有比第二区域14的弹性模量相对高的弹性模量，图像传感器12和封装基板11可以被牢固地固定。此外，第二区域14具有比第一区域13的弹性模量相对低的弹性模量，因此可以减小由于在组装或使用半导体封装10的过程中发生的冲击而施加到图像传感器12的应力。
形成接合层15的面积可以小于图像传感器12的下表面的面积。表示接合层15的面积与图像传感器12的下表面的面积之比的覆盖率可以为约70％。同时，第一区域13和第二区域14可以以分配、打点(dotting)或类似方式施加到封装基板11的上表面或图像传感器12的下表面。
图3至图6是提供以示出根据示例实施方式的半导体封装的视图。图3至图6是示出提供在图像传感器的与封装基板相对的下表面上的接合层的视图。
首先，参照图3，提供在图像传感器100的下表面上的接合层110可以包括第一区域111和第二区域112。在图3所示的一示例实施方式中，第一区域111可以提供在图像传感器100的下表面的中央区中，第二区域112可以提供为完全围绕第一区域111的周边，并且第二区域112可以具有比第一区域111的面积大的面积。虽然第一区域111被描绘成圆形形状、由描绘为矩形形状的第二区域围绕，但是第一区域111和第二区域112的形状不被特别限制于此。
第一区域111和第二区域112可以由包括粘合剂的材料形成，或者可以由粘合材料形成，并且第一区域111和第二区域112可以由不同的材料形成，例如不同的粘合材料。在一示例实施方式中，形成第一区域111的材料可以具有比形成第二区域112的材料的弹性模量高的弹性模量。具有相对低的弹性模量的第二区域112提供为完全围绕第一区域111的周边，从而可以有效地减轻传输到图像传感器100的应力。
接着，参照图4，提供在图像传感器100的下表面上的接合层120可以包括第一区域121和第二区域122。在图4所示的一示例实施方式中，第一区域121可以提供在图像传感器100的下表面的中央区中。第二区域122可以包括通过第一区域121彼此分开的多个子区域，并且可以设置在第一区域121的周边上。第二区域122可以设置在与第一区域121相同的层上，并且第二区域122可以具有十字形状，但不限于此。第二区域122中包括的多个子区域可以关于第一区域121对称地布置。此外，在图4所示的一示例实施方式中，接合层120可以不形成在第二区域122中包括的多个子区域之间。
参照图5所示的一示例实施方式，在图像传感器100的下表面上，包括第一区域131、第二区域132和第三区域133的接合层130可以提供在其上。第一区域131可以提供在图像传感器100的下表面的中央区中，第二区域132可以具有在第一区域131的周边对称地形成和布置的多个子区域。在图5所示的一示例实施方式中，第二区域132中包括的多个子区域可以布置成X形。同时，第三区域133中包括的多个子区域可以设置在第二区域132中包括的多个子区域之间以及在第二区域132中包括的多个子区域的周边。
第一区域131、第二区域132和第三区域133中的至少一部分可以由具有不同弹性模量的材料形成。在一示例实施方式中，第二区域132可以由具有比第一区域131和第三区域133的弹性模量低的弹性模量的材料形成。换言之，第二区域132可以由更软的粘合材料形成，即由与第一区域131和第三区域133的材料相比更软的材料形成。
第一区域131和第三区域133可以由更硬的粘合材料形成，即由与第二区域132的材料相比更硬的材料形成。第一区域131的弹性模量和第三区域133的弹性模量可以相同或不同。在一示例实施方式中，第一区域131的弹性模量可以大于第三区域133的弹性模量。第三区域133可以形成为允许图像传感器100的下表面的一部分向外暴露。因此，接合层130对图像传感器100的下表面的覆盖率可以小于100％。
参照图6，接合层140可以包括第一区域141和第二区域142。第一区域141可以提供在图像传感器的下表面的中央区中，并且第二区域142可以完全围绕第一区域141的周边并包括从第一区域141向外辐射的多个部分。第二区域142可以具有比第一区域141的面积相对大的面积，并且可以由具有比第一区域141的弹性模量相对低的弹性模量的材料形成。
在图3至图6所示的示例实施方式中，第二区域112、122、132和142可以设置在第一区域111、121、131和141的周边。换言之，第二区域112、122、132和142可以设置为与第一区域111、121、131和141相比更靠近图像传感器100的下表面的边缘。图像传感器100使用第一区域111、121、131和141牢固地附接到封装基板，并且第二区域112、122、132和142提供在其附近以减轻在制造工艺期间或在使用期间施加到图像传感器100的应力，从而防止图像传感器100弯曲或倾斜。换言之，第二区域112、122、132和142可以用作一种类型的应力缓冲层。同时，在图3至图6所示的示例实施方式中，接合层110、120、130和140不仅可以允许图像传感器100附接到封装基板，而且还可以执行将图像传感器100的操作期间产生的热传递到封装基板的功能。
在图3至图6所示的示例实施方式中，第一区域111、121、131和141以及第二区域112、122、132和142被描绘成彼此直接接触。然而，可以在第一区域111、121、131和141与第二区域112、122、132和142之间提供空间。
如前所述，第一区域111、121、131和141可以由诸如粘合剂或粘合材料的具有比第二区域112、122、132和142的弹性模量相对高的弹性模量的材料形成。在一示例实施方式中，第一区域111、121、131和141可以由环氧树脂形成，第二区域112、122、132和142可以由环氧硅树脂形成。或者，第一区域111、121、131和141以及第二区域112、122、132和142可以由环氧树脂形成。在这种情况下，第一区域111、121、131和141可以由银(Ag)环氧树脂形成，第二区域112、122、132和142可以由热固性环氧树脂形成。
图7是示意性地示出根据一示例实施方式的图像传感器的透视图。
参照图7，根据一示例实施方式的图像传感器可以包括像素阵列区域210、提供在像素阵列区域210下方的逻辑电路区域220、提供在逻辑电路区域220下方的存储区域230等。像素阵列区域210、逻辑电路区域220和存储区域230可以一个堆叠在另一个上。在一示例实施方式中，像素阵列区域210和逻辑电路区域220可以在晶片级堆叠，并且存储区域230可以在芯片级附接到逻辑电路区域220的下部。
像素阵列区域210可以包括其中提供多个像素PX的感测区SA、以及提供在感测区SA周边的第一焊盘区PA1。多个上焊盘PAD被包括在第一焊盘区PA1中，并且多个上焊盘PAD可以通过通路等连接到逻辑电路LC以及提供在逻辑电路区域220的第二焊盘区PA2中的焊盘。
多个像素PX的每个可以包括接收光并产生电荷的光电器件、将由光电器件产生的电荷转换成电信号的像素电路等。光电器件可以包括有机光电二极管或半导体光电二极管等。在一示例实施方式中，有机光电二极管和半导体光电二极管可以在多个像素PX的每个中一个堆叠在另一个上。像素电路可以包括将由光电器件产生的电荷转换成电信号的多个晶体管。
逻辑电路区域220可以包括形成在逻辑电路LC中的多个电路元件。逻辑电路LC中包括的多个电路元件可以提供用于驱动提供在像素阵列区域210中的像素电路的电路，例如行驱动器、列驱动器、定时控制器等。逻辑电路LC中包括的多个电路元件可以通过第一焊盘区PA1和第二焊盘区PA2连接到像素电路。
提供在逻辑电路区域220下方的存储区域230可以包括存储芯片MC、虚设芯片DC、以及密封存储芯片MC和虚设芯片DC的保护层EN。存储芯片MC可以是动态随机存取存储器(DRAM)或静态随机存取存储器(SRAM)，虚设芯片DC可以不具有实际存储数据的功能。
存储芯片MC可以通过凸块电连接到逻辑电路区域220中包括的电路元件的至少一部分。在一示例实施方式中，凸块可以是微凸块。在存储芯片MC与逻辑电路区域220之间，保护微凸块并允许存储芯片MC和逻辑电路区域220彼此稳定地附接的第一芯片接合层可以被提供。
同时，虚设芯片DC可以不向逻辑电路区域220发送信号和从逻辑电路区域220接收电信号，因而可以附接到逻辑电路区域220而没有凸块。在一示例实施方式中，允许虚设芯片DC附接到逻辑电路区域220的第二芯片接合层可以由与第一芯片接合层的材料不同的材料形成。在下文中，这将参照图8更详细地描述。
图8是示出根据一示例实施方式的图像传感器的剖视图。
参照图8，根据一示例实施方式的图像传感器200可以包括像素阵列区域210、逻辑电路区域220和存储区域230。像素阵列区域210可以包括多个像素PX。多个像素PX的每个可以包括微透镜211、光电器件212、像素电路213、第一通路214等。
微透镜211可以收集从外部透射的光，并且可以将光透射到光电器件212。光电器件212可以是形成在第一半导体基板201中的半导体光电二极管，并且可以从由微透镜211收集的光中产生电荷。在一示例实施方式中，除半导体光电二极管之外，光电器件212还可以包括有机光电二极管，并且有机光电二极管可以提供在半导体光电二极管与微透镜211之间。同时，在微透镜211与第一半导体基板201之间，缓冲层以及用于增大光透射率的层可以被提供。
由光电器件212产生的电荷可以被传输到像素电路213。像素电路213可以包括多个晶体管。例如，像素电路可以具有三晶体管(3T)或四晶体管(4T)结构。当像素电路213具有4T结构时，连接到单个光电器件212的像素电路213可以包括传输晶体管、驱动晶体管、复位晶体管、选择晶体管、存储电荷的浮置扩散节点等。
提供在像素阵列区域210下方的逻辑电路区域220可以包括用于驱动像素电路213的电路，诸如行驱动器、列驱动器、定时控制器等。逻辑电路区域220可以包括形成在第二半导体基板202中的电路元件221，并且电路元件221的至少一部分可以通过第一通路214连接到上焊盘PAD。上焊盘PAD可以通过引线连接到提供在封装基板中的电路图案，并且电路元件221可以通过上焊盘PAD和第一通路214与图像处理器发送和接收信号。
存储区域230提供在逻辑电路区域220下方，并且可以包括能够存储数据的存储芯片MC、以及虚设芯片DC。存储芯片MC可以通过上存储焊盘231、下存储焊盘232和提供在其间的微凸块233连接到逻辑电路区域220的下部。上存储焊盘231可以通过第二通路222连接到形成在逻辑电路区域220中的电路元件221的至少一部分。
同时，在存储芯片MC和虚设芯片DC的每个与逻辑电路区域220之间，可以提供包括第一芯片接合层241和第二芯片接合层242的接合层240。第一芯片接合层241保护微凸块233，同时允许存储芯片MC和逻辑电路区域220进一步可靠地彼此结合。虚设芯片DC是不执行单独功能的芯片，因而可以使用第二芯片接合层242而没有凸块地与逻辑电路区域220的下部结合。
在一示例实施方式中，第一芯片接合层241和第二芯片接合层242可以由不同的材料形成。第一芯片接合层241是为了图像传感器200的操作所需的存储芯片MC的稳定连接而提供的层，因而可以由具有比第二芯片接合层242的弹性模量相对高的弹性模量的材料形成。例如，用于第一芯片接合层241的形成的材料具有几GPa的弹性模量，而用于第二芯片接合层242的形成的材料可以具有几十到几百MPa的弹性模量。
在一示例实施方式中，第二芯片接合层242使用具有相对低的弹性模量的材料形成，因此可以通过力或热有效地减轻施加到图像传感器200的应力。虚设芯片DC是不参与图像传感器200的实际操作的部件，因此不需要使用具有高弹性模量的硬材料来将虚设芯片DC与逻辑电路区域220结合。因此，第二芯片接合层242使用具有相对低的弹性模量的软材料形成，因此可以获得应力缓冲效果。
图9是示出根据一示例实施方式的半导体封装的剖视图。
根据图9所示的一示例实施方式的半导体封装300可以包括安装在封装基板301上的图像传感器310、接合层320、引线330、IR滤光器340、光学部分350等。限定其中提供图像传感器310的安装空间的保持件303可以提供在封装基板301上，并且图像传感器310可以通过接合层320附接到封装基板301的上表面。
图像传感器310可以包括像素阵列区域311、逻辑电路区域312和存储区域313。像素阵列区域311、逻辑电路区域312和存储区域313可以在厚度方向上堆叠。存储区域313可以包括能够存储由像素阵列区域311和逻辑电路区域312生成的图像数据的存储芯片MC、以及不具有数据存储功能的虚设芯片DC。存储芯片MC和虚设芯片DC可以由保护层EN密封。
上焊盘316可以提供在像素阵列区域311上，并且上焊盘316可以通过引线330连接到提供在封装基板301中的基板焊盘302。基板焊盘302可以电连接到封装基板301中的电路图案、图像传感器等。因此，像素阵列区域311和逻辑电路区域312可以通过引线330向图像处理器等发送信号和从图像处理器等接收信号。
存储芯片MC通过第一芯片接合层314附接到逻辑电路区域312，并且虚设芯片DC可以通过第二芯片接合层315附接到逻辑电路区域312。第一芯片接合层314可以具有比第二芯片接合层315的弹性模量高的弹性模量。例如，第一芯片接合层314的弹性模量可以为几GPa。
允许图像传感器310与封装基板301结合的接合层320可以包括第一区域321和第二区域322。第二区域322可以提供在第一区域321的周边，并且可以由具有比第一区域321的弹性模量低的弹性模量的材料形成。图像传感器310可以通过具有高弹性模量的第一区域321稳定地固定到封装基板301，并且可以通过具有低弹性模量的第二区域322减轻图像传感器310接收的应力。
在一示例实施方式中，接合层320中包括的第一区域321和第二区域322的弹性模量可以低于第一芯片接合层314的弹性模量。在一示例实施方式中，第一芯片接合层314应执行固定逻辑电路区域312和存储芯片MC同时保护允许逻辑电路区域312和存储芯片MC彼此电连接的微凸块的功能，因而可以具有比第二芯片接合层315和接合层320的弹性模量高的弹性模量。
图10至图15是提供以示出根据一示例实施方式的制造半导体封装的工艺的视图。
首先，参照图10，保持件403可以提供在封装基板401上。保持件403可以由诸如聚酰亚胺等的聚合绝缘材料形成。用于电信号传输的电路图案可以形成在封装基板401的上表面上或者在封装基板401的内部，并且电路图案可以连接到暴露于封装基板401的上表面的基板焊盘402。
参照图11，接合层的第一区域421可以提供在封装基板401的上表面的一部分上。第一区域421可以由具有相对高的弹性模量的环氧树脂形成，并且可以提供在封装基板401的上表面的中央。接着，参照图12，第二区域422形成为在第一区域421的周边，因此可以形成接合层420。第二区域422形成为围绕第一区域421，并且可以形成为比第一区域421的面积大。在一示例实施方式中，第二区域422可以由具有比第一区域421的弹性模量低的弹性模量的材料形成，例如硅树脂。
在图11和图12所示的一示例实施方式中，第一区域421和第二区域422被描绘成彼此直接接触。然而，可以在第一区域421与第二区域422之间提供空间。第一区域421和第二区域422可以使用诸如分配、打点等的各种方法形成在封装基板401的上表面上。
参照图13，图像传感器410可以附接到接合层420。在图13中，示意性地示出了图像传感器410，但是图像传感器410可以具有其中堆叠像素阵列区域、逻辑电路区域、存储区域等的结构。上焊盘416可以提供在图像传感器410的上表面上。同时，以与参照图11至图13所示的示例实施方式不同的方式，包括第一区域421和第二区域422的接合层420形成在图像传感器410的下表面中，并且图像传感器410可以附接到封装基板401。
接着，参照图14，在形成用于连接上焊盘416和基板焊盘402的引线430之后，IR滤光器440可以被固定到保持件403。IR滤光器440可以是用于从来自外部源的光中去除红外线从而改善图像传感器410的性能的滤光器。同时，上焊盘416和基板焊盘402通过引线430连接，因此通过封装基板401的电路图案传输的控制命令可以被传输到图像传感器410，并且由图像传感器410生成的图像数据可以通过封装基板401的电路图案传输到中央处理单元、应用处理器和/或存储器等。
参照图15，光学部分450可以附接到保持件403和IR滤光器440的上部。光学部分450可以包括多个透镜，并且用于通过移动多个透镜而聚焦在期望的对象上的AF致动器可以被单独提供。
图16是示出包括根据一示例实施方式的半导体封装的电子设备的框图。
参照图16，根据一示例实施方式的图像传感器1010可以安装在封装基板上，并且可以应用于计算机设备1000，同时具有半导体封装的形式。除图像传感器1010之外，图16所示的根据一示例实施方式的计算机设备1000可以包括输入和输出装置1020、存储器1030、处理器1040、端口1050等。此外，计算机设备1000还可以包括有线/无线通信装置、电源装置等。在图16所示的部件当中，端口1050可以是提供为允许计算机设备1000与显卡、声卡、存储卡、USB装置等通信的装置。计算机设备1000可以是覆盖智能电话、平板PC、智能可穿戴设备等以及通用台式计算机和膝上型计算机的全部的概念。
处理器1040可以执行特定操作、命令、任务等。处理器1040可以是中央处理单元(CPU)或微处理器单元，并且可以通过总线1060与连接到存储器1030、输入和输出装置1020、图像传感器1010和端口1050的其它装置通信。
存储器1030可以是存储计算机设备1000的操作所需的数据、多媒体数据等的存储介质。存储器1030可以包括诸如随机存取存储器(RAM)的易失性存储器、或诸如闪速存储器等的非易失性存储器。此外，存储器1030可以包括固态驱动器(SSD)、硬盘驱动器(HDD)和光盘驱动器(ODD)当中的至少一个作为存储装置。输入和输出装置1020可以包括提供给用户的诸如键盘、鼠标、触摸屏等的输入装置以及诸如显示器、音频输出单元等的输出装置。
图像传感器1010安装在封装基板上，并且可以通过总线1060或其它通信装置连接到处理器1040。图像传感器1010可以应用于计算机设备1000，同时具有根据参照图1至图15所示的各种示例实施方式的形式。
如上所述，根据本发明构思的示例实施方式，图像传感器与封装基板之间的接合层可以包括具有不同弹性模量的第一区域和第二区域。具有相对低的弹性模量的第二区域设置在第一区域的周边，因此可以显著地减小图像传感器由于施加到半导体封装的冲击而接收到的应力。
虽然以上已经显示和描述了示例实施方式，但是对本领域技术人员将明显的是，可以进行修改和变化而不背离如由所附权利要求限定的本公开的范围。
本申请要求享有2017年9月29日向韩国知识产权局提交的韩国专利申请第10-2017-0127986号的优先权权益，其公开通过引用全文在此合并。

Claims (20)

1.一种半导体封装，包括：
封装基板；
设置在所述封装基板上的图像传感器；以及
设置在所述封装基板与所述图像传感器之间的接合层，
其中所述接合层包括第一区域和第二区域，
其中所述第二区域具有比所述第一区域的弹性模量低的弹性模量，并且设置在所述第一区域的周边。
2.根据权利要求1所述的半导体封装，其中所述第二区域包括多个子区域。
3.根据权利要求2所述的半导体封装，其中所述多个子区域的至少一部分通过所述第一区域彼此分开。
4.根据权利要求2所述的半导体封装，其中所述多个子区域的至少一部分具有从所述第一区域延伸的形状。
5.根据权利要求2所述的半导体封装，其中所述多个子区域的至少一部分关于所述第一区域对称地布置。
6.根据权利要求1所述的半导体封装，其中所述第二区域围绕所述第一区域。
7.根据权利要求1所述的半导体封装，其中所述接合层包括在所述第二区域的周边的第三区域。
8.根据权利要求7所述的半导体封装，其中所述第三区域具有比所述第二区域的弹性模量高的弹性模量。
9.根据权利要求7所述的半导体封装，其中所述第三区域具有比所述第一区域的弹性模量低的弹性模量。
10.根据权利要求1所述的半导体封装，其中所述第一区域的面积小于所述第二区域的面积。
11.根据权利要求1所述的半导体封装，其中所述第一区域包括环氧树脂，所述第二区域包括硅树脂。
12.根据权利要求1所述的半导体封装，其中所述图像传感器包括像素阵列区域、提供在所述像素阵列区域下方的逻辑电路区域、以及提供在所述逻辑电路区域下方的存储区域，
所述存储区域具有存储数据的存储芯片以及与所述存储芯片相邻设置的虚设芯片。
13.根据权利要求12所述的半导体封装，其中所述图像传感器具有允许所述存储芯片附接到所述逻辑电路区域的下部的第一芯片接合层、以及允许所述虚设芯片附接到所述逻辑电路区域的下部的第二芯片接合层。
14.根据权利要求13所述的半导体封装，其中所述第一芯片接合层具有比所述第二芯片接合层的弹性模量高的弹性模量。
15.一种半导体封装，包括：
封装基板；
图像传感器，其包括存储区域、堆叠在所述存储区域上的逻辑电路区域、以及堆叠在所述逻辑电路区域上的像素阵列区域，其中所述存储区域具有通过第一芯片接合层附接到所述逻辑电路区域的存储芯片和通过第二芯片接合层附接到所述逻辑电路区域的虚设芯片，其中所述第二芯片接合层具有与所述第一芯片接合层的弹性模量不同的弹性模量；以及
接合层，其设置在所述封装基板与所述图像传感器之间，其中所述接合层将所述封装基板和所述图像传感器彼此附接，以及其中所述接合层包括第一区域和第二区域，其中所述第一区域具有与所述第二区域的弹性模量不同的弹性模量。
16.根据权利要求15所述的半导体封装，其中所述第一芯片接合层具有比所述第二芯片接合层的弹性模量高的弹性模量。
17.根据权利要求16所述的半导体封装，其中所述第一芯片接合层具有比所述第二芯片接合层、所述第一区域和所述第二区域的弹性模量高的弹性模量。
18.根据权利要求15所述的半导体封装，其中所述第一区域具有比所述第二区域的弹性模量高的弹性模量，所述第二区域设置在所述第一区域的周边。
19.根据权利要求15所述的半导体封装，其中所述图像传感器包括设置在所述存储芯片与所述逻辑电路区域之间的微凸块，以及
其中所述第一芯片接合层保护所述微凸块。
20.一种图像传感器，包括：
具有多个像素的像素阵列区域；
设置在所述像素阵列区域下方的逻辑电路区域；
设置在所述逻辑电路区域下方的存储区域，其中所述存储区域具有电连接到所述逻辑电路区域中包括的电路元件的至少一部分的存储芯片和与所述存储芯片相邻设置的虚设芯片；以及
芯片接合层，其包括将所述存储芯片和所述逻辑电路区域彼此附接的第一芯片接合层、以及将所述虚设芯片和所述逻辑电路区域彼此附接的第二芯片接合层，其中所述第二芯片接合层具有比所述第一芯片接合层的弹性模量低的弹性模量。
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