CN113380727A - 包括虚设晶粒的微电子器件 - Google Patents

包括虚设晶粒的微电子器件 Download PDF

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Publication number
CN113380727A
CN113380727A CN202110549348.6A CN202110549348A CN113380727A CN 113380727 A CN113380727 A CN 113380727A CN 202110549348 A CN202110549348 A CN 202110549348A CN 113380727 A CN113380727 A CN 113380727A
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China
Prior art keywords
die
active
dummy
redistribution layer
microelectronic device
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CN202110549348.6A
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施信益
施能泰
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Micron Technology Inc
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Micron Technology Inc
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Publication of CN113380727A publication Critical patent/CN113380727A/zh
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Abstract

本申请涉及半导体器件。半导体器件包括：一中介层，具有一第一面及相对于第一面的第二面；至少一有源芯片，通过多个第一凸块安装到所述第一面的一芯片接合区域内；至少一虚设芯片，安装到所述第一面的所述芯片接合区域旁的一周边区域内；一成型模料，设置在所述第一面上，并且所述成型模料覆盖所述至少一有源芯片与所述至少一虚设芯片；以及多个焊接凸块，设置在所述第二面上。

Description

包括虚设晶粒的微电子器件
本申请为发明名称为“半导体器件”的原中国发明专利申请的分案申请。原申请的中国申请号为201510508330.6；原申请的申请日为2015年8月 18日。
技术领域
本发明属于半导体封装领域，特别是涉及一种无衬底或无穿硅通孔 (throughsilicon via,TSV)的半导体器件。
背景技术
半导体封装领域中所熟知的扇出晶圆级封装(FOWLP)，是通过位于衬底上的重布线层(RDL)，例如位于具有穿硅通孔(TSV)的衬底，将原本半导体晶粒的接垫重新布线分配到一较大的区域。
重布线层是在晶圆表面上形成介电层与金属导线的叠层，将芯片原本的输入/输出(I/O)接垫重新布线分配到一个间距较宽松的布局范围。上述重布线的制作通常使用薄膜聚合物，例如苯并环丁稀(Benzocyclobutene,BCB)、聚亚酰胺(polyimind,PI)，或其他有机聚合物作为介电层材料，再以金属化工艺，例如铝或铜，形成金属导线，将芯片周围的接垫重新布线分配成阵列状连接垫。
由于工艺繁复，具有穿硅通孔的中介层衬底成本较高，因此，使用具有穿硅通孔中介层的扇出晶圆级封装也会比较昂贵，并不利于特定的应用场合。
此外，晶圆级封装工艺中，通常会在晶圆及安装在晶圆上的芯片表面覆盖一相对较厚的成型模料。此成型模料与集成电路衬底的热膨胀系数(CTE) 差异，容易导致封装翘曲变形，也使得封装整体的厚度增加。晶圆翘曲一直是本领域关注的问题。
晶圆翘曲使芯片与晶圆间的接合不易维持，使“芯片对晶圆接合”(chip towafer)的组装失败。翘曲问题在大尺寸晶圆上更是明显，特别是对于具有小间距重布线层的晶圆级半导体封装制，问题更为严重。因此，业界仍需要一个改良的晶圆级封装方法，可以解决上述现有技术的问题。
发明内容
本发明的目的在于提供一种改良的半导体器件，可减少中介层上的成型模料用量，因而改善成型后的翘曲问题。
根据本发明提供的半导体器件，包括一中介层，具有一第一面及相对于第一面的第二面；至少一有源芯片，通过多个第一凸块安装到所述第一面的一芯片接合区域内；至少一虚设芯片，安装到所述第一面的所述芯片接合区域旁的一周边区域内；一成型模料，设置在所述第一面上，并且所述成型模料覆盖所述至少一有源芯片与所述至少一虚设芯片；以及多个焊接凸块，设置在所述第二面上。
根据本发明一实施例，所述虚设芯片通过多个设置在所述周边区域内的虚设接垫上的第二凸块安装到所述第一面上。
根据本发明另一实施例，所述虚设芯片直接通过一黏着剂安装到所述第一面上。
总之，本领域的技术人员读完接下来本发明优选实施例的详细说明与附图后，均可了解本发明的目的。
附图说明
图1到图8为根据本发明一实施例使用无衬底或无穿硅通孔的中介层制作一晶圆级封装的方法的示意性剖面图，其中:
图1到图7为示意性剖面图，为本发明一实施例的晶圆级封装工艺的中间产物；
图8为俯视图，为有源芯片与虚设芯片在重布线层上的布局；
图9到图13为根据本发明另一实施例使用无衬底或无穿硅通孔的中介层制作一晶圆级封装的方法的示意性剖面图。
其中，附图标记说明如下：
10、10a 晶圆级封装
102 芯片接合区域
104 周边区域
300 载板
301 无穿硅通孔的中介层
310 钝化层
410 重布线层
412 介电层
414 金属层
430 黏着剂
500 成型模料
520 焊接凸块
415/415a/ 凸块垫
415b 虚设接垫
416/416a/416b 凸块
420a 覆晶芯片
420b 虚设芯片
具体实施方式
接下来的详细叙述须参考相关附图所示内容，用来说明可依据本发明具体实行的实施例。这些实施例提供足够的细节，可使此领域中的技术人员充分了解并具体实行本发明。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改应用在其他实施例上。
因此，接下来的详细说明并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具有同等意义者，也应属本发明涵盖的范围。
本发明实施例所参考的附图为示意图，并未按比例绘制，而相同或类似的特征通常以相同的附图标记描述。在本说明书中，“晶粒”、“半导体芯片”与“半导体晶粒”具有相同含意，可交替使用。
在本说明书中，“晶圆”与“基板”意指任何包括一暴露面，可依据本发明实施例所示在其上沉积材料，制作集成电路结构的结构物，例如重布线层。须了解的是“基板”包括半导体晶圆，但并不限于此。"基板"在工艺中也意指包括制作于其上的材料层的半导体结构物。
请参考图1到图8，为根据本发明一实施例使用无衬底或无穿硅通孔的中介层制作一晶圆级封装的方法的示意性剖面图。
如图1所示，预备一载板300。载板300例如为可卸式衬底材料，可以包括一黏着层(图未示)。载板300的上表面上包括至少一介电层或钝化层310。钝化层310可包括有机材料，例如聚亚酰胺(polyimide,PI)，或无机材料，例如氮化硅、氧化硅或类似的材料。
接着，如图2所示，在钝化层310上方形成重布线层(RDL)410。重布线层410包括至少一介电层412与至少一金属层414。介电层412可包括有机材料，例如聚亚酰胺(polyimide,PI)，或无机材料，例如氮化硅、氧化硅或类似的材料，但不限于此。金属层414可包括铝、铜、钨、钛、氮化钛或类似的材料。
根据所述实施例，金属层414可包括多个凸块垫415a和虚设接垫415b，自介电层412的上表面暴露出来。凸块垫415a设置在芯片接合区域102内，而虚设接垫415b设置在芯片接合区域102外，例如设置在芯片接合区域102 的周边区域104内。
根据所述实施例，虚设接垫415b为孤立、闲置的接垫，未与重布线层410 的金属导线电性连接。换句话说，当芯片封装体在操作模式时，不会有信号通过虚设接垫415b到其他地方。
如图3所示，在重布线层410上形成多个凸块416a与416b，例如微凸块，作为后续连接使用。凸块416a可直接形成在金属层414个别的凸块垫415a 上。凸块416b可直接形成在金属层414个别的虚设接垫415b上。在某些实施例中，形成凸块416a与416b之前，可以在重布线层410上形成一钝化层或介电层(图未示)。
如图4所示，形成凸块416a与416b之后，个别的有源芯片420a以有源面朝下面对重布线层410，通过凸块416a安装到重布线层410上，形成“芯片对晶圆接合”的堆叠结构。这些个别的有源芯片420a为具有特定功能的有源集成电路芯片，例如绘图处理器(GPU)、中央处理器(CPU)、存储器芯片等等。
根据所述实施例，虚设芯片420b通过凸块416b安装到芯片接合区域102 旁的周边区域104内。图8为有源芯片420a与虚设芯片420b在重布线层上的布局方式。虚设芯片420b可以是硅芯片、晶粒、或尺寸与有源芯片420a 相似的器件，但并不限于此。须了解的是虚设芯片420b也可包括其他材料，例如金属、玻璃或陶瓷。
上述步骤完成后，可选择性的在有源芯片420a与虚设芯片420b下方填充底胶(图未示)。随后，进行热处理，使凸块416a和416b回焊。
如图5所示，晶粒接合完成后，接着在上方覆盖一成型模料500。成型模料500覆盖住安装在重布线层上的有源芯片420a与虚设芯片420b，同时也覆盖住重布线层410的上表面。成型模料500随后会通过一固化工艺使之固化。成型模料500例如为环氧树脂与二氧化硅填充剂的混和物，但并不限于此。
接着，可选择性的研磨移除部分成型模料500的上部，使有源芯片420a 与虚设芯片420b的上表面暴露出来。
由于芯片接合区域102的周边区域104中大多都具有虚设芯片420b，因此可减少成形模料500的用量，降低甚至完全避免衬底或晶圆发生翘曲变形的情况。根据所述实施例，虚设芯片420b也可称之为翘曲控制虚设芯片。
如图6所示，形成成型模料500后，再将载板300剥离，使钝化层310 暴露出来，形成无穿硅通孔的中介层301。例如，可利用激光剥离技术或紫外光照射技术来剥离载板300，但不限于此。
剥离载板300时，可提供另一个暂时性的载板(图未示)固定于成型模料 500上方。载板300剥离完成后，接着在钝化层310形成开口，使金属层的焊接垫暴露出来，然后在个别焊接垫上形成焊接凸块或焊接球520。
随后，如图7所示，进行切割工艺，分隔出个别的晶圆级封装10。
请参考图9到图13，为根据本发明另一实施例使用无衬底或无穿硅通孔的中介层制作一晶圆级封装的方法的示意性剖面图，其中仍沿用相同的附图标记，表示相似的区域、材料层或器件。
请参考图9，如同前一个实施例，在钝化层310上方形成重布线层410。重布线层410包括至少一介电层412与至少一金属层414。介电层412可包括有机材料，例如聚亚酰胺(PI)，或无机材料，例如氮化硅、氧化硅或类似的材料，但不限于此。金属层414可包括铝、铜、钨、钛、氮化钛或类似的材料。
根据所述实施例，金属层414包括多个凸块垫415，自介电层412的上表面暴露出来。凸块垫415位于芯片接合区域102内。大致上，芯片接合区域 102以外的周边区域104不具有凸块垫。重布线层410包括多个凸块416，例如微凸块，以供后续连接使用。凸块416可直接形在金属层414个别的凸块垫415上。
如图10所示，形成凸块416后，个别的有源芯片420a以有源面朝下面对重布线层410，通过凸块416安装到重布线层410上，形成“芯片对晶圆接合”的堆叠结构。可选择性的在有源芯片420a下方填充底胶(图未示)。随后，进行热处理，使凸块416回焊。
根据所述实施例，虚设芯片420b通过黏着剂430，直接固定在芯片接合区域102外的周边区域104的重布线层410的介电层412上。
如图11所示，晶粒接合完成后，接着在上方覆盖一成型模料500。成型模料500覆盖住安装在重布线层上的有源芯片420a和虚设芯片420b，同时也覆盖住重布线层410的上表面。成型模料500随后会通过一固化工艺使之固化。后续，可选择性的研磨移除部分成型模料500的上部，使有源芯片420a 与虚设芯片420b的上表面暴露出来。
如图12所示，形成成型模料500后，再将载板300剥离，使钝化层310 暴露出来，形成无穿硅通孔的中介层301。例如，可利用激光剥离技术或紫外光照射技术来剥离载板300，但不限于此。
剥离载板300时，可以提供另一个暂时性的载板(图未示)固定于成型模料 500上方。载板300剥离完成后，接着在钝化层310形成开口，使金属层的焊接垫暴露出来，然后在个别焊接垫上形成焊接凸块或焊接球520。
随后，如图13所示，进行切割工艺，分隔出个别的晶圆级封装10a。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (20)

1.一种微电子器件，包括：
重布线层，其包括嵌入在介电材料内的金属区段，所述金属区段包括位于所述重布线层的晶粒接合区域内的有源凸块垫以及位于所述晶粒接合区域外且位于横向围绕所述晶粒接合区域的周边区域内的电孤立的、闲置的虚设接垫；
至少一有源晶粒，其安装在所述晶粒接合区域内且所述周边区域外的所述重布线层上，各个有源晶粒通过直接位于所述至少一有源晶粒的有源面以及相应有源凸块垫之间的第一凸块安装在所述有源凸块垫的一个有源凸块垫上；
虚设晶粒，其安装在所述周边区域内且所述晶粒接合区域外的所述重布线层上，所述虚设晶粒包括虚设硅晶粒，所述虚设硅晶粒具有与所述至少一有源晶粒尺寸相似的尺寸，各个虚设晶粒通过直接位于所述各个虚设晶粒以及相应电孤立的、闲置的虚设接垫之间的第二凸块安装在所述电孤立的、闲置的虚设接垫的一个电孤立的、闲置的虚设接垫上，所述虚设晶粒的至少一者沿着所述至少一有源晶粒的每个侧表面延伸，使得所述虚设晶粒围绕所述至少一有源晶粒且占据大部分周边区域；以及
成型模料，其覆盖所述至少一有源晶粒与所述虚设晶粒的侧表面，而不覆盖所述至少一有源晶粒与所述虚设晶粒的上表面。
2.根据权利要求1所述的微电子器件，其中所述虚设晶粒完全位于所述周边区域内。
3.根据权利要求1所述的微电子器件，其中所述周边区域位于邻近各个封装的外边缘处，所述晶粒接合区域通过所述周边区域与所述各个封装的所述外边缘分隔。
4.根据权利要求1所述的微电子器件，其中所述有源凸块垫通过所述重布线层的所述介电材料与所述电孤立的、闲置的虚设接垫横向分隔。
5.根据权利要求1所述的微电子器件，其中所述电孤立的、闲置的虚设接垫分别连接到所述虚设晶粒的相应不同的一个虚设晶粒。
6.根据权利要求1所述的微电子器件，其中所述重布线层的至少一些金属区段与所述至少一有源晶粒和所述虚设晶粒中的一个或多个垂直对齐。
7.根据权利要求1所述的微电子器件，其中所述金属区段和所述介电材料的外表面在所述重布线层的至少一侧彼此共面。
8.根据权利要求1所述的微电子器件，其中所述至少一有源晶粒包括通过所述重布线层的金属区段彼此互连的两个或多个有源晶粒，所述两个或多个有源晶粒中的至少一些包括存储器芯片。
9.根据权利要求1所述的微电子器件，进一步包括：
钝化材料，其位于所述重布线层的至少一侧上；
焊接凸块，其通过所述钝化材料中的开口直接接触所述重布线层的所述金属区段。
10.一种微电子器件，包括：
重布线层，其包括嵌入在介电材料内的金属区段，所述金属区段包括位于所述重布线层的晶粒接合区域内的有源凸块垫；
至少一有源晶粒，其安装在所述晶粒接合区域内的所述重布线层上，各个有源晶粒通过直接位于所述至少一有源晶粒的有源面以及相应有源凸块垫之间的凸块安装在所述有源凸块垫的一个有源凸块垫上；
虚设晶粒，其安装在所述晶粒接合区域外且横向围绕所述晶粒接合区域的周边区域内的所述重布线层上，所述虚设晶粒包括虚设硅晶粒，所述虚设硅晶粒具有与所述至少一有源晶粒尺寸相似的尺寸，且所述虚设晶粒通过黏着剂直接安装在所述重布线层的所述介电材料上且与所述金属区段电孤立，所述虚设晶粒的至少一者沿着所述至少一有源晶粒的每个侧表面延伸，使得所述虚设晶粒围绕所述至少一有源晶粒且占据大部分周边区域；以及
成型模料，其覆盖所述至少一有源晶粒与所述虚设晶粒的侧表面，而不覆盖所述至少一有源晶粒与所述虚设晶粒的上表面。
11.根据权利要求10所述的微电子器件，其中所述至少一有源晶粒完全位于所述晶粒接合区域内而不位于所述周边区域内。
12.根据权利要求10所述的微电子器件，其中所述至少一有源晶粒安装在所述有源凸块垫的一者上。
13.根据权利要求10所述的微电子器件，其中各个有源凸块垫与所述至少一有源晶粒直接垂直对齐。
14.根据权利要求10所述的微电子器件，其中所述虚设晶粒位于所述至少一有源晶粒的高度水平上，所述虚设晶粒与所述重布线层的电路电孤立。
15.根据权利要求10所述的微电子器件，其中所述黏着剂直接位于所述虚设晶粒和所述重布线层的所述介电材料之间。
16.根据权利要求10所述的微电子器件，其中所述至少一有源晶粒包括两个或多个有源晶粒，所述两个或多个有源晶粒和所述虚设晶粒中的每一者通过所述成型模料彼此横向分隔。
17.根据权利要求10所述的微电子器件，其中所述成型模料直接接触所述重布线层的所述介电材料，所述虚拟晶粒位于并经配置以减少围绕所述至少一有源晶粒的所述成型模料的体积。
18.根据权利要求10所述的微电子器件，进一步包括安装在与所述至少一有源晶粒相对的所述重布线层的一侧的焊接凸块，其中所述焊接凸块仅通过所述重布线层可操作地连接到所述至少一有源晶粒。
19.根据权利要求18所述的微电子器件，其中所述重分布层的所述金属区段直接位于所述至少一有源晶粒和所述焊接凸块之间。
20.根据权利要求18所述的微电子器件，其中所述焊接凸块中的至少一些与所述至少一有源晶粒和所述虚设晶粒中的一个或多个垂直对齐。
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US10446509B2 (en) 2019-10-15
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US20210175188A1 (en) 2021-06-10
US10043769B2 (en) 2018-08-07
US20190371749A1 (en) 2019-12-05
US20160358865A1 (en) 2016-12-08
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US10937749B2 (en) 2021-03-02
TW201643971A (zh) 2016-12-16

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