TWI739025B - 混合接合結構及其製造方法 - Google Patents

混合接合結構及其製造方法 Download PDF

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TWI739025B
TWI739025B TW107128598A TW107128598A TWI739025B TW I739025 B TWI739025 B TW I739025B TW 107128598 A TW107128598 A TW 107128598A TW 107128598 A TW107128598 A TW 107128598A TW I739025 B TWI739025 B TW I739025B
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Taiwan
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conductor
integrated circuit
dielectric layer
conductors
interconnection structure
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TW107128598A
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TW201926483A (zh
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蔡伯宗
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供包括第一積體電路組件與第二積體電路組件的混合接合結構。第一積體電路組件包括第一介電層、第一導體與隔離結構。第一導體與隔離結構嵌入於第一介電層中。隔離結構與第一導體電性絕緣，且隔離結構圍繞第一導體。第二積體電路組件包括第二介電層與第二導體。第二導體嵌入於第二介電層中。第一介電層接合至第二介電層，且第一導體接合至第二導體。

Description

混合接合結構及其製造方法
本揭露是有關於一種混合接合結構及其製造方法。
製造三維積體電路(three-dimensional integrated circuit，3D-IC)組件的方法包括藉由晶圓級混合接合(wafer level hybrid bonding)技術以進行晶圓對晶圓的接合(wafer-to-wafer bonding)。三維積體電路例如是背側照明式互補金氧半導體影像感測器(back-side illuminated complementary metal-oxide semiconductor image sensor，BSI-CIS)。在製造BSI-CIS時，提供包括陣列排列的背照明式積體電路的感測器晶圓以及包括陣列排列的邏輯電路晶片的邏輯電路晶圓。藉由晶圓級混合接合技術將感測器晶圓與邏輯電路晶圓對接，以使邏輯電路晶圓堆疊於感測器晶圓上。隨後，封裝經混合接合的感測器晶圓與邏輯電路晶圓，且進行單體化以形成BSI-CIS元件。在感測器晶圓與邏輯電路晶圓的混合接合製程期間，在兩晶圓的接合介面處可能產生銅突出(copper extrusion)及/或銅遷移(copper migration)。如此一來， 混合接合的晶圓的可靠度因上述的銅突出及/或銅遷移而降低。
根據本揭露的一些實施例，提供第一積體電路組件，其中所述第一積體電路組件包括其中具有多個第一半導體元件的第一半導體基底、設置於所述第一半導體基底上的第一內連線結構、覆蓋所述第一內連線結構的第一介電層以及至少一第一導體群組，所述至少一第一導體群組包括藉由所述第一內連線結構而彼此電性連接的多個第一導體；提供第二積體電路組件，其中所述第二積體電路組件包括其中具有多個第二半導體元件的第二半導體基底、設置於所述第二半導體基底上的第二內連線結構、覆蓋所述第二內連線結構的第二介電層以及至少一第二導體群組，所述至少一第二導體群組包括藉由所述第二內連線結構而彼此電性連接的多個第二導體；以及進行混合接合製程以接合所述第一積體電路組件與所述第二積體電路組件，以使所述第一介電層接合至所述第二介電層，且所述多個第一導體接合至所述多個第二導體。
根據本揭露的一些實施例，提供混合接合結構的製造方法，包括下列步驟：提供第一積體電路組件，其中所述第一積體電路組件包括第一半導體基底、第一內連線結構、第一介電層以及多個第一導體群組，所述第一半導體基底包括位於其中的多個第一半導體元件，所述第一內連線結構設置於所述第一半導體基 底上並電性連接至所述第一半導體元件，所述第一介電層覆蓋所述第一內連線結構，所述多個第一導體群組嵌入於所述第一介電層中並經由所述第一內連線結構而電性連接至所述第一半導體元件，且所述多個第一導體群組中的至少一第一導體群組包括彼此電性連接的多個第一導體；提供第二積體電路組件，其中所述第二積體電路組件包括第二半導體基底、第二內連線結構、第二介電層以及多個第二導體群組，所述第二半導體基底包括位於其中的多個第二半導體元件，所述第二內連線結構設置於所述第二半導體基底上並電性連接至所述第二半導體元件，所述第二介電層覆蓋所述第二內連線結構，所述多個第二導體群組嵌入於所述第二介電層中並經由所述第二內連線結構而電性連接至所述第二半導體元件，且所述多個第二導體群組中的至少一第二導體群組包括彼此電性連接的多個第二導體；進行混合接合製程以接合所述第一積體電路組件與所述第二積體電路組件，以使所述第一介電層接合至所述第二介電層，且所述至少一第一導體群組電性連接至所述至少一第二導體群組，其中所述至少一第一導體群組、所述至少一第二導體群組、所述第一內連線結構以及所述第二內連線結構提供分流路徑。
根據本揭露的一些實施例，提供包括第一積體電路晶片與第二積體電路晶片的混合接合結構。第一積體電路晶片包括其中具有多個第一半導體元件的第一半導體基底、設置於所述第一半導體基底上的第一內連線結構、覆蓋所述第一內連線結構的第 一介電層以及至少一第一導體群組，所述至少一第一導體群組包括藉由所述第一內連線結構而彼此電性連接的多個第一導體。第二積體電路晶片包括其中具有多個第二半導體元件的第二半導體基底、設置於所述第二半導體基底上的第二內連線結構、覆蓋所述第二內連線結構的第二介電層以及至少一第二導體群組，所述至少一第二導體群組包括藉由所述第二內連線結構而彼此電性連接的多個第二導體。
100:第一積體電路組件
102:影像感測晶片
110:第一半導體基底
112:第一半導體元件
120:第一內連線結構
122、222:層間介電層
124、224:內連線金屬層
128A、128B:隔離部分
130:第一介電層
140:第一導體群組
142:第一導體
200:第二積體電路組件
202:邏輯積體電路晶片
210:第二半導體基底
212:第二半導體元件
220:第二內連線結構
230:第二介電層
240:第二導體群組
242:第二導體
250:重佈線層
260:保護層
270:導電端子
300:接著層
400:蓋板
500:間隔件
CF:濾光層
HB1、HB2:混合接合結構
ML:微透鏡陣列
SL:切割線
SP1、SP2:分流路徑
ST1:第一分流走線
ST2:第二分流走線
TH:穿孔
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖7根據本揭露的一些實施例繪示用以製造BSI-CIS元件的製程流程。
圖8與圖9是根據本揭露的一些實施例繪示的晶圓的混合接合製程的剖視圖。
圖10是根據本揭露的一些實施例的混合接合結構的剖視圖。
圖11與圖12是根據本揭露的一些替代實施例繪示的晶圓的混合接合製程的剖視圖。
圖13至圖18是根據本揭露的各種實施例繪示的混合接合結構的剖視圖。
圖19至圖28是根據本揭露的各種實施例分別繪示的第一積體電路組件及/或第二積體電路組件的一導體群組的上視圖。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及配置的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各個實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於…之下(beneath)」、「位於...下面(below)」、「下部的(lower)」、「位於...上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示一個部件或特徵與另一(其他)部件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括元件在使用或操作中的不同定向。裝置可具有其他定向(旋轉90度或處於其他定向)，且本文中所用的空間相對性描述語可同樣相應地進行解釋。
圖1至圖7根據本揭露的一些實施例繪示用以製造 BSI-CIS元件的製程流程。
請參照圖1，提供第一積體電路組件100與第二積體電路組件200。第一積體電路組件100可包括其中形成有多個第一半導體元件的第一半導體基底110、設置於第一半導體基底110上的第一內連線結構120、覆蓋第一內連線結構120的第一介電層130以及至少一第一導體群組140。至少一第一導體群組140可包括藉由第一內連線結構120相互電性連接的多個第一導體142。至少一第一導體群組140嵌入於第一介電層130中。第二積體電路組件200可包括其中形成有多個第二半導體元件的第二半導體基底210、設置於第二半導體基底210上的第二內連線結構220、覆蓋第二內連線結構220的第二介電層230以及至少一第二導體群組240。至少一第二導體群組40可包括藉由第二內連線結構220相互電性連接的多個第二導體242。至少一第二導體群組240嵌入於第二介電層230中。
如圖1所示，在一些實施例中，第一積體電路組件100可為包括陣列排列的多個影像感測晶片102的第一半導體晶圓(亦即感測器晶圓)，且第二積體電路組件200可為包括陣列排列的多個邏輯積體電路晶片202的第二半導體晶圓(亦即邏輯電路晶圓)。換言之，上述的第一半導體基底110、第一內連線結構120、第一介電層130以及至少一第一導體群組140可形成第一半導體晶圓內的多個影像感測晶片102，且上述的第二半導體基底210、第二內連線結構220、第二介電層230以及至少一第二導體群組 240可形成第二半導體晶圓內的多個邏輯積體電路晶片202。
在一些實施例中，第一導體142與第二導體242的材料可為銅或其他適合的金屬材料，而第一介電層130與第二介電層230的材料可為氧化矽(SiOx，其中x大於零)、氮化矽(SiNx，其中x大於零)、氮氧化矽(SiOxNy，其中x大於零，且y大於零)或其他適合的介電材料。可藉由沈積製程形成第一導體142，且接著進行化學機械研磨(chemical mechanical polishing，CMP)。相似地，可藉由另一沈積製程形成第二導體242，且接著進行化學機械研磨。第一導體142與第二導體242有助於調整導體密度，以減少腐蝕(corrosion)及/或碟形凹陷(dishing)的問題。
在一些實施例中，對第一積體電路組件100與第二積體電路組件200的接合表面進行表面處理(surface preparation)，以協助晶圓對晶圓混合接合(wafer-to-wafer hybrid bonding)。舉例而言，表面處理可包括表面清潔與活化(activation)。可在第一積體電路組件100與第二積體電路組件200的接合表面上進行表面清潔，以移除第一導體142、第一介電層130、第二導體242以及第二介電層230的頂面上的微粒(particle)。舉例而言，可藉由濕式清潔來清潔第一積體電路組件100與第二積體電路組件200的接合表面。除了移除微粒之外，也可移除形成於第一導體142與第二導體242的頂面上的原生氧化層(native oxide)。舉例而言，可藉由使用濕式清潔製程中的化學品移除形成於第一導體142與第二導體242的頂面上的原生氧化層。
在清潔第一積體電路組件100與第二積體電路組件200的接合表面之後，可對第一介電層130與第二介電層230的頂面進行活化，以用於發展出高接合強度。在一些實施例中，可進行電漿活化，以對第一介電層130與第二介電層230的頂面進行處理。
請參照圖1與圖2，第一積體電路組件100與第二積體電路組件200相互對齊，且可達到次微米級的對位精度(sub-micron alignment precision)。一旦第一積體電路組件100與第二積體電路組件200精確地相互對齊，將第一積體電路組件100放置且接觸於第二積體電路組件200上。第一介電層130的經活化的頂面接觸第二介電層230的經活化的頂面時，第一積體電路組件100的第一介電層130與第二積體電路組件200的第二介電層230被預接合(pre-bond)。換言之，經由第一介電層130與第二介電層230預接合第一積體電路組件100與第二積體電路組件200。在第一介電層130與第二介電層230預接合之後，第一導體142接觸第二導體242。
在將第一積體電路組件100預接合至第二積體電路組件200上之後，進行第一積體電路組件100與第二積體電路組件200的混合接合。第一積體電路組件100與第二積體電路組件200的混合接合可包括用於介電層接合(dielectric bonding)的處理以及用於導體接合(conductor bonding)的熱退火(thermal annealing)。在一些實施例中，進行用於介電層接合的處理以增強第一介電層 130與第二介電層230之間的接合。舉例而言，可在約攝氏100度至約攝氏150度的溫度範圍進行用於介電層接合的處理。在進行用於介電層接合的處理之後，進行用於導體接合的熱退火以協助第一導體142與第二導體242之間的接合。舉例而言，可在約攝氏300度至約攝氏400度的溫度範圍進行用於導體接合的熱退火。用於導體接合的熱退火的製程溫度高於用於介電層接合的處理的製程溫度。由於在較高的溫度下進行用於導體接合的熱退火，故金屬的擴散與晶粒成長(grain growth)可能會發生於第一導體142與第二導體242之間的接合接面。另一方面，在進行用於導體接合的熱退火時，第一導體142與第二導體242可能承受由導體(第一導體142與第二導體242)與介電層(第一介電層130與第二介電層230)之間的熱膨脹係數差異造成的壓力。在進行用於導體接合的熱退火之後，第一介電層130接合至第二介電層230，且第一導體140接合至第二導體240。在一些實施例中，第一導體140可為導電通孔(例如是銅通孔)、導電接墊(例如是銅接墊)或其組合，而第二導體240可為導電通孔(例如是銅通孔)、導電接墊(例如是銅接墊)或其組合。舉例而言，第一導體140與第二導體240之間的導體接合可為通孔對通孔接合(via-to-via bonding)、接墊對接電接合(pad-to-pad bonding)或通孔對接墊接合(via-to-pad bonding)。
在進行第一積體電路組件100與第二積體電路組件200的混合接合之後，第一內連線結構120與第二內連線結構220經 由第一導體142與第二導體242而彼此電性連接。
如圖2所示，在混合接合第一積體電路組件100與第二積體電路組件200之後，完成包括彼此堆疊且混合接合的晶圓的混合接合結構HB1。在一些實施例中，若有需要，可將混合接合結構HB1單體化為經單體化的多個混合接合結構HB2。每一經單體化的混合接合結構HB2包括彼此堆疊且混合接合的晶片。換言之，每一經單體化的混合接合結構HB2可包括邏輯積體電路晶片與影像感測晶片，其中影像感測晶片堆疊且混合接合於邏輯積體電路晶片上。在以上所述的實施例中，混合接合結構HB1包括混合接合晶圓，且混合接合結構HB2包括混合接合晶片。然而，本揭露並不以此為限。在一些替代實施例中，混合接合結構(未繪示)可包括晶圓以及堆疊且混合接合於晶圓上的至少一晶片。
請參照圖3與圖4，在第一半導體基底110的背面上形成接著層(adhesive)300。舉例而言，接著層300經形成以覆蓋影像感測晶片102的邊緣區域，從而環繞影像感測晶片102的感測區域。提供蓋板400。蓋板400具有設置於蓋板400的底面上的間隔件500。可應用蓋板400以覆蓋混合接合結構HB1，且間隔件500的位置對應於接著層300的分布位置。藉由形成於混合接合結構HB1上的接著層300，間隔件500附接於混合接合結構HB1，且在蓋板400與混合接合結構HB1之間形成間隙。由於蓋板400藉由間隔件500與間隙而與混合接合結構HB1隔開，形成於混合接合結構HB1上的組件不與蓋板400接觸，且可被良好地保護。 舉例而言，接著層300的材料可為具有適當的絕緣特性的有機材料。蓋板400可為具有光學塗層(例如是抗反射塗層)或不具有光學塗層的蓋玻璃(cover glass)，且間隔件500可為環氧樹脂或其他適合的材料。
在一些實施例中，在蓋板400與間隔件500附接至混合接合結構HB1之後，可在第二半導體基底210的背面上進行研磨製程，以進一步降低混合接合結構HB1的厚度。
請參照圖5，在蓋板400與間隔件500經由接著層300附接於混合接合結構HB1之後，在第二半導體基底210中形成多個穿孔TH。舉例而言，可藉由矽穿孔(through silicon via，TSV)製程形成多個穿孔TH，直至第二積體電路組件200的第二內連線結構220暴露出來為止。隨後，在第二半導體基底210的背面(亦即底面)上形成重佈線層250。重佈線層250經由穿孔TH而電性連接至第二內連線結構220。在形成重佈線層250之前，可在第二半導體基底210的背面以及穿孔TH的側壁上形成絕緣層(未繪示)，從而使重佈線層250與第二半導體基底210電性絕緣。如圖5所示，重佈線層250將第一內連線結構120與第二內連線結構220重分佈至第二半導體基底210的背面。在一些實施例中，儘管未繪示於圖式中，內連線結構220可包括著陸接墊(landing pad)。著陸接墊可被穿孔TH暴露，且重佈線層250可經由穿孔TH而電性連接至著陸接墊。
請參照圖6，在第二半導體基底210的背面上形成保護層 260，以部分地覆蓋重佈線層250。保護層260可包括多個開口，以部分地暴露出重佈線層250(例如是暴露出重佈線層250的焊球接墊(ball pad))。在形成保護層260之後，在重佈線層250的被保護層260的開口暴露的部分上形成陣列排列的多個導電端子270(例如是導電焊球)。導電端子270可為藉由植球(ball placement)與回流(reflow)製程形成的焊球。
請參照圖6與圖7，在形成導電端子270之後，沿著切割線SL進行切割製程(dicing process)以單體化圖6所得的結構，以形成多個BSI-CIS元件。如圖7所示，經單體化的BSI-CIS元件可為球柵陣列(ball grid array，BGA)元件。
混合接合結構HB1可影響BSI-CIS元件的可靠度。由於突出(例如是銅突出)及/或遷移(例如是電遷移、熱遷移及/或應力遷移)可能發生於混合接合的介面，第一積體電路組件100與第二積體電路組件200之間的電性連接可能因此失效。需要第一內連線結構120與第二內連線結構220的新穎設計以解決突出與遷移的問題。接下來，將參照圖8至圖18而描述第一內連線結構120與第二內連線結構220的細節。
圖8與圖9是根據本揭露的一些實施例繪示的晶圓的混合接合製程的剖視圖。
請參照圖8與圖9，在一些實施例中，第一積體電路組件100可包括形成於第一半導體基底100上或第一半導體基底100中的多個第一半導體元件112(例如是光二極體(photo diode)、 電晶體、電容等)以及形成於第一半導體基底110的背面(例如是頂面)的微透鏡陣列(micro-lens array)ML。形成於第一半導體基底110中的第一半導體元件112可陣列排列，且形成於第一半導體基底110的背面上的微透鏡陣列ML可覆蓋第一半導體元件112。在一些替代實施例中，第一積體電路組件100更可包括形成於微透鏡陣列ML與第一半導體元件112之間的多個濾光層(color filter)CF。換言之，濾光層CF形成於第一半導體基底110的背面上，而微透鏡陣列ML形成於濾光層CF上。基於實際的設計需求，可形成其他光學組件(例如是黑色矩陣(black matrix))，以改善第一積體電路組件100中的第一半導體元件112的光學特性。
此外，在一些實施例中，第二積體電路組件200可包括形成於第二半導體基底210中或第二半導體基底210上的多個第二半導體元件212(例如是電晶體、電容等)。在一些實施例中，第二半導體元件212與第一內連線結構120可構成邏輯電路系統(logic circuitry)。
如圖8與圖9所示，儘管示出第一導體142的兩個群組以及第二導體242的兩個群組，本揭露並不以形成於第一積體電路組件100上的第一導體142的群組數量與形成於第二積體電路組件200上的第二導體242的群組數量為限。再者，本揭露並不以各個導體群組(第一導體群組140或第二導體群組240)包括的導體(第一導體142或第二導體242)的數量為限。在此實施例中， 舉例而言，一個第一導體群組140包括兩個第一導體142，且一個第二導體群組240包括兩個第二導體242。
第一導體群組140可經由第一內連線結構120中的第一分流走線ST1電性連接至第一半導體元件112。換言之，至少一第一導體群組140可經由第一內連線結構120中的一個對應的第一分流走線ST1而電性連接至第一半導體元件112中的一者。第一分流走線ST1的數量可等同於第一導電群組140的數量。在一些實施例中，第一內連線結構120可包括層間介電層(inter-dielectric layer)122以及內連線金屬層124。內連線金屬層124電性連接於第一導體群組140與第一半導體元件112之間。第一內連線結構120中的第一分流走線ST1可由內連線金屬層124的一些部分形成。相似地，第二導體群組240可經由第二內連線結構220中的第二分流走線ST2而電性連接至第二半導體元件212。換言之，至少一第二導體群組240可經由第二內連線結構220中的一個對應的第二分流走線ST2而電性連接至第二半導體元件212中的一者。第二分流走線ST2的數量可等同於第二導體群組240的數量。在一些實施例中，第二內連線結構220可包括層間介電層222以及內連線金屬層224。內連線金屬層224電性連接於第二導體群組240與第二半導體元件212之間。第二內連線結構220中的第二分流走線ST2可由內連線金屬層224的一些部分形成。
第一導體群組140中的一者所包括的第一導體142直接接觸且連接於內連線金屬層124的的一個最頂層的金屬圖案(亦 即最底層的金屬層)。相似地，第二導體群組240中的一者所包括的第二導體242直接接觸且連接於內連線金屬層224的一個最頂層金屬圖案(亦即最上層金屬層)。換言之，第一導體142與第二導體242位於內連線金屬層124的最頂層金屬圖案與內連線金屬層224的最頂層金屬圖案之間。
如圖8所示，在混合接合第一積體電路組件100與第二積體電路組件200之前，清潔第一積體電路組件100與第二積體電路組件200，且將第一積體電路組件100與第二積體電路組件200相互對齊，以用於預接合。換言之，在第一積體電路組件100上的第一導體群組140以及在第二積體電路組件200上的第二導體群組240在進行混合接合之前已相互對齊。
如圖9所示，在混合接合第一積體電路組件100與第二積體電路組件200之後，第一分流走線ST1、第二分流走線ST2、第一導體142(亦即第一導體群組140)以及第二導體242(亦即第二導體群組240)在第一積體電路組件100與第二積體電路組件200中提供多條分流路徑SP1。第一半導體元件112可經由分流路徑SP1而電性連接至第二半導體元件212。在此實施例中，每一分流路徑SP1包括用於在第一半導體元件112與第二半導體元件212之間傳輸電流的兩連接路徑。然而，本揭露並不以每一分流路徑SP1中的連接路徑的數量為限。在一些替代實施例中，不同分流路徑SP1中的連接路徑的數量可彼此相同，或彼此相異。
第一分流走線ST1與第二分流走線ST2可分散(spread) 在第一半導體元件112與第二半導體元件212之間流動的電流，以降低第一分流走線ST1與第二分流走線ST2的電流密度。第一分流走線ST1與第二分流走線ST2中電流密度的下降可減少發生於第一積體電路組件100與第二積體電路組件200之間的混合接合介面的電遷移(例如是銅遷移)。第一分流走線ST1與第二分流走線ST2以及混合接合導體(第一導體142/第二導體242)可提供低的電阻。再者，第一分流走線ST1與第二分流走線ST2可分散在混合接合期間第一導體142與第二導體242所承受的應力。分散第一導體142與第二導體242所承受的應力可減少發生於第一積體電路組件100與第二積體電路組件200之間的混合接合介面的應力遷移。如此一來，基於第一分流走線ST1與第二分流走線ST2，可提高混合接合的良率(yield)。
在上述的用於介電層接合的處理期間，第一內連線結構120與第二內連線結構220的設計可減少由熱遷移導致的斷路及/或短路的問題。在上述用於導體接合的熱退火期間，第一內連線結構120與第二內連線結構220的設計不只是可減少由熱遷移導致的斷路及/或短路的問題，更可減少熱膨脹係數差異導致的突出問題。在上述的用於減低混合接合結構(如圖4所示)的厚度的研磨製程期間，第一內連線結構120與第二內連線結構220的設計可減少應力所導致的突出問題與應力遷移。在BSI-CIS元件的操作期間，第一內連線結構120與第二內連線結構220的設計可減少電遷移造成的斷路/短路問題。綜上所述，第一內連線結構120 與第二內連線結構220的設計可減少上述的突出與遷移。
圖10是根據本揭露的一些實施例的混合接合結構的剖視圖。
請參照圖9與圖10，圖10所示的混合接合結構相似於圖9所示的混合接合結構，惟每一第一導體群組140包括3個第一導體142，且每一第二導體群組240包括3個第二導體242。此外，在此實施例中，每一分流路徑SP2例如是包括用於在第一半導體元件112與第二半導體元件212之間傳輸電流的3個連接路徑。然而，本揭露並不以每一分流路徑SP2中的連接路徑的數量為限。在一些替代實施例中，不同分流路徑SP2中的連接路徑的數量可彼此相同，或彼此相異。
圖11與圖12是根據本揭露的一些替代實施例繪示的晶圓的混合接合製程的剖視圖。
請參照圖8、圖9、圖11與圖12，圖11及圖12所繪示的第一內連線結構120與第二內連線結構220相似於圖8及圖9所示的第一內連線結構120與第二內連線結構220，惟第一導體群組140的一者所包括的第一導體142接觸於內連線金屬層124的多個頂層金屬圖案(亦即最下層的金屬層)，且第一導體群組140的一者所包括的第一導體142藉由位於頂層金屬圖案上方的一金屬圖案而彼此電性連接。相似地，第二導體群組240的一者所包括的第二導體242接觸於內連線金屬層224的多個頂層金屬圖案(亦即最上層的金屬層)，且第二導體群組240的一者所包括的第 二導體242藉由位於頂層金屬圖案上方的一金屬圖案而彼此電性連接。
第一導體群組140可經由第一內連線結構120中的第一分流走線ST1而電性連接至第一半導體元件112。換言之，至少一第一導體群組140可經由第一內連線結構120中的一對應的第一分流走線ST1而電性連接至第一半導體元件112的一者。第一分流走線ST1的數量可等同於第一導體群組140的數量。在一些實施例中，第一內連線結構120可包括層間介電層122與內連線金屬層124。內連線金屬層124電性連接於第一導體群組140與第一半導體元件112之間。第一內連線結構120中的第一分流走線ST1可由內連線金屬層124的一些部分形成。相似地，第二導體群組240可經由第二內連線結構220中的第二分流走線ST2而電性連接至第二半導體元件212。換言之，至少一第二導體群組240可經由第二內連線結構220中的一對應的第二分流走線ST2而電性連接至第二半導體元件212的一者。第二分流走線ST2的數量可等同於第二導體群組240的數量。在一些實施例中，第二內連線結構220可包括層間介電層222與內連線金屬層224。內連線金屬層224電性連接於第二導體群組240與第二半導體元件212之間。第二內連線結構220中的第二分流走線ST2可由內連線金屬層224的一些部分形成。換言之，除了第一導體142與第二導體242位於內連線金屬層124的頂層金屬圖案與內連線金屬層224的頂層金屬圖案之間之外，內連線金屬層124與內連線金屬層224 的一些部分夾設於內連線金屬層124的頂層金屬圖案與內連線金屬層224的頂層金屬圖案之間。
圖13至圖18是根據本揭露的各種實施例繪示的混合接合結構的剖視圖。
請參照圖13，圖13中的第一內連線結構120與第二內連線結構220相似於圖11與圖12中的第一內連線結構120與第二內連線結構220，惟第一內連線結構120更包括多個隔離結構。每一隔離結構包括隔離部分128A與隔離部分128B。隔離結構的隔離部分128A與第一導體142電性絕緣，且隔離部分128A的一者環繞第一導體142。此外，隔離結構的多個隔離部分128B與第二導體242電性絕緣，且隔離部分128B的一者環繞第二導體242。隔離部分128A嵌入於第一介電層130中，且隔離部分128B嵌入於第二介電層230中。隔離部分128A為電性浮置(electrically floated)並彼此分離，且隔離部分128B為電性浮置並彼此分離。如圖13所示，每一隔離部分128A分別混合接合於隔離結構128B的一者。在一些實施例中，可藉由相同的製程與相同的材料形成隔離部分128A與第一導體142，且可藉由相同的製程與相同的材料形成隔離部分128B與第二導體242。舉例而言，隔離部分128A、第一導體142、隔離部分128B與第二導體242由相同的材料構成，所述材料例如是銅或其他適合的金屬材料。
可藉由沈積製程與隨後的化學機械研磨形成第一導體142與隔離部分128A。相似地，可藉由另一沈積製程與隨後的化 學機械研磨形成第二導體242與隔離部分128B。第一導體142、隔離部分128A、第二導體242與隔離部分128B有助於調整導體密度，以減少腐蝕及/或碟形凹陷的問題。此外，電性浮置的隔離部分128A與隔離部分128B可抑制第一導體142與第二導體242的遷移問題所導致的斷路/短路問題。
請參照圖14，圖14所示的第一內連線結構120與第二內連線結構220相似於圖13所示的第一內連線結構120與第二內連線結構220，惟省略第一內連線結構120中的隔離部分128A(如圖13所示)。在一些實施例中，可藉由相同的製程與相同的材料形成隔離部分128B與第二導體242。舉例而言，隔離部分128B、第一導體142與第二導體242可由相同的材料構成，所述材料例如是銅或其他適合的金屬材料。
請參照圖15，圖15所示的第一內連線結構120與第二內連線結構220相似於圖13所示的第一內連線結構120與第二內連線結構220，惟省略第二內連線結構220中的隔離部分128B(如圖13所示)。在一些實施例中，可藉由相同的製程與相同的材料形成隔離部分128A與第一導體142。舉例而言，隔離部分128A、第一導體142與第二導體242可由相同的材料構成，所述材料例如是銅或其他適合的金屬材料。
請參照圖16至圖18，圖16、圖17與圖18所示的第一內連線結構120與第二內連線結構220相似於圖13、圖14與圖15所示的第一內連線結構120與第二內連線結構220，惟第一內 連線結構120與第二內連線結構220中不具有第一分流走線ST1與第二分流走線ST2。換言之，分流走線的設計不需要與隔離結構結合。
圖19至圖28是根據本揭露的各種實施例分別繪示的第一積體電路組件及/或第二積體電路組件的一導體群組的上視圖。
請參照圖19至圖22，在一導體群組(第一導體群組140/第二導體群組240)中，可包括多個(例如是2個、3個或4個)導體(第一導體142/第二導體242)。每一導體(第一導體142/第二導體242)被一隔離部分128A及/或隔離部分128B環繞。在此實施例中，隔離部分128A或隔離部分128B可為矩形環。屬於一導體群組(第一導體群組140/第二導體群組240)的導體(第一導體142/第二導體242)可沿著列方向或行方向排列，或陣列排列。
如圖23與圖24所示，在一些替代實施例中，藉由一內連線金屬層(內連線金屬層124/內連線金屬層224)而彼此電性連接的導體(第一導體142/第二導體242)可具有例如是圓形的形狀，且隔離部分128A或隔離部分128B可例如是圓環。在一些替代實施例中，如圖25與圖26所示，藉由一內連線金屬層(內連線金屬層124/內連線金屬層224)而彼此電性連接的導體(第一導體142/第二導體242)可具有例如是矩形的形狀，且隔離部分128A或隔離部分128B可例如是包括多個彼此分離的隔離條(isolation stripe)，其中多個隔離條例如是經配置以環繞導體(第一導體142/第二導體242)。在一些其他實施例中，如圖27與圖28所示，藉 由一內連線金屬層(內連線金屬層124/內連線金屬層224)而彼此電性連接的導體(第一導體142/第二導體242)可例如是具有矩形的形狀，且隔離部分128A或隔離部分128B可具有六邊形的形狀。
根據本揭露的一些實施例，提供第一積體電路組件，其中所述第一積體電路組件包括其中具有多個第一半導體元件的第一半導體基底、設置於所述第一半導體基底上的第一內連線結構、覆蓋所述第一內連線結構的第一介電層以及至少一第一導體群組，所述至少一第一導體群組包括藉由所述第一內連線結構而彼此電性連接的多個第一導體；提供第二積體電路組件，其中所述第二積體電路組件包括其中具有多個第二半導體元件的第二半導體基底、設置於所述第二半導體基底上的第二內連線結構、覆蓋所述第二內連線結構的第二介電層以及至少一第二導體群組，所述至少一第二導體群組包括藉由所述第二內連線結構而彼此電性連接的多個第二導體；以及進行混合接合製程以接合所述第一積體電路組件與所述第二積體電路組件，以使所述第一介電層接合至所述第二介電層，且所述多個第一導體接合至所述多個第二導體。
在一些實施例中，所述混合接合製程包括：進行用於所述第一介電層與所述第二介電層之間的介電層接合的處理；以及進行用於所述多個第一導體與所述多個第二導體之間的導體接合的熱退火。在一些實施例中，用於導體接合的所述熱退火的製程溫度高於用於介電層接合的所述處理的製程溫度。在一些實施例 中，在約攝氏100度至約攝氏150度的溫度範圍進行用於介電層接合所述第一介電層與所述第二介電層的所述處理。在一些實施例中，在約攝氏300度至約攝氏400度的溫度範圍進行用於導體接合的所述熱退火。在一些實施例中，所述多個第一導體與所述多個第二導體之間的導體接合包括通孔對通孔接合、接墊對接墊接合或通孔對接墊接合。在一些實施例中，混合接合結構的製造方法更包括：單體化彼此混合接合的所述第一積體電路組件與所述第二積體電路組件，以形成經單體化的多個混合接合結構。
根據本揭露的一些實施例，提供混合接合結構的製造方法，包括下列步驟：提供第一積體電路組件，其中所述第一積體電路組件包括第一半導體基底、第一內連線結構、第一介電層以及多個第一導體群組，所述第一半導體基底包括位於其中的多個第一半導體元件，所述第一內連線結構設置於所述第一半導體基底上並電性連接至所述第一半導體元件，所述第一介電層覆蓋所述第一內連線結構，所述多個第一導體群組嵌入於所述第一介電層中並經由所述第一內連線結構而電性連接至所述第一半導體元件，且所述多個第一導體群組中的至少一第一導體群組包括彼此電性連接的多個第一導體；提供第二積體電路組件，其中所述第二積體電路組件包括第二半導體基底、第二內連線結構、第二介電層以及多個第二導體群組，所述第二半導體基底包括位於其中的多個第二半導體元件，所述第二內連線結構設置於所述第二半導體基底上並電性連接至所述第二半導體元件，所述第二介電層 覆蓋所述第二內連線結構，所述多個第二導體群組嵌入於所述第二介電層中並經由所述第二內連線結構而電性連接至所述第二半導體元件，且所述多個第二導體群組中的至少一第二導體群組包括彼此電性連接的多個第二導體；進行混合接合製程以接合所述第一積體電路組件與所述第二積體電路組件，以使所述第一介電層接合至所述第二介電層，且所述至少一第一導體群組電性連接至所述至少一第二導體群組，其中所述至少一第一導體群組、所述至少一第二導體群組、所述第一內連線結構以及所述第二內連線結構提供分流路徑。
在一些實施例中，所述混合接合製程包括：進行用於所述第一介電層與所述第二介電層之間的介電層接合的處理；進行用於所述多個第一導體與所述多個第二導體之間的導體接合的熱退火。在一些實施例中，用於導體接合的所述熱退火的製程溫度高於用於介電層接合的所述處理的製程溫度。在一些實施例中，在約攝氏100度至約攝氏150度的溫度範圍進行用於介電層接合所述第一介電層與所述第二介電層的所述處理。在一些實施例中，在約攝氏300度至約攝氏400度的溫度範圍進行用於導體接合的所述熱退火。在一些實施例中，所述多個第一導體與所述多個第二導體之間的導體接合包括通孔對通孔接合、接墊對接墊接合或通孔對接墊接合。在一些實施例中，混合接合結構的製造方法更包括：單體化彼此混合接合的所述第一積體電路組件與所述第二積體電路組件，以形成經單體化的多個混合接合結構。
根據本揭露的一些實施例，提供包括第一積體電路晶片與第二積體電路晶片的混合接合結構。第一積體電路晶片包括其中具有多個第一半導體元件的第一半導體基底、設置於所述第一半導體基底上的第一內連線結構、覆蓋所述第一內連線結構的第一介電層以及至少一第一導體群組，所述至少一第一導體群組包括藉由所述第一內連線結構而彼此電性連接的多個第一導體。第二積體電路晶片包括其中具有多個第二半導體元件的第二半導體基底、設置於所述第二半導體基底上的第二內連線結構、覆蓋所述第二內連線結構的第二介電層以及至少一第二導體群組，所述至少一第二導體群組包括藉由所述第二內連線結構而彼此電性連接的多個第二導體。
在一些實施例中，所述多個第一導體包括導電通孔及/或導電接墊。在一些實施例中，所述至少一第一導體群組經由所述第一內連線結構中的第一分流走線而電性連接至所述多個第一半導體元件中的一者，所述至少一第二導體群組經由所述第二內連線結構中的第二分流走線而電性連接至所述多個第二半導體元件中的一者，以使所述第一分流走線、所述第二分流走線、所述多個第一導體與所述多個第二導體提供所述第一積體電路晶片與所述第二積體電路晶片中的分流路徑。在一些實施例中，混合接合結構更包括多個隔離結構，其中所述隔離結構與所述多個第一導體電性絕緣，且所述隔離結構環繞所述多個第一導體。在一些實施例中，所述多個隔離結構為電性浮置且彼此分離。在一些實施 例中，所述第一積體電路晶片為影像感測晶片，且所述第二積體電路晶片為邏輯積體電路晶片。
前文概述若干實施例的特徵，使得熟習此項技術者可更佳地理解本揭露的態樣。熟習此項技術者應理解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優勢的其他處理程序及結構的基礎。熟習此項技術者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且熟習此項技術者可在不脫離本揭露的精神及範疇的情況下在本文中進行改變、替代及更改。
100‧‧‧第一積體電路組件
110‧‧‧第一半導體基底
112‧‧‧第一半導體元件
120‧‧‧第一內連線結構
122、222‧‧‧層間介電層
124、224‧‧‧內連線金屬層
128A、128B‧‧‧隔離部分
130‧‧‧第一介電層
140‧‧‧第一導體群組
142‧‧‧第一導體
200‧‧‧第二積體電路組件
210‧‧‧第二半導體基底
212‧‧‧第二半導體元件
220‧‧‧第二內連線結構
230‧‧‧第二介電層
240‧‧‧第二導體群組
242‧‧‧第二導體
CF‧‧‧濾光層
ML‧‧‧微透鏡陣列
SL‧‧‧切割線
ST1‧‧‧第一分流走線
ST2‧‧‧第二分流走線

Claims (12)

  1. 一種混合接合結構的製造方法，包括：提供第一積體電路組件，其中所述第一積體電路組件包括其中具有多個第一半導體元件的第一半導體基底、設置於所述第一半導體基底上的第一內連線結構、覆蓋所述第一內連線結構的第一介電層以及至少一第一導體群組，所述至少一第一導體群組包括藉由所述第一內連線結構而彼此電性連接的多個第一導體；提供第二積體電路組件，其中所述第二積體電路組件包括其中具有多個第二半導體元件的第二半導體基底、設置於所述第二半導體基底上的第二內連線結構、覆蓋所述第二內連線結構的第二介電層以及至少一第二導體群組，所述至少一第二導體群組包括藉由所述第二內連線結構而彼此電性連接的多個第二導體；以及進行混合接合製程以接合所述第一積體電路組件與所述第二積體電路組件，以使所述第一介電層接合至所述第二介電層，且所述多個第一導體接合至所述多個第二導體，其中所述至少一第一導體群組、所述至少一第二導體群組、所述第一內連線結構以及所述第二內連線結構提供分流路徑。
  2. 如申請專利範圍第1項所述的混合接合結構的製造方法，其中所述混合接合製程包括：進行用於所述第一介電層與所述第二介電層之間的介電層接合的處理；以及 進行用於所述多個第一導體與所述多個第二導體之間的導體接合的熱退火。
  3. 如申請專利範圍第2項所述的混合接合結構的製造方法，其中用於導體接合的所述熱退火的製程溫度高於用於介電層接合的所述處理的製程溫度。
  4. 如申請專利範圍第2項所述的混合接合結構的製造方法，其中在約攝氏100度至約攝氏150度的溫度範圍進行用於介電層接合所述第一介電層與所述第二介電層的所述處理；或其中在約攝氏300度至約攝氏400度的溫度範圍進行用於導體接合的所述熱退火。
  5. 如申請專利範圍第1項所述的混合接合結構的製造方法，其中所述多個第一導體與所述多個第二導體之間的導體接合包括通孔對通孔接合、接墊對接墊接合或通孔對接墊接合。
  6. 如申請專利範圍第1項所述的混合接合結構的製造方法，更包括：單體化彼此混合接合的所述第一積體電路組件與所述第二積體電路組件，以形成經單體化的多個混合接合結構。
  7. 一種混合接合結構的製造方法，包括：提供第一積體電路組件，其中所述第一積體電路組件包括第一半導體基底、第一內連線結構、第一介電層以及多個第一導體群組，所述第一半導體基底包括位於其中的多個第一半導體元 件，所述第一內連線結構設置於所述第一半導體基底上並電性連接至所述第一半導體元件，所述第一介電層覆蓋所述第一內連線結構，所述多個第一導體群組嵌入於所述第一介電層中並經由所述第一內連線結構而電性連接至所述第一半導體元件，且所述多個第一導體群組中的至少一第一導體群組包括彼此電性連接的多個第一導體；提供第二積體電路組件，其中所述第二積體電路組件包括第二半導體基底、第二內連線結構、第二介電層以及多個第二導體群組，所述第二半導體基底包括位於其中的多個第二半導體元件，所述第二內連線結構設置於所述第二半導體基底上並電性連接至所述第二半導體元件，所述第二介電層覆蓋所述第二內連線結構，所述多個第二導體群組嵌入於所述第二介電層中並經由所述第二內連線結構而電性連接至所述第二半導體元件，且所述多個第二導體群組中的至少一第二導體群組包括彼此電性連接的多個第二導體；進行混合接合製程以接合所述第一積體電路組件與所述第二積體電路組件，以使所述第一介電層接合至所述第二介電層，且所述至少一第一導體群組電性連接至所述至少一第二導體群組，其中所述至少一第一導體群組、所述至少一第二導體群組、所述第一內連線結構以及所述第二內連線結構提供分流路徑。
  8. 一種混合接合結構，包括：第一積體電路晶片，包括其中具有多個第一半導體元件的第 一半導體基底、設置於所述第一半導體基底上的第一內連線結構、覆蓋所述第一內連線結構的第一介電層以及至少一第一導體群組，所述至少一第一導體群組包括藉由所述第一內連線結構而彼此電性連接的多個第一導體；以及第二積體電路晶片，包括其中具有多個第二半導體元件的第二半導體基底、設置於所述第二半導體基底上的第二內連線結構、覆蓋所述第二內連線結構的第二介電層以及至少一第二導體群組，所述至少一第二導體群組包括藉由所述第二內連線結構而彼此電性連接的多個第二導體，其中所述第一介電層接合至所述第二介電層，且所述多個第一導體接合至所述多個第二導體，其中所述至少一第一導體群組經由所述第一內連線結構中的第一分流走線而電性連接至所述多個第一半導體元件中的一者，所述至少一第二導體群組經由所述第二內連線結構中的第二分流走線而電性連接至所述多個第二半導體元件中的一者。
  9. 如申請專利範圍第8項所述的混合接合結構，其中所述第一分流走線、所述第二分流走線、所述多個第一導體與所述多個第二導體提供所述第一積體電路晶片與所述第二積體電路晶片中的分流路徑。
  10. 如申請專利範圍第8項所述的混合接合結構，更包括多個隔離結構，其中所述隔離結構與所述多個第一導體電性絕緣，且所述隔離結構環繞所述多個第一導體。
  11. 如申請專利範圍第10項所述的混合接合結構，其中所述多個隔離結構為電性浮置且彼此分離。
  12. 如申請專利範圍第8項所述的混合接合結構，其中所述第一積體電路晶片為影像感測晶片，且所述第二積體電路晶片為邏輯積體電路晶片。
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