TWI778858B - 線路基板結構及其製造方法 - Google Patents

線路基板結構及其製造方法 Download PDF

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TWI778858B
TWI778858B TW110141784A TW110141784A TWI778858B TW I778858 B TWI778858 B TW I778858B TW 110141784 A TW110141784 A TW 110141784A TW 110141784 A TW110141784 A TW 110141784A TW I778858 B TWI778858 B TW I778858B
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Taiwan
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circuit substrate
disposed
wafers
connectors
circuit
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TW110141784A
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English (en)
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TW202221882A (zh
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曾子章
林溥如
柯正達
劉漢誠
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欣興電子股份有限公司
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Priority to US17/567,883 priority Critical patent/US20220130781A1/en
Publication of TW202221882A publication Critical patent/TW202221882A/zh
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  • Engineering & Computer Science (AREA)
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Abstract

一種線路基板結構，包括線路基板、至少二晶片以及橋接元件。線路基板具有彼此相對的第一表面與第二表面。至少二晶片並列設置於線路基板的第一表面上且性連接至線路基板。晶片具有主動表面、相對於主動表面的背表面以及連接主動表面與背表面的側表面。晶片包括側邊線路。側邊線路設置於側表面上且具有第一端與第二端。其中，第一端沿著側表面而延伸至主動表面，且第二端沿著側表面而延伸至背表面。橋接元件設置於至少二晶片的背表面上，且透過側邊線路電性連接至至少二晶片的主動表面。

Description

線路基板結構及其製造方法
本發明是有關於一種基板結構及其製造方法，且特別是有關於一種具有多晶片的線路基板結構及其製造方法。
目前，以晶片互連橋接技術（Embedded Multi-die Interconnect Bridge，EMIB）來整合多晶片的技術方案中，由於基板上的微凸塊與內埋的連接橋上的微凸塊的尺寸不同，因而使得在將多晶片組裝至基板與連接橋時，容易有組裝良率不佳的問題。此外，在使用矽穿孔（TSV）的晶片在多晶片整合的技術方案中，製程繁複的矽穿孔會增加晶片的製作成本。
本發明提供一種線路基板結構及其製造方法，其可有效提升組裝良率或可有效降低晶片製作成本。
本發明的線路基板結構，包括線路基板、至少二晶片以及橋接元件。線路基板具有彼此相對的第一表面與第二表面。至少二晶片並列設置於線路基板的第一表面上且性連接至線路基板。至少二晶片具有主動表面、相對於主動表面的背表面以及連接主動表面與背表面的側表面。至少二晶片包括側邊線路。側邊線路設置於至少二晶片的側表面上且具有第一端與第二端。其中，第一端沿著側表面而延伸至主動表面，且第二端沿著側表面而延伸至背表面。橋接元件設置於至少二晶片的背表面上。橋接元件透過側邊線路電性連接至至少二晶片的主動表面。
在本發明的一實施例中，上述的至少二晶片包括多個接墊。多個接墊設置於至少二晶片的背表面上，且接觸所述側邊線路的第二端。
在本發明的一實施例中，上述的至少二晶片更包括多個第一連接件。多個第一連接件設置於至少二晶片的主動表面上。多個第一連接件中的每一個的尺寸大致上相同。
在本發明的一實施例中，上述的多個第一連接件包括多個第一接墊以及多個第一焊料帽。多個第一接墊設置於主動表面上且接觸側邊線路。多個第一焊料帽設置於多個第一接墊上。多個第一焊料帽中的每一個的尺寸大致上相同。
在本發明的一實施例中，上述的線路基板包括多個第三接墊、多個第四接墊以及多個導電端子。多個第三接墊設置於線路基板的第一表面上且接觸多個第一連接件的多個第一焊料帽。多個第四接墊設置於線路基板的第二表面上。多個導電端子設置多個第四接墊上，且透過多個第四接墊電性連接至線路基板。
在本發明的一實施例中，上述的橋接元件包括玻璃載板、重佈線路層以及至少二第二連接件。重佈線路層設置於玻璃載板上。重佈線路層中的線路為細線路。至少二第二連接件設置於重佈線路層上，且電性連接重佈線路層與側邊線路。至少二第二連接件中的每一個的尺寸大致上相同。
在本發明的一實施例中，上述的至少二第二連接件包括銅柱以及第二焊料帽。銅柱設置於重佈線路層上。第二焊料帽設置於銅柱上。第二焊料帽電性連接至側邊線路。
在本發明的一實施例中，在線路基板的法線方向上，上述的橋接元件重疊於至少二晶片的一部分。
在本發明的一實施例中，上述的橋接元件在線路基板上的正投影重疊於側邊線路在線路基板上的正投影。
在本發明的一實施例中，上述的至少二晶片的其中一個晶片的主動表面與另一個晶片的主動表面齊平，且其中一個晶片的背表面與另一個晶片的背表面齊平。
本發明的線路基板結構的製造方法包括以下步驟。首先，提供至少二晶片。至少二晶片具有主動表面、相對於主動表面的背表面以及連接主動表面與背表面的側表面。至少二晶片包括側邊線路。側邊線路設置於至少二晶片的側表面上且具有第一端與第二端。其中，第一端沿著側表面而延伸至主動表面，且第二端沿著側表面而延伸至背表面。接著，配置橋接元件於至少二晶片的背表面上，以使橋接元件透過側邊線路電性連接至至少二晶片的主動表面。然後，提供線路基板。線路基板具有彼此相對的第一表面與第二表面。最後，並列設置至少二晶片於線路基板的第一表面上，以電性連接至線路基板。
在本發明的一實施例中，上述的橋接元件的製造方法包括以下步驟。首先，提供玻璃載板。接著，形成多個重佈線路層於晶圓或玻璃載板上。多個重佈線路層之間具有間距。多個重佈線路層中的線路為細線路。然後，形成至少二第二連接件於各重佈線路層上，以電性連接至各重佈線路層。至少二第二連接件中的每一個的尺寸大致上相同。然後，對玻璃載板進行薄化製程。最後，進行單體化製程，以形成橋接元件。
在本發明的一實施例中，上述的製造方法更包括以下步驟。設置多個導電端子於線路基板的第二表面上，以電性連接至線路基板。
基於上述，在本發明一實施例的線路基板結構及其製造方法中，相較於一般以製程繁複的矽穿孔（TSV）來連接多個晶片的技術方案，本實施例利用橋接元件與側邊線路來連接多個晶片的設計可以有效地降低晶片的製作成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下將列舉其他實施例以作為說明。在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。
圖1是依照本發明一實施例的線路基板結構的製造方法的流程圖。圖2A至圖2C是依照本發明一實施例的線路基板結構的製造方法的流程示意圖。圖3A至圖3C是依照本發明一實施例的晶片的側邊線路的製造方法的剖面示意圖。圖4A至圖4D是依照本發明一實施例的橋接元件的製造方法的流程示意圖。
本實施例的線路基板結構10的製造方法可包括以下步驟：
首先，請同時參照圖1與圖2A，執行步驟S1：提供至少二晶片10a、10b。晶片10a、10b可具有主動表面110、相對於主動表面110的背表面120以及連接主動表面110與背表面120的側表面130。此處，至少二晶片10a、10b可為具有不同的功能的晶片，例如是邏輯晶片、記憶體晶片、晶片組（chiplet）或其他系統級晶片（SOC）等中的至少二者，但不以此為限。
在本實施例中，晶片10a、10b可包括側邊線路140、多個第一連接件150以及接墊160。側邊線路140設置於晶片10a、10b的側表面130上，且側邊線路140具有第一端142與第二端144。其中，側邊線路140的第一端142可沿著側表面130而延伸至主動表面110，且側邊線路140的第二端144可沿著側表面130而延伸至背表面120。
多個第一連接件150設置於晶片10a、10b的主動表面110上。在本實施例中，多個第一連接件150包括多個第一接墊152以及多個第一焊料帽154。多個第一接墊152設置於主動表面110上，且多個第一接墊152中的其中一個可接觸側邊線路140的第一端142。多個第一焊料帽154可設置於多個第一接墊152上。也就是說，第一焊料帽154與晶片10a、10b分別位於第一接墊152的相對兩側。此處，第一接墊152的材料可例如是銅、鋁或其他合適的材料，第一焊料帽154的材料可例如是錫、錫銀合金或其他合適的材料，但不以此為限。
在本實施例中，第一連接件150為第一接墊152與第一焊料帽154所構成，其具現化為C4（controlled collapse chip connection）凸塊。在其他實施例中，第一連接件也可是C2凸塊（具阻擋層的銅柱（Cu-pillar with barrier layer）與焊料帽（solder cap）所構成），或是其他的導電連接件，本發明並不以此為限。
在本實施例中，多個第一接墊152的每一個的尺寸大致上相同，且多個第一焊料帽154的每一個的尺寸也大致上相同，致使至少二晶片10a、10b的主動表面120上的多個第一連接件150中的每一個也具有大致上相同的尺寸，如此一來，在後續製程中，將晶片10a、10b翻轉以組裝至線路基板30上時（如圖2C所示），由於第一連接件150的尺寸相同，具有良好的平面性，進而有效提升組裝良率。
接墊160設置於背表面120上，且可接觸側邊線路140的第二端144。
在本實施例中，至少二晶片10a、10b的製造方法可例如是包括但不限於以下步驟：
請參照圖3A，本實例的具有側邊線路的晶片的製造方法可包是以下步驟但不限於此：首先，提供晶圓100，並形成種子層102於晶圓（可例如是矽晶圓或其他合適的晶圓）100的相對兩側上。接著，透過例如是光刻製程或其他合適的製程（lithography），以形成光阻層（photoresist）104在種子層102上。此處，種子層102的材料為單層或複合層的金屬層，可例如是銅或在鈦上的銅層或其他合適的材料，但並不以此為限。光阻層104的材料可例如是正光阻或負光阻或其他合適的材料，但並不以此為限。
接著，請參照圖3B，透過例如是鍍敷（plating）、乾膜光阻去除（PR stripping）與蝕刻（etching）或其他合適製程之組合，以形成圖案化線路層（例如可包括第一接墊152、接墊160）在晶圓100的相對兩側上，並移除光阻層104與位於光阻層104正下方的部分種子層102（即，未於其上形成圖案化線路層的種子層102）。然後，進行單體化製程，將晶圓100切割成單個晶片10a’、10b’。具體來說，晶片10a’、10b’具有主動表面110與相對於主動表面110的背表面120以及連接主動表面110與背表面120的側表面130。本實施例的第一接墊152設置於晶片10a’、10b’的主動表面110上，接墊160設置於晶片10a’、10b’的背表面120上，但並不以此為限。此處，圖案化線路層的材料已於上文中詳述，故於此不再重複贅述。
然後，請參考圖3C，形成側邊線路140在單個晶片10a’、10b’上。其中，側邊線路140的第一端142可沿著晶片10a’、10b’的側表面130而延伸至主動表面110，以直接接觸第一接墊152。此外，側邊線路140的第二端144可沿著晶片10a’、10b’的側表面130而延伸至背表面120，以直接接觸接墊160。然後，形成第一焊料帽154在第一接墊152的頂部（相對於晶片10a’、10b’的主動表面120）上，以形成第一連接件150。至此，已製作完成本實施例的晶片10a、10b。
接著，請同時參照圖1與圖2B，執行步驟S2：配置橋接元件20於晶片10a、10b的背表面120上，以使橋接元件20可透過側邊線路140電性連接至晶片10a、10b的主動表面110。在本實施例中，配置橋接元件20於晶片10a、10b的背表面120上的步驟例如是先使晶片10a的背表面120接合至橋接元件20，再使晶片10b的背表面120接合至橋接元件20，但不以此為限。
具體來說，橋接元件20包括玻璃載板210、重佈線路層220以及至少二第二連接件230。重佈線路層220設置於玻璃載板210上。重佈線路層220包括圖案化線路層222、介電層224以及導通孔226。圖案化線路層222設置於玻璃載板210上。介電層224設置於圖案化線路層222上，以覆玻璃載板210與圖案化線路層222。導通孔226連接圖案化線路層222且貫穿介電層224。在本實施例中，重佈線路層220中的線路（即圖案化線路層222）為細線路（fine line），線寬（line width）約2微米（um）至10微米，且線距（line space）約2微米（um）至10微米。本實施例的重部線路層220僅繪示單層的圖案化線路層222、單層的介電層224以及單層的導通孔226，但本發明並不以此為限。在其他實施例，橋接元件的重佈線路層可包括多層的圖案化線路層、多層介電層以及多層導通孔互相堆疊。
至少二第二連接件230設置於重佈線路層220上，以電性連接至重佈線路層220。至少二第二連接件230包括含有阻擋層（未示出）的銅柱（Cu-pillar with barrier layer）232以及第二焊料帽（solder cap）234。換言之，本實施例的第二連接件可具現化為C2凸塊，但本發明不以此為限。在其他實施例中（未示出），第二連接件也可是C4（controlled collapse chip connection）凸塊（由接墊（pad）與焊料帽（solder cap）所構成），或是其他的導電連接件，本發明並不以此為限。
在本實施例中，銅柱232設置於重佈線路層220上且接觸導通孔226。第二焊料帽234設置於銅柱232上。也就是說，第二焊料帽234與重佈線路層220分別位於銅柱232的相對兩側。此處，含有阻擋層的銅柱232的材料可例如是銅，第二焊料凸塊234的材料可例如是錫、錫銀合金，但不以此為限。
在本實施例中，由於至少二第二連接件230的第二焊料帽234可接觸晶片10a、10b的背表面120上的接墊160，因而可使第二焊料帽234透過接墊160而電性連接至側邊線路140，並可使橋接元件20的重佈線路層220可依序透過至少二第二連接件230、接墊160以及側邊線路140而電性連接至晶片10a、10b的主動表面110。也就是說，至少二第二連接件230可電性連接重佈線路層220與側邊線路140。本實施例藉由橋接元件及側邊線路來連接多晶片的設計，可取代以矽穿孔（TSV）來連接多晶片以進行多晶片整合的技術方案。由於晶片的TSV製程較晶片的側邊線路製程更為細緻且繁複，因此，本實施例可有效降低晶片製作成本。
再者，在本實施例中，由於至少二第二連接件230中的每一個銅柱232具有大致上相同的尺寸，且至少二第二連接件230中的每一個第二焊料帽234具有大致上相同的尺寸，因而使得至少二第二連接件230中的每一個第二連接件230也具有大致上相同的尺寸，具有良好的平面性。如此一來，橋接元件可易於與多晶片接合，進而可有效地提升組裝良率。
在本實施例中，橋接元件20的製造方法可例如是包括但不限於以下步驟：首先，請參照圖4A，提供玻璃載板210，並形成多個重佈線路層220、220’於晶圓或玻璃載板210上。其中重佈線路層220與重佈線路層220’之間具有間距D。玻璃載板210具有厚度T1。此外，重佈線路層220’的組成與重佈線路層220的組成相同，各組成已於上文中詳述，故於此不在重複贅述。
特別說明的是，本實施例以玻璃載板210作為載板（carrier），並於其上製作重佈線路層220，但本發明並不以此為限。在其他實施例中，也可以使用矽晶圓作為載板來製作重佈線路層200，本發明於此不加以限制。只要載板的表面具有高度平整性可用於製作細線路，並具有足夠強度可乘載多晶片的接合以及後續的薄化製程，即可用以作為橋接元件的載板。
然後，請參照圖4B，形成至少二第二連接件230於重佈線路層220上，以使至少二第二連接件230可電性連接至重佈線路層220；並形成至少二第二連接件230’於重佈線路層220’上，以使至少二第二連接件230’可電性連接至重佈線路層220’。第二連接件220’的組成與第二連接件220的組成相同，其中的各組成已於上文中詳述，故於此不再贅述。
然後，請參照圖4C，對玻璃載板210進行薄化製程，以使薄化後的玻璃載板210的厚度為T2。詳細來說，可例如是以化學機械平坦化（Chemical-Mechanical Planarization，CMP）對玻璃載板210相對於重佈線路層220、220’的表面進行薄化製程，其中，厚度為T2小於厚度為T1。
最後，請參照圖4D，進行單體化製程，以形成橋接元件20、20’。具體來說，例如是沿著重佈線路層220的側邊221以及重佈線路層220’的側邊221’對玻璃載板210進行切割，以形成單獨的橋接元件20、20’。至此，已製作完成本實施例的橋接元件20、20’。
然後，請同時參照圖1與圖2C，執行步驟S3：提供線路基板30。線路基板30具有彼此相對的第一表面30a與第二表面30b。線路基板30包括多個第三接墊310、多個第四接墊320以及多個導電端子330。多個第三接墊310設置於線路基板30的第一表面30a上。多個第四接墊320設置於線路基板30的第二表面30b上。多個導電端子330設置多個第四接墊320上。線路基板30與多個導電端子330分別位於多個第四接墊320的相對兩側。多個導電端子330可透過多個第四接墊320電性連接至線路基板30。
最後，請再同時參照圖1與圖2C，執行步驟S4：並列設置至少二晶片10a、10b於線路基板30的第一表面30a上，以使至少二晶片10a、10b可電性連接至線路基板30。具體來說，晶片10a與晶片10b相鄰設置，且晶片10a與晶片10b之間沒有其他晶片或元件(包括被動元件)。至少二晶片10a、10b的其中一個晶片10a的主動表面110與另一個晶片10b的主動表面110齊平，且其中一個晶片10a的背表面120與另一個晶片10b的背表面120齊平。
在本實施例中，由於至少二晶片10a、10b的多個第一連接件150可接觸線路基板30的多個第三接墊310，因而可使至少二晶片10a、10b可透過多個第一連接件150與多個第三接墊310而電性連接至線路基板30。
此外，在本實施例中，在線路基板30的法線方向上，橋接元件20可重疊於至少二晶片10a、10b的一部分。在本實施例中，橋接元件20在線路基板30上的正投影可重疊於側邊線路140在線路基板30上的正投影。至此，已製作完成本實施例的線路基板結構10。
簡言之，本實施例的線路基板結構10可包括線路基板30、至少二晶片10a、10b以及橋接元件20。線路基板30具有彼此相對的第一表面30a與第二表面30b。至少二晶片10a、10b並列設置於線路基板30的第一表面30a上且性連接至線路基板30。至少二晶片10a、10b具有主動表面110、相對於主動表面110的背表面120以及連接主動表面110與背表面120的側表面130。至少二晶片10a、10b包括側邊線路140。側邊線路140設置於至少二晶片10a、10b的側表面130。上且具有第一端142與第二端144。其中，第一端142沿著側表面130而延伸至主動表面110，且第二端144沿著側表面130而延伸至背表面120。橋接元件20設置於至少二晶片10a、10b的背表面120上。橋接元件20透過側邊線路140電性連接至至少二晶片10a、10b的主動表面110。
綜上所述，在本發明一實施例的線路基板結構及其製造方法中，相較於一般以製程繁複的矽穿孔（TSV）來連接多個晶片的技術方案，本實施例利用橋接元件與側邊線路來連接多個晶片的設計可以有效地降低晶片的製作成本。此外，由於橋接元件的至少二第二連接件中的每一個第二連接件可具有大致上相同的尺寸，因而使得橋接元件可以提供良好的平面性，以利於至少二晶片可易於接合或組裝至橋接元件，進而有效地提升接合或組裝的良率。另外，由於至少二晶片的多個第一連接件中的每一個第一連接件可具有大致上相同的尺寸，因而使得至少二晶片可以提供良好的平面性，以利於至少二晶片可易於接合或組裝至線路基板，進而有效地提升接合或組裝的良率。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10:基板結構 10a、10b、10a’、10b’:晶片 100:晶圓 102:種子層 104:光阻層 110:主動表面 120:背表面 130:側表面 140:側邊線路 142:第一端 144:第二端 150:第一連接件 152:第一接墊 154:第一焊料帽 160:接墊 20、20’:橋接元件 210:玻璃載板 220、220’:重佈線路層 221、221’:側邊 222、222’:圖案化線路層 224、224’:介電層 226、226’:導通孔 230、230’:第二連接件 232、232’:銅柱 234、234’:第二焊料帽 30:線路基板 30a:第一表面 30b:第二表面 310:第三接墊 320:第四接墊 330:導電端子 D:間距 T1、T2:厚度
圖1是依照本發明一實施例的線路基板結構的製造方法的流程圖。 圖2A至圖2C是依照本發明一實施例的線路基板結構的製造方法的剖面示意圖。 圖3A至圖3C是依照本發明一實施例的晶片的側邊線路的製造方法的剖面示意圖。 圖4A至圖4D是依照本發明一實施例的橋接元件的製造方法的剖面示意圖。
10:基板結構
10a、10b:晶片
110:主動表面
120:背表面
130:側表面
140:側邊線路
150:第一連接件
152:第一接墊
154:第一焊料帽
160:接墊
20:橋接元件
210:玻璃載板
220:重佈線路層
230:第二連接件
232:銅柱
234:第二焊料帽
30:線路基板
30a:第一表面
30b:第二表面
310:第三接墊
320:第四接墊
330:導電端子

Claims (15)

  1. 一種線路基板結構，包括： 線路基板，具有彼此相對的第一表面與第二表面； 至少二晶片，並列設置於所述線路基板的所述第一表面上，且電性連接至所述線路基板，其中所述至少二晶片具有主動表面、相對於所述主動表面的背表面以及連接所述主動表面與所述背表面的側表面，且所述至少二晶片包括： 側邊線路，設置於所述至少二晶片的所述側表面上且具有第一端與第二端，其中所述第一端沿著所述側表面而延伸至所述主動表面，且所述第二端沿著所述側表面而延伸至所述背表面；以及 橋接元件，設置於所述至少二晶片的所述背表面上，且透過所述側邊線路電性連接至所述至少二晶片的所述主動表面。
  2. 如請求項1所述的線路基板結構，其中所述至少二晶片包括多個接墊，所述多個接墊設置於所述至少二晶片的所述背表面上，且接觸所述側邊線路的所述第二端。
  3. 如請求項1所述的線路基板結構，其中所述至少二晶片包括多個第一連接件，所述多個第一連接件設置於所述至少二晶片的所述主動表面上，且所述多個第一連接件中的每一個的尺寸大致上相同。
  4. 如請求項3所述的線路基板結構，其中所述多個第一連接件包括： 多個第一接墊，設置於所述主動表面上，且接觸所述側邊線路；以及 多個第一焊料帽，設置於所述多個第一接墊上，其中所述多個第一焊料帽中的每一個的尺寸大致上相同。
  5. 如請求項4所述的線路基板結構，其中所述線路基板包括： 多個第三接墊，設置於所述線路基板的所述第一表面上，且接觸所述多個第一連接件的所述多個第一焊料帽； 多個第四接墊，設置於所述線路基板的所述第二表面上；以及 多個導電端子，設置所述多個第四接墊上，且透過所述多個第四接墊電性連接至所述線路基板。
  6. 如請求項1所述的線路基板結構，其中所述橋接元件包括： 玻璃載板； 重佈線路層，設置於所述玻璃載板上，其中所述重佈線路層中的線路為細線路；以及 至少二第二連接件，設置於所述重佈線路層上，且電性連接所述重佈線路層與所述側邊線路，其中所述至少二第二連接件中的每一個的尺寸大致上相同。
  7. 如請求項6所述的線路基板結構，其中所述至少二第二連接件包括： 銅柱，設置所述重佈線路層上；以及 第二焊料帽，設置於所述銅柱上，且電性連接至所述側邊線路。
  8. 如請求項1所述的線路基板結構，其中在所述線路基板的法線方向上，所述橋接元件重疊於所述至少二晶片的一部分。
  9. 如請求項1所述的線路基板結構，其中所述橋接元件在所述線路基板上的正投影重疊於所述側邊線路在所述線路基板上的正投影。
  10. 如請求項1所述的線路基板結構，所述至少二晶片的其中一個晶片的主動表面與另一個晶片的主動表面齊平，且所述其中一個晶片的背表面與所述另一個晶片的背表面齊平。
  11. 一種線路基板結構的製造方法，包括： 提供至少二晶片，其中所述至少二晶片具有主動表面、相對於所述主動表面的背表面以及連接所述主動表面與所述背表面的側表面，且所述至少二晶片包括： 側邊線路，設置於所述至少二晶片的所述側表面上且具有第一端與第二端，其中所述第一端沿著所述側表面而延伸至所述主動表面，且所述第二端沿著所述側表面而延伸至所述背表面； 配置橋接元件於所述至少二晶片的所述背表面上，以使所述橋接元件透過所述側邊線路電性連接至所述至少二晶片的所述主動表面； 提供線路基板，其中所述線路基板具有彼此相對的第一表面與第二表面；以及 並列設置所述至少二晶片於所述線路基板的所述第一表面上，以電性連接至所述線路基板。
  12. 如請求項11所述的製造方法，其中所述至少二晶片包括多個第一連接件，所述多個第一連接件設置於所述至少二晶片的所述主動表面上，且所述多個第一連接件中的每一個的尺寸大致上相同。
  13. 如請求項12所述的製造方法，其中所述多個第一連接件包括： 多個第一接墊，設置於所述主動表面上，且接觸所述側邊線路；以及 多個第一焊料帽，設置於所述多個第一接墊上，其中所述多個第一焊料帽中的每一個的尺寸大致上相同。
  14. 如請求項11所述的製造方法，其中所述橋接元件的製造方法包括： 提供玻璃載板； 形成多個重佈線路層於所述玻璃載板上，其中所述多個重佈線路層之間具有間距，且所述多個重佈線路層中的線路為細線路； 形成至少二第二連接件於各所述多個重佈線路層上，以電性連接至各所述多個重佈線路層，其中所述至少二第二連接件中的每一個的尺寸大致上相同； 對所述玻璃載板進行薄化製程；以及 進行單體化製程，以形成所述橋接元件。
  15. 如請求項14所述的製造方法，其中所述至少二第二連接件包括： 銅柱，設置所述重佈線路層上；以及 第二焊料帽，設置於所述銅柱上，且電性連接至所述側邊線路。
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