CN112701100A - 晶片至晶圆结合结构以及使用其的半导体封装件 - Google Patents

晶片至晶圆结合结构以及使用其的半导体封装件 Download PDF

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CN112701100A
CN112701100A CN202010640793.9A CN202010640793A CN112701100A CN 112701100 A CN112701100 A CN 112701100A CN 202010640793 A CN202010640793 A CN 202010640793A CN 112701100 A CN112701100 A CN 112701100A
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China
Prior art keywords
pad
test
wafer
bonding
layer
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CN202010640793.9A
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洪志硕
姜芸炳
姜明成
金泰勋
朴相天
李赫宰
黄智焕
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN112701100A publication Critical patent/CN112701100A/zh
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Abstract

根据本发明构思的一方面，提供了一种晶片至晶圆结合结构，其包括晶片，该晶片具有第一测试焊盘、形成在第一测试焊盘上的第一结合焊盘以及第一绝缘层，第一结合焊盘穿透第一绝缘层。该结构还可包括晶圆，该晶圆具有第二测试焊盘、形成在第二测试焊盘上的第二结合焊盘以及第二绝缘层，第二结合焊盘穿透第二绝缘层。该结构还可包括围绕第一结合焊盘的所有侧表面和第二结合焊盘的所有侧表面的聚合物层，该聚合物层布置在晶片和晶圆之间。此外，晶圆和晶片可被结合在一起。

Description

晶片至晶圆结合结构以及使用其的半导体封装件
相关申请的交叉引用
本申请要求2019年10月7日提交于韩国知识产权局的韩国专利申请No.10-2019-0123973的优先权，其公开内容整体以引用方式并入本文中。
技术领域
本发明构思涉及晶片至晶圆结合结构以及使用其的半导体封装件，更具体地，涉及一种包括聚合物层的晶片至晶圆结合结构以及使用该晶片至晶圆结合结构的半导体封装件。
背景技术
最近，根据电子行业的快速发展和用户的需求，电子装置已变得更紧凑且更轻。对于电子装置中使用的半导体封装件，要求高性能和大容量以及小型化和轻量化。响应于这些要求，为了实现高性能和大容量以及小型化和轻量化，正不断对其中结合多个半导体晶片的半导体封装件进行研究和开发。
发明内容
本发明构思提供了一种在被直接结合(直接结合)的结合焊盘之间具有优异的结合可靠性的晶片至晶圆结合结构以及使用该晶片至晶圆结合结构的半导体封装件。
本发明构思的技术思想要解决的问题不限于上述问题，本领域普通技术人员可从以下描述清楚地理解其它未提及的问题。
根据本发明构思的一方面，提供了一种晶片至晶圆结合结构，其包括晶片，该晶片具有第一测试焊盘、形成在第一测试焊盘上的第一结合焊盘以及第一绝缘层，第一结合焊盘穿透第一绝缘层。该结构还可包括晶圆，该晶圆具有第二测试焊盘、形成在第二测试焊盘上的第二结合焊盘以及第二绝缘层，第二结合焊盘穿透第二绝缘层。该结构还可包括围绕第一结合焊盘的所有侧表面和第二结合焊盘的所有侧表面的聚合物层，该聚合物层被布置在晶片和晶圆之间。此外，晶圆和晶片可被结合在一起。
根据本发明构思的另一方面，提供了一种晶片至晶圆结合结构，其包括晶片，该晶片具有在第一衬底上的第一集成电路层、连接到第一集成电路层的第一金属布线层、在第一金属布线层上的多个第一测试焊盘、第一绝缘层以及形成在多个第一测试焊盘上的多个第一结合焊盘，所述多个第一结合焊盘穿透第一绝缘层。该结构还可包括晶圆，该晶圆具有在第二衬底上的第二集成电路层、连接到第二集成电路层的第二金属布线层、在第二金属布线层上的多个第二测试焊盘、第二绝缘层以及形成在多个第二测试焊盘上的多个第二结合焊盘，所述多个第二结合焊盘穿透第二绝缘层。该结构还可包括围绕第一结合焊盘的所有侧表面和第二结合焊盘的所有侧表面的聚合物层，该聚合物层被布置在晶片和晶圆之间。此外，不平坦部分可形成在多个第一测试焊盘中的至少一个第一测试焊盘的表面上，并且多个第一结合焊盘和多个第二结合焊盘面向彼此并且彼此结合。
根据本发明构思的另一方面，提供了一种半导体封装件，其包括在第一衬底上的第一金属布线层、在第一金属布线层上的第一测试焊盘、在第一测试焊盘上的第一绝缘层、在第一测试焊盘和第一绝缘层上的聚合物层、在聚合物层上的第二绝缘层、在聚合物层和第二绝缘层上的第二测试焊盘。该结构还可包括在第二测试焊盘上的第二金属布线层、在第二金属布线层上的第二衬底以及穿透聚合物层并连接第一测试焊盘和第二测试焊盘的结合焊盘，该结合焊盘由聚合物层围绕。
根据本发明构思的另一方面，提供了一种半导体封装件的制造方法，该方法包括：制备第一晶圆，该第一晶圆包括在第一衬底上的第一金属布线层、在第一金属布线层上的第一测试焊盘以及在第一测试焊盘上的第一绝缘层，该第一晶圆包括多个单独的晶片。该方法还可包括：对第一绝缘层进行图案化以暴露第一测试焊盘的顶表面；通过使暴露的第一测试焊盘与测试装置的测试引脚接触来执行测试；在第一绝缘层和第一测试焊盘上形成掩模图案；以及在第一测试焊盘的未形成掩模图案的表面上形成第一结合焊盘。该方法还可包括：去除掩模图案；形成覆盖所有第一绝缘层、第一测试焊盘和第一结合焊盘的第一聚合物层；通过对第一聚合物层进行抛光来暴露第一结合焊盘；通过切割第一晶圆来将第一晶圆分离成单独的晶片；以及将已分离的晶片结合到第二晶圆。此外，每个晶片可包括至少一个第一结合焊盘。
附图说明
通过以下结合附图进行的详细描述，将更清楚地理解本发明构思的实施例，附图中：
图1是示出根据本发明构思的实施例的晶片至晶圆结合结构的结合部分的剖视图；
图2A至图2C是示出制造图1的晶片至晶圆结合结构的工艺的部分的剖视图；
图3至图5是示出根据本发明构思的实施例的晶片至晶圆结合结构的结合部分的剖视图；
图6是示出根据本发明构思的实施例的晶片至晶圆的结合工艺的立体图；
图7是示出根据本发明构思的实施例的晶片至晶圆结合结构的剖视图；
图8A至图8I是示出制造图7的晶片至晶圆结合结构的工艺的剖视图；
图9是示出根据本发明构思的实施例的晶片至晶圆结合结构的剖视图；
图10A和图10B是示出制造图9的晶片至晶圆结合结构的工艺的部分的剖视图；
图11是示出根据本发明构思的实施例的半导体封装件的剖视图；
图12是示出根据本发明构思的实施例的半导体封装件的剖视图。
具体实施方式
以下，将参照附图详细描述本发明构思的实施例。
图1是示出根据本发明构思的实施例的晶片至晶圆结合结构10的结合部分的剖视图。
参照图1，晶片至晶圆结合结构10可具有其中晶片100-1结合到晶圆100-2的结构。
晶片100-1可指单独的半导体晶片或单独的半导体芯片。晶片100-1可包括第一测试焊盘110-1、第一绝缘层120-1、第一结合焊盘130-1、第一聚合物层140-1和第一层间绝缘层150-1。为了描述方便，晶片100-1接触晶圆100-2的表面可被称为晶片100-1的顶表面，与晶片100-1的顶表面相对的晶片100-1的表面可被称为晶片100-1的底表面。例如，晶片100-1的顶表面可接触晶圆100-2，晶片100-1的底表面可与晶片100-1的顶表面相对并且不与晶圆100-2直接接触。此外，顶表面和底表面可在水平方向上延伸。
晶圆100-2可指其中多个半导体晶片没有单独地分离的衬底或者其中多个半导体芯片没有单独地分离的衬底。例如，晶圆可包括其上设置有多个半导体晶片和/或多个半导体芯片的衬底。晶圆100-2可包括第二测试焊盘110-2、第二绝缘层120-2、第二结合焊盘130-2、第二聚合物层140-2和第二层间绝缘层150-2。为了描述方便，晶圆100-2接触晶片100-1的表面可被称为晶圆100-2的顶表面，与晶圆100-2的顶表面相对的晶圆100-2的表面可被称为晶圆100-2的底表面。例如，晶圆100-2的顶表面可接触晶片100-1，晶圆100-2的底表面可与晶圆100-2的顶表面相对并且不与晶片100-1直接接触。将理解，当元件被称为与另一元件“接触”时，它可直接接触、连接或耦接到另一元件或另一元件上，或者可存在中间元件。相反，当元件被称为与另一元件“直接接触”时，不存在中间元件。
例如，第一测试焊盘110-1可具有双镶嵌图案。双镶嵌图案可以是具有底部窄且顶部宽的结构的图案，并且可通过双镶嵌工艺形成。例如，构成第一测试焊盘110-1的材料可包括铝(Al)。构成第一测试焊盘110-1的材料可包括与构成第一结合焊盘130-1的材料相比具有相对低的硬度和强度的金属。例如，第一测试焊盘110-1的顶表面可具有矩形形状。然而，第一测试焊盘110-1的顶表面的形状可不限于矩形形状。例如，第一测试焊盘110-1的顶表面可具有诸如圆形形状、椭圆形形状和多边形形状的各种形状。
第一测试焊盘110-1可被配置为多个，例如多个第一测试焊盘110-1。第一结合焊盘130-1可形成在多个第一测试焊盘110-1的部分(或子组)上，并且第一结合焊盘130-1可不形成在多个第一测试焊盘110-1的剩余部分上。例如，第一结合焊盘130-1可仅形成在多个第一测试焊盘110-1的子组上，并且可不形成在多个第一结合焊盘130-1中的每个结合焊盘上。第一绝缘层120-1、第一结合焊盘130-1和第一聚合物层140-1可与其上形成第一结合焊盘130-1的第一测试焊盘110-1的顶表面接触。此外，第一绝缘层120-1和第一聚合物层140-1可与其上不形成第一结合焊盘130-1的第一测试焊盘110-1的顶表面接触。
当从侧视图看时，第一测试焊盘110-1在水平方向上的最大宽度可大于第一结合焊盘130-1在水平方向上的最大宽度。此外，当在平面图中看时，第一测试焊盘110-1的表面积可大于第一结合焊盘130-1的表面积。
例如，第一绝缘层120-1可包括氧化硅、氮化硅和/或氮氧化硅。第一绝缘层120-1可包括单一材料的单个层，或者可包括不同材料的多个层。例如，当第一绝缘层120-1包括多个层时，第一绝缘层120-1可包括第一氮化硅碳(SiCN)层、正硅酸乙酯(TEOS)层和第二SiCN层。此外，第一绝缘层120-1可包括第一SiCN层、第一TEOS层、第二SiCN层和第二TEOS层。
第一结合焊盘130-1可布置在多个第一测试焊盘110-1中的一些上。第一结合焊盘130-1可被布置为在不通过垂直接触件的情况下使第一结合焊盘130-1的底表面与第一测试焊盘110-1的顶表面接触。例如，第一结合焊盘130-1的底表面可与第一测试焊盘110-1的顶表面直接接触。此外，第一结合焊盘130-1的所有侧表面可被第一聚合物层140-1围绕。
第一结合焊盘130-1可通过例如镀覆工艺或物理气相沉积(PVD)工艺来形成。第一结合焊盘130-1可具有例如圆柱形形状。然而，第一结合焊盘130-1的形状不限于此。例如，第一结合焊盘130-1可具有诸如椭圆柱、正方柱和多边形柱的各种形状。
第一结合焊盘130-1可具有各种尺寸。例如，第一结合焊盘130-1在水平方向上的宽度可为约1μm至约20μm。例如，第一结合焊盘130-1在竖直方向上的厚度可为其宽度的约15％至约50％。此外，随着第一结合焊盘130-1的宽度增加，厚度与宽度之比可相对减小。例如，当第一结合焊盘130-1的宽度为约1μm时，其厚度可为约1μm至约201μm。当第一结合焊盘130-1的宽度为约201μm时，其厚度可为约31μm至约51μm。当然，第一结合焊盘130-1的宽度和厚度不限于上述值。
第一聚合物层140-1可形成在第一测试焊盘110-1和第一绝缘层120-1上，并且可具有围绕第一结合焊盘130-1的侧表面的结构。第一聚合物层140-1可具有围绕第一绝缘层120-1的所有侧表面和顶表面以及第一结合焊盘130-1的侧表面的结构。此外，第一结合焊盘130-1的顶表面S1可与第一聚合物层140-1的顶表面S2共面。
例如，第一聚合物层140-1可包括具有相对高的耐热性和高结合强度的聚合物材料。第一聚合物层140-1可包括容易地通过热处理回流或者容易地通过热处理与另一聚合物(例如，晶圆100-2的第二聚合物层140-2)组合的材料。此外，第一聚合物层140-1可包括通过热处理固化并且由于固化而维持强结合力的材料。
在一些实施例中，例如，第一聚合物层140-1可包括聚酰亚胺、聚酰胺、聚丙烯酸酯和聚芳酰胺中的任一种。当然，第一聚合物层140-1的材料不限于此。在其它实施例中，当第一聚合物层140-1具有上述特性(例如，耐热、可回流、通过固化的更高结合强度等)时，第一聚合物层140-1可包括上述材料以外的其它类型的材料。
构成晶圆100-2的元件的结构、材料等可与上述构成晶片100-1的元件的结构、材料等基本上相同或相似。因此，省略晶圆100-2的详细描述。
在一些实施例中，与第二测试焊盘110-2相比，第一测试焊盘110-1可包括一些其它特性。可在至少一个第一测试焊盘110-1中形成不平坦部分110-1G(非平面部分)。例如，如图1所示，示出左第一测试焊盘110-1(标记)和右第一测试焊盘110-1(未标记)，并且不平坦部分110-1G可对应于非平面的并且也不与其它测试焊盘110-1共面的突起和/或凹陷(凸出和/或缩进)。又例如，右第一测试焊盘110-1(未标记)不与左第一测试焊盘110-1(标记)共面。第一测试焊盘110-1的不平坦部分110-1G可通过用于筛选晶片100-1的测试工艺形成。可执行测试工艺以验证晶片100-1的功能和电连接。可通过将测试设备(参见图8C中的TA)的测试引脚(参见图8C中的TP)与第一测试焊盘110-1物理接触来执行测试工艺。与非接触式测试工艺相比，接触式测试工艺可具有相对高的测试性能，因此接触式测试工艺可具有优于非接触式测试工艺的优点。然而，如第一测试焊盘110-1的不平坦部分110-1G，接触式测试工艺可伴随有降低表面均匀性的形状。
尽管在图1中第一结合焊盘130-1和第二结合焊盘130-2以及第一聚合物层140-1和第二聚合物层140-2通过点划线来彼此区分，但图示旨在表明第一结合焊盘130-1和第一聚合物层140-1源自晶片100-1，并且第二结合焊盘130-2和第二聚合物层140-2源自晶圆100-2。因此，本领域技术人员将理解，第一结合焊盘130-1和第二结合焊盘130-2可彼此结合以形成集成结合焊盘130A，并且第一聚合物层140-1和第二聚合物层140-2可彼此结合以形成一体配置的聚合物层140A。
晶片至晶圆结合结构10可具有其中晶片100-1和晶圆100-2通过热处理彼此结合的结构。例如，通过使用热处理将第一结合焊盘130-1和第二结合焊盘130-2结合并且使用热处理将第一聚合物层140-1和第二聚合物层140-2结合。这里，可在形成第一结合焊盘130-1与第二结合焊盘130-2之间的结合耦接的温度下执行热处理。在一些实施例中，例如，热处理温度可为约180℃至约300℃。
如上所述，第一聚合物层140-1和第二聚合物层140-2由于当它们在上面公开的热处理温度范围内被加热时通过回流而具有流动性，因此可填充不想要的空隙。此外，由于第一聚合物层140-1和第二聚合物层140-2由于通过热处理的固化而维持强结合力，所以可防止和/或抑制(在传统硅绝缘层之间的结合中可能发生的)结合故障的可能性。
此外，第一聚合物层140-1和第二聚合物层140-2可通过热处理而被固化以具有约90％或更高的固化度。通常，固化可指聚合物材料在玻璃化转变温度以上结晶。例如，约90％或更高的固化度可意指约90％或更多的聚合物材料在玻璃化转变温度以上结晶，并且根据该结晶，可维持非常强的结合力。
结果，在根据本发明构思的技术思想的晶片至晶圆结合结构10中，可利用聚合物层140A的回流填充不想要的空隙，并且可防止和/或抑制由该现象导致的缺陷。此外，通过将聚合物层140A以约90％或更高的固化度结合，可维持非常强的结合力。例如，当利用将第一聚合物层140-1和第二聚合物层140-2加热到适当热处理温度的回流工艺时，所得聚合物层140A可具有约90％或更大的固化度，因此在晶片100-1和晶圆100-2之间形成相对强的结合力。
此外，通过利用类似第一聚合物层140-1的具有良好流动性的材料填充不平坦部分110-1G，根据本发明构思的技术思想的晶片至晶圆结合结构10可形成不受第一测试焊盘110-1的表面均匀性影响并且可靠的结合结构。例如，当测试设备(参见图8C中的TA)导致在第一测试焊盘110-1中形成不平坦部分110-1G时，可如上所述通过回流工艺可靠地填充不平坦部分110-1G。
最终，由于测试的已知合格晶片(KGD)100-1可以可靠的结合结构安装在晶圆100-2上，所以根据本发明构思的技术构思的晶片至晶圆结合结构10可增加半导体封装件的产率和可靠性。
图2A至图2C是示出制造图1的晶片至晶圆结合结构10的工艺的部分的剖视图。
参照图2A，可在第一层间绝缘层150-1和第一测试焊盘110-1上形成包括第一开口120-1H的第一绝缘层120-1。
在第一层间绝缘层150-1和第一测试焊盘110-1上形成初步绝缘层之后，通过经由光学处理和蚀刻工艺对初步绝缘层进行图案化，可形成具有暴露第一测试焊盘110-1的中心部分的第一开口120-1H的第一绝缘层120-1。
在用于筛选晶片100-1的测试工艺中，可能形成第一测试焊盘110-1的不平坦部分110-1G。可通过将测试设备(参见图8C中的TA)的测试引脚(参见图8C中的TP)与第一测试焊盘110-1物理接触来执行测试工艺。这样，可伴随降低表面均匀性的形状，如第一测试焊盘110-1的不平坦部分110-1G。
参照图2B，可在多个第一测试焊盘110-1中的一些上布置初步结合焊盘130-1P。
初步结合焊盘130-1P可被布置为使得其底表面接触第一测试焊盘110-1的顶表面。初步结合焊盘130-1P可仅形成在多个第一测试焊盘110-1之中不包括不平坦部分110-1G的第一测试焊盘110-1上。例如，初步结合焊盘130-1P可仅形成在其中测试引脚TP(参见图8C)没有接触过和/或将不接触相应第一测试焊盘110-1的第一测试焊盘110-1上。又例如，初步结合焊盘130-1P可仅形成在未被测试引脚TP(参见图8C)接触和/或变形的第一测试焊盘110-1的子组上，并且可不形成在被测试引脚TP(参见图8C)接触和/或变形的剩余第一测试焊盘110-1上。
初步结合焊盘130-1P可例如在镀覆工艺或物理气相沉积(PVD)工艺中形成。例如，构成初步结合焊盘130-1P的材料可包括铜(Cu)。构成初步结合焊盘130-1P的材料可包括与构成第一测试焊盘110-1的材料相比具有相对更高的硬度和强度的金属。
初步结合焊盘130-1P可具有例如圆柱形形状。初步结合焊盘130-1P在竖直方向上的厚度可大于第一绝缘层120-1在竖直方向上的厚度。此外，初步结合焊盘130-1P在水平方向上的宽度可小于第一开口120-1H在水平方向上的宽度。
参照图2C，可在第一绝缘层120-1和第一测试焊盘110-1上形成第一聚合物层140-1以覆盖第一结合焊盘130-1的侧表面。
第一聚合物层140-1可具有围绕第一绝缘层120-1的所有侧表面和顶表面以及第一结合焊盘130-1的侧表面的结构。该结构通过减少与第一结合焊盘130-1接触的材料的种类可减少在不同材料之间的接触区域处发生的缺陷。在一些实施例中，第一聚合物层140-1可不接触结合焊盘130-1的顶表面。
第一聚合物层140-1可包括具有相对高的耐热性和高结合强度的聚合物材料。第一聚合物层140-1可包括通过热处理容易地回流，并且此外通过热处理容易地结合到其它聚合物层和/或材料的材料。此外，第一聚合物层140-1可包括通过热处理固化并且由于固化而维持强结合力的材料。
当从侧视图看时，第一测试焊盘110-1在水平方向上的最大宽度110-1W可大于第一结合焊盘130-1在水平方向上的最大宽度130-1W。此外，当在平面图中看时，第一测试焊盘110-1的表面积可大于第一结合焊盘130-1的表面积。因此，不仅第一结合焊盘130-1，而且第一绝缘层120-1和第一聚合物层140-1可接触第一测试焊盘110-1的顶表面。
第一绝缘层120-1在竖直方向上的厚度120-1T可为约0.5μm至约10μm。此外，第一聚合物层140-1在竖直方向上的厚度140-1T可为约1μm至约20μm。第一聚合物层140-1在竖直方向上的厚度140-1T可为第一绝缘层120-1在竖直方向上的厚度120-1T的约两倍或更多倍。在一些实施例中，第一聚合物层140-1的暴露表面的增加和其厚度的增加可有意地维持晶片至晶圆结合结构10中的强结合力。此外，聚合物层140A在竖直方向上的厚度可为第一聚合物层140-1在竖直方向上的厚度140-1T的约两倍，并且可为约2μm至约40μm。
此外，第一聚合物层140-1在竖直方向上的厚度140-1T可与第一结合焊盘130-1在竖直方向上的厚度基本上相同。例如，第一聚合物层140-1的顶表面可与第一结合焊盘130-1的顶表面共面。这可以是因为第一聚合物层140-1与第一结合焊盘130-1一起被平坦化。
通过经由直接结合将此工艺中制造的晶片100-1安装在晶圆100-2(参见图1)上，可制造根据本发明构思的示例实施例的晶片至晶圆结合结构10。
图3至图5是示出根据本发明构思的示例实施例的晶片至晶圆结合结构10的结合部分的各剖视图。
下面将描述的构成晶片至晶圆结合结构(20、30、40)的每一个的组件以及包括在组件中的材料的大部分可与参照图1描述的那些基本上相同或相似。因此，为了描述方便，将主要描述与上述晶片至晶圆结合结构10(参照图1)的不同之处。
参照图3，晶片至晶圆结合结构20可具有其中晶片100-3结合到晶圆100-4的结构。
晶片100-3可包括第三测试焊盘110-3、第三绝缘层120-3、第三结合焊盘130-3、第三聚合物层140-3和第三层间绝缘层150-3。
第三结合焊盘130-3可形成在所有多个第三测试焊盘110-3上。例如，第三结合焊盘130-3可形成在多个第三测试焊盘110-3中的各个测试焊盘上。第三结合焊盘130-3可被布置为使得第三结合焊盘130-3的底表面接触第三测试焊盘110-3的顶表面。第三结合焊盘130-3的所有侧表面可由第三聚合物层140-3围绕。
晶圆100-4可具有与晶片100-3基本上相同或相似的配置，并且可包括：第四测试焊盘110-4、第四绝缘层120-4、第四结合焊盘130-4、第四聚合物层140-4和第四层间绝缘层150-4。
在一些实施例中，与第四测试焊盘110-4相比，第三测试焊盘110-3可包括一些其它特性。例如，可在至少一个第三测试焊盘110-3中形成不平坦部分110-3G。如上所解释的，第三测试焊盘110-3的不平坦部分110-3G可在用于筛选晶片100-3的测试工艺中形成。相反，在第四测试焊盘110-4中可不形成不平坦部分。
第三结合焊盘130-3可填充第三测试焊盘110-3的不平坦部分110-3G。因此，形成在包括不平坦部分110-3G的第三测试焊盘110-3上的(位于图3中的右侧的)第三结合焊盘130-3的底表面的表面轮廓可具有根据第三测试焊盘110-3的顶表面的形状(由第三测试焊盘110-3的顶表面的形状限定)的形状。相反，形成在不具有不平坦部分110-3G的第三测试焊盘110-3上的(位于图3中的左侧的)第三结合焊盘130-3的底表面可以是平坦表面(例如，平面表面)。结果，多个结合焊盘130B中的一些结合焊盘130B的厚度可大于多个结合焊盘130B中的其它结合焊盘130B的厚度。
通过使第三测试焊盘110-3的不平坦部分110-3G由第三结合焊盘130-3填充，根据本发明构思的技术思想的晶片至晶圆结合结构20可形成不受第三测试焊盘110-3的表面均匀性影响并且可靠的结构。
参照图4，晶片至晶圆结合结构30可具有其中晶片100-1结合到晶圆100-2的结构。
晶片100-1可以以其中第一阻挡金属层131-1围绕第一结合焊盘130-1的底表面和侧表面的结构形成。第一阻挡金属层131-1可面向第一测试焊盘110-1的结构，使得第一阻挡金属层131-1的底表面接触第一测试焊盘110-1并且第一阻挡金属层131-1的侧表面接触第一聚合物层140-1。
以基本上相同的方式，晶圆100-2可以以其中第二阻挡金属层131-2围绕第二结合焊盘130-2的下表面和侧表面的结构形成。第二阻挡金属层131-2可面向第二结合焊盘130-2的结构，使得第二阻挡金属层131-2的底表面接触第二测试焊盘110-2并且第二阻挡金属层131-2的侧表面接触第二聚合物层140-2。
第一阻挡金属层131-1可防止Cu(其可以是构成第一结合焊盘130-1的材料)扩散，并且可包括包含例如钛(Ti)和钽(Ta)、氮化钛(TiN)和氮化钽(TaN)中的一种或更多种的层叠结构。然而，第一聚合物层140-1的材料不限于此。
第一结合焊盘130-1和第一阻挡金属层131-1可形成在多个第一测试焊盘110-1的一些部分上，并且第一结合焊盘130-1和第一阻挡金属层131-1可不形成在多个第一测试焊盘110-1的其它部分上。例如，第一结合焊盘130-1和第一阻挡金属层131-1可仅形成在第一测试焊盘110-1中的一些(子组)上，并且可不形成在剩余第一测试焊盘110-1(剩余子组)上。
第一聚合物层140-1可形成在第一测试焊盘110-1和第一绝缘层120-1上，并且可具有围绕第一阻挡金属层130-1的侧表面的结构。第一聚合物层140-1可具有围绕第一绝缘层120-1的所有侧表面和顶表面以及第一阻挡金属层131-1的侧表面的结构。此外，第一结合焊盘130-1的顶表面S1、第一阻挡金属层131-1的顶表面S11和第一聚合物层140-1的顶表面S2可彼此共面。这可以是例如第一结合焊盘130-1、第一阻挡金属层131-1和第一聚合物层140-1与彼此平坦化的结果。
尽管在图4中第一结合焊盘130-1和第二结合焊盘130-2、第一阻挡金属层131-1和第二阻挡金属层131-2以及第一聚合物层140-1和第二聚合物层140-2通过点划线彼此相区分，但该图示旨在表明第一结合焊盘130-1、第一阻挡金属层131-1和第一聚合物层140-1源自晶片100-1，第二结合焊盘130-2、第二阻挡金属层131-2和第二聚合物层140-2源自晶圆100-2。因此，第一结合焊盘130-1和第二结合焊盘130-2可彼此直接结合以形成集成结合焊盘130C，第一阻挡金属层131-1和第二阻挡金属层131-2可彼此直接结合以形成集成阻挡金属层131C，第一聚合物层140-1和第二聚合物层140-2可彼此直接结合以形成集成聚合物层140C。
参照图5，晶片至晶圆结合结构40可具有其中晶片100-3结合到晶圆100-4的结构。
晶片至晶圆结合结构40可在概念上被认为与将晶片至晶圆结合结构20(参照图3)的特性和晶片至晶圆结合结构30(参照图4)的特性组合基本上相同。
因此，通过参考上面给出的晶片至晶圆结合结构20和30的描述，本领域普通技术人员将理解晶片至晶圆结合结构40。因此，省略晶片至晶圆结合结构40的详细描述。
此外，第三阻挡金属层131-3可填充第三测试焊盘110-3的不平坦部分110-3G。因此，形成在包括不平坦部分110-3G的第三测试焊盘110-3上的(位于图5中的右侧的)第三阻挡金属层131-3的底表面的表面轮廓可具有根据(由其限定)(同样位于图5中的右侧的)第三测试焊盘110-3的顶表面的形状的形状。相反，形成在不具有不平坦部分110-3G的(位于图5中的左侧的)第三测试焊盘110-3上的(同样位于图5中的左侧的)第三阻挡金属层131-3的底表面可以是平坦表面。
图6是示出根据本发明构思的实施例的晶片至晶圆结合工艺的立体图。
参照图6，晶片至晶圆结合工艺可将多个晶片100-1安装在一个晶圆100-2上。
首先，将一个晶圆100-2装载到晶圆台WT的晶圆固定部分WP中。接下来，可将多个晶片100-1顺序地安装在这一个晶圆100-2上。最后，可将这一个晶圆100-2卸载到晶圆台WT，并且多个晶片100-1的安装工艺可完成。可根据需要改变顺序来执行上述操作。
在图6中，示出三个晶片100-1被安装在一个晶圆100-2上的状态，但这仅是结合工艺的示例，更大数量的晶片100-1可被顺序地安装在晶圆100-2上。
在结合工艺中，由于经测试和筛选的晶片100-1(已知合格晶片KGD)以可靠的结合结构被安装在一个晶圆100-2上，所以根据本发明构思的技术构思的晶片至晶圆结合结构可增加半导体封装件的产率和可靠性。
在一些实施例中，安装在一个晶圆100-2上的多个晶片100-1中的至少一个可以是虚拟晶片。换言之，已筛选的多个晶片100-1和至少一个虚拟晶片可被一起安装在一个晶圆100-2上。在其它实施例中，没有虚拟晶片，仅已筛选的多个晶片100-1可安装在一个晶圆100-2上。
图7是示出根据本发明构思的实施例的晶片至晶圆结合结构1100的剖视图。
参照图7，晶片至晶圆结合结构1100可详细示出第一层间绝缘层150-1和第二层间绝缘层150-2、第一金属布线层160-1和第二金属布线层160-2、第一集成电路层103-1和第二集成电路层103-2以及第一集成电路层105-1和第二集成电路层105-2。
以下，描述布置在晶片至晶圆结合结构1100的顶部的晶片100-1。
晶片100-1可包括第一衬底101-1、第一集成电路层103-1和105-1、第一测试焊盘110-1、第一绝缘层120-1、第一结合焊盘130-1、第一聚合物层140-1、第一层间绝缘层150-1和第一金属布线层160-1。
第一衬底101-1可包括Si。在一些实施例中，第一衬底101-1可包括诸如锗(Ge)的半导体元素，或者诸如诸如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)和磷化铟(InP)的化合物半导体元素。在一些实施例中，第一衬底101-1可具有绝缘体上硅(SOI)结构。例如，第一衬底101-1可包括掩埋氧化物(BOX)层。此外，第一衬底101-1可包括导电区域，例如，掺杂有杂质的阱，或者掺杂有杂质的结构。此外，第一衬底101-1可具有诸如浅沟槽隔离(STI)结构的各种器件隔离结构。
第一集成电路层103-1和105-1可形成在第一衬底101-1上，并且例如可包括诸如晶体管、二极管、电阻器和电容器的各种半导体器件。图7示出晶体管作为代表性集成电路。例如，晶体管可包括形成在第一衬底101-1中的源极/漏极区域和沟道区域以及形成在第一衬底101-1上的栅极结构。
在一些实施例中，例如，包括在(位于图7中的左侧的)第一集成电路层103-1中的晶体管可以是存储器装置中使用的晶体管，包括在(位于图7中的右侧的)第一集成电路层105-1中的晶体管可以是逻辑器件或运送区域(ferry region)中使用的晶体管。
第一集成电路层(103-1和105-1)可通过第一接触件161-1电连接到第一金属布线层160-1，并且可通过第一金属布线层160-1与外部交换电信号。这里，例如，电信号可包括电源电压、接地电压、信号电压等。第一金属布线层160-1可包括多个布线层。第一金属布线层160-1可包括Cu，但示例实施例不限于此。
第一层间绝缘层150-1可形成在第一衬底101-1上并覆盖第一集成电路层(103-1和105-1)和第一金属布线层160-1。第一层间绝缘层150-1可包括与构成第一金属布线层160-1的布线层的数量对应的多个层。当第一层间绝缘层150-1包括多个层时，第一层间绝缘层150-1可包括多个相同的单一材料层，或者可包括具有不同材料层的至少两个层。
第一测试焊盘110-1可被配置为多个，例如多个第一测试焊盘110-1。第一结合焊盘130-1可形成在多个第一测试焊盘110-1中的部分(子组)上，并且第一结合焊盘130-1可不形成在多个第一测试焊盘110-1中的其它剩余部分(剩余子组)上。第一绝缘层120-1、第一结合焊盘130-1和第一聚合物层140-1可与其上形成第一结合焊盘130-1的第一测试焊盘110-1的顶表面接触。此外，第一绝缘层120-1和第一聚合物层140-1可与其上未形成第一结合焊盘130-1的第一测试焊盘110-1的顶表面接触。
第一绝缘层120-1、第一结合焊盘130-1和第一聚合物层140-1的细节可与参照图1描述的那些基本上相同或相似，因此这里省略其详细描述。
第一结合焊盘130-1与第二结合焊盘130-2之间以及第一聚合物层140-1和第二聚合物层140-2之间的区别可仅是为了方便描述并用于理解其各自的起源。因此，第一结合焊盘130-1和第二结合焊盘130-2可彼此不可分离地结合(直接结合)成集成结合焊盘130A，并且第一聚合物层140-1和第二聚合物层140-2可彼此不可分地结合(直接结合)成集成聚合物层140A。
此外，尽管晶圆100-2和晶片100-1被示出为具有相同的尺寸，但晶圆100-2可具有安装多个晶片100-1的尺寸。换言之，晶圆100-2可包括切割之前的衬底，晶片100-1可表示切割之后的衬底。
如上面参照图6描述的，由于经测试和筛选的晶片100-1(已知合格晶片KGD)以可靠的结合结构被安装在一个晶圆100-2上，所以根据本发明构思的技术构思的晶片至晶圆结合结构1100可增加半导体封装件的产率和可靠性。
图8A至图8I是示出制造图7的晶片至晶圆结合结构1100的工艺的剖视图。
参照图8A，示出在第一衬底101-1上形成第一集成电路层(103-1和105-1)、第一层间绝缘层150-1和第一金属布线层160-1。此外，形成电连接到第一金属布线层160-1的第一测试焊盘110-1，并且在第一测试焊盘110-1和第一层间绝缘层150-1上形成初步绝缘层120-1P。
初步绝缘层120-1P可形成为在其最上层处覆盖第一测试焊盘110-1的顶表面和第一层间绝缘层150-1的顶表面二者。例如，初步绝缘层120-1P可包括氧化硅、氮化硅和/或氮氧化硅。例如，初步绝缘层120-1P可如所示形成为单个层，或者可形成为多个层。
参照图8B，示出通过经由光学处理和蚀刻工艺对初步绝缘层120-1P(参照图8A)进行图案化,形成包括暴露第一测试焊盘110-1的顶表面110-1T的第一开口120-1H的第一绝缘层120-1。
可在初步绝缘层120-1P(参照图8A)上形成光掩模图案(未示出)，并且可通过使用光掩模图案作为蚀刻掩模并蚀刻第一绝缘层120-1P(参照图8A)来形成包括第一开口120-1H的初步绝缘层120-1P。在形成第一绝缘层120-1之后，可通过例如灰化工艺和剥离工艺去除光掩模图案。
第一绝缘层120-1可覆盖第一测试焊盘110-1的顶表面110-1T的一部分。换言之，第一绝缘层120-1可不完全暴露第一测试焊盘110-1的顶表面110-1T，而是可仍覆盖边缘部分。例如，第一绝缘层120-1可部分地暴露第一测试焊盘110-1的顶表面110-1T的中心部分并且覆盖第一测试焊盘110-1的顶表面110-1T的剩余边缘部分。
参照图8C，通过使用测试设备TA可对晶片100-1(参照图8A)执行测试工艺。
可执行测试工艺以验证晶片100-1(参照图8A)的功能性和电连接特性。
测试设备TA可包括针形测试引脚TP，并且测试引脚TP可与第一测试焊盘110-1进行物理接触以执行测试工艺。例如，与非接触式测试工艺相比，诸如图8C所示的接触式测试工艺可具有相对高的测试性能。
例如，测试引脚TP可以是连接到测试设备TA的探针卡的一部分。此外，多个测试引脚TP可位于探针卡上。
参照图8D，使用测试设备TA(参照图8C)的测试工艺T100可包括第一操作T110至第六操作T160。
本领域技术人员将容易理解，当特定实施例被不同地实现时，可与所描述的顺序不同地执行特定操作。例如，两个连续描述的操作可基本上同时执行，或者按照与所描述的顺序不同的顺序执行或以相反的顺序执行。
可执行测试晶片的第一操作T110。对晶片的测试可包括例如DC测试、AC测试和/或功能测试。这些测试可以是如上所述的接触式测试工艺。然而，上述测试类型和方法不限于此。
可执行第二操作T120以验证测试结果是否通过。在通过测试之后，晶片可移至筛选晶片的第三操作T130。另一方面，如果晶片没有通过测试，则其可被移至将该晶片确定为有缺陷的第四操作T140。
如果在第三操作T130确定晶片合格，则可执行第五操作T150，其中在后续工艺中将确定为合格的晶片结合到晶圆。另一方面，如果在第四操作T140确定晶片有缺陷，则可执行在后续工艺中修复或丢弃被确定为有缺陷的晶片的第六操作T160。
结果，通过测试工艺T100被选为“通过”和/或被认为合格的晶片可以以可靠的直接结合结构被安装在晶圆上。
参照图8E，示出形成覆盖第一绝缘层120-1和第一测试焊盘110-1的顶表面110-1T的部分的掩模图案M1的形状。
掩模图案M1可形成为具有暴露第一测试焊盘110-1的顶表面110-1T的一部分的第二开口M1H的图案。例如，掩模图案M1可以是光掩模图案或硬掩模图案。
尽管图8E中仅示出一个第二开口M1H，但可形成多个第二开口M1H。换言之，由于通过掩模图案M1的第二开口M1H暴露的第一测试焊盘110-1的顶表面110-1T的部分对应于在后续工艺中形成初步结合焊盘130-1P(参照图8F)的部分，所以当初步结合焊盘130-1P(参照图8F)形成为多个时，掩模图案M1的第二开口M1H可形成为多个以与各个初步结合焊盘130-1P(参照图8F)对应。例如，在具有多个第一测试焊盘110-1的实施例中，可针对多个第一测试焊盘110-1中的每个对应的第一测试焊盘110-1存在对应的第二开口M1H。
参照图8F，可形成初步结合焊盘130-1P以填充掩模图案M1的第二开口M1H(参照图8E)。例如，初步结合焊盘130-1P可至少部分地填充第二开口M1H。
为了形成初步结合焊盘130-1P，例如，可对其上形成有掩模图案M1的第一衬底101-1执行镀覆工艺。在一些实施例中，例如，可首先在第一测试焊盘110-1上形成种子层(未示出)，然后可使用种子层通过镀覆工艺形成初步结合焊盘130-1P。
例如，初步结合焊盘130-1P可包括由铜(Cu)、镍(Ni)和金(Au)形成的金属或其合金，或者Cu和Ni和Au的多种金属的多层结构。这里，初步结合焊盘130-1P被描述为包括Cu。
初步结合焊盘130-1P可形成为仅填充掩模图案M1的一部分，而不完全填充掩模图案M1的第二开口M1H(参照图8E)。换言之，初步结合焊盘130-1P的顶表面的水平可低于掩模图案M1的顶表面的水平。例如，当在剖视图中看时，初步结合焊盘130-1P的顶表面的高度可低于掩模图案M1的顶表面的高度。
参照图8G，可去除掩模图案M1(参照图8F)，并且可形成初步聚合物层140-1P以完全覆盖第一测试焊盘110-1、第一绝缘层120-1和初步结合焊盘130-1P。
初步聚合物层140-1P可填充第一绝缘层120-1的侧壁与初步结合焊盘130-1P的侧壁之间的间隙。此外，初步聚合物层140-1P可填充形成在至少一个第一测试焊盘110-1中的不平坦部分110-1G。
初步聚合物层140-1P可初始形成为比其最终设计厚度大的厚度，因为一些初步聚合物层140-1P的一些可通过后续工艺被去除。例如，比较图8G的初步聚合物层140-1P与图8H的第一聚合物层140-1。此外，可考虑通过后续工艺去除初步聚合物层140-1P的比率或量来适当地调节构成初步聚合物层140-1P的材料。
参照图8H，可例如使用化学机械抛光(CMP)工艺对包括初步聚合物层140-1P(参照图8G)的所得产品进行抛光以使得第一结合焊盘130-1的顶表面暴露。
通过CMP工艺，可形成第一结合焊盘130-1和第一聚合物层140-1。第一结合焊盘130-1的厚度可小于初步结合焊盘130-1P(参照图8G)的厚度。此外，第一聚合物层140-1的厚度可小于初步聚合物层140-1P(参照图8G)的厚度。
第一结合焊盘130-1的顶表面和第一聚合物层140-1的顶表面可形成在同一平面上以共面。此特性可以是CMP工艺的平坦化特性的结果。
参照图8I，(图8I的)晶圆100-2可具有与(图8I的)晶片100-1类似的结构。
可将晶片100-1放置在晶圆100-2上，使得第一结合焊盘130-1面向第二结合焊盘130-2，并且此外，晶片100-1的位置也被可精确地对准。例如，第一结合焊盘130-1的顶表面可被对准为与第二结合焊盘130-2的顶表面精确匹配。
返回参照图7，第一结合焊盘130-1和第二结合焊盘130-2可彼此结合以形成结合焊盘130A，并且可通过将第一聚合物层140-1结合到第二聚合物层140-2以形成聚合物层140A来结合晶片100-1和晶圆100-2。
通过晶片100-1和晶圆100-2的结合，可实现根据本发明构思的技术思想的晶片至晶圆结合结构1100。
此外，晶片至晶圆结合结构1100的制造工艺可与半导体封装件的制造工艺基本上相同或相似。因此，本领域普通技术人员可从上述晶片至晶圆结合结构1100的制造工艺理解半导体封装件的制造工艺。
图9是示出根据本发明构思的实施例的晶片至晶圆结合结构1200的剖视图。
下面将描述的构成晶片至晶圆结合结构1200的组件以及包括在组件中的材料的大部分可与参照图7描述的那些基本上相同或相似。因此，为了描述方便，下面主要描述与上述晶片至晶圆结合结构1100(参照图7)的不同之处。
参照图9，晶片至晶圆结合结构1200可详细示出第三层间绝缘层150-3和第四层间绝缘层150-4、第三金属布线层160-3和第四金属布线层160-4以及第三集成电路层(103-3和105-3)和第四集成电路层(103-4和105-4)。
第三结合焊盘130-3可形成在多个第三测试焊盘110-3中的每个测试焊盘上。第三结合焊盘130-3可被布置为使得第三结合焊盘130-3的底表面接触第三测试焊盘110-3的顶表面。第三结合焊盘130-3的所有侧表面可由第三聚合物层140-3围绕。
与第四测试焊盘110-4相比，第三测试焊盘110-3可包括一些其它特性。例如，可在至少一个第三测试焊盘110-3中形成不平坦部分110-3G。第三测试焊盘110-3的不平坦部分110-3G可在用于筛选晶片100-3的接触式测试工艺(参见图8D的T100)中形成。在一些实施例中，在第四测试焊盘110-4中可不形成不平坦部分。此外，一些实施例可包括具有不平坦部分110-3G的第三测试焊盘110-3和不具有不平坦部分110-3G的第三测试焊盘110-3。
第三结合焊盘130-3可填充第三测试焊盘110-3的不平坦部分110-3G。因此，形成在包括不平坦部分110-3G的第三测试焊盘110-3上的(位于图9中的右侧)第三结合焊盘130-3的底表面的表面轮廓可具有根据第三测试焊盘110-3的顶表面的形状的形状。例如，第三结合焊盘130-3的底表面的表面轮廓可由第三测试焊盘110-3的顶表面的形状限定。相反，形成在不具有不平坦部分110-3G的第三测试焊盘110-3上的(位于图9中的左侧)第三结合焊盘130-3的底表面可以是平坦表面。结果，多个结合焊盘130B中的一些结合焊盘在竖直方向上的厚度可大于其它结合焊盘130B。
图10A和图10B是示出制造图9的晶片至晶圆结合结构1200的工艺的部分的剖视图。
下面描述的构成晶片至晶圆结合结构的制造方法的制造操作的大部分与上面参照图8A至图8I描述的那些基本上相同或相似。此外，还在将第三结合焊盘130-3形成在包括不平坦部分110-3G的第三测试焊盘110-3上的工艺中存在差异。因此，为了描述方便，下面将主要描述与上述晶片至晶圆结合结构的不同之处。
参照图10A，可在第三测试焊盘110-3上形成第三结合焊盘130-3。
第三结合焊盘130-3可形成在多个第三测试焊盘110-3中的所有测试焊盘上。第三结合焊盘130-3可被布置为使得第三结合焊盘130-3的底表面接触第三测试焊盘110-3的顶表面。第三结合焊盘130-3的所有侧表面可由第三聚合物层140-3围绕。
例如，可通过经由CMP工艺对初步结合焊盘(未示出)进行抛光来形成第三结合焊盘130-3，并且可通过经由CMP工艺对初步聚合物层(未示出)进行抛光来形成第三聚合物层140-3。
第三结合焊盘130-3的顶表面和第三聚合物层140-3的顶表面可形成在同一平面上，因此被视为共面。此特性可以是CMP工艺的平坦化特性的结果。
图10B示出制备了具有与晶片100-1相似的结构的晶圆100-4。
可将晶片100-3放置在晶圆100-4上，使得第三结合焊盘130-3面向第四结合焊盘130-4，另外，晶片100-3的位置也可精确地对准。例如，第三结合焊盘130-3的顶表面可被对准为与第四结合焊盘130-4的顶表面精确匹配。
返回参照图9，第三结合焊盘130-3和第四结合焊盘130-4可彼此结合以形成结合焊盘130B，并且可通过将第三聚合物层140-3和第四聚合物层140-4结合以形成聚合物层140B来结合晶片100-3和晶圆100-4。
通过晶片100-3和晶圆100-4的结合，可实现根据本发明构思的技术思想的晶片至晶圆结合结构1200。
图11是示出根据本发明构思的技术思想的半导体封装件1100P的剖视图。
参照图11，半导体封装件1100P可使用半导体芯片1100-1、第二半导体芯片1100-2、结合焊盘130A和聚合物层140A形成直接结合结构。
第一半导体芯片1100-1可由上述晶片100-1制造，并且第二半导体芯片1100-2可由上述晶圆100-2制造。因此，由于构成第一半导体芯片1100-1和第二半导体芯片1100-2的组件的大部分与上面描述的那些相同或相似，所以下面仅描述其差异。
包括在半导体封装件1100P中的第一半导体芯片1100-1和第二半导体芯片1100-2可分别是逻辑芯片或存储器芯片。例如，第一半导体芯片1100-1和第二半导体芯片1100-2可以是相同类型的存储器芯片，或者第一半导体芯片1100-1和第二半导体芯片1100-2之中的一个芯片可以是存储器芯片，另一芯片可以是逻辑芯片。例如，第一半导体芯片1100-1可以是存储器芯片，第二半导体芯片1100-2可以是逻辑芯片。
例如，存储器芯片可以是诸如动态随机存取存储器(RAM)(DRAM)和静态RAM(SRAM)的易失性存储器半导体芯片、或者诸如相变RAM(PRAM)、磁阻RAM(MRAM)、铁电RAM(FeRAM)和电阻RAM(RRAM)的非易失性存储器芯片。此外，例如，逻辑芯片可包括微处理器、模拟元件或数字信号处理器。
第二半导体芯片1100-2可包括穿透第二衬底101-2的贯通电极170-2。凸块焊盘180-2可在第二衬底101-2的底表面101-2B上，使得底表面101-2B连接到贯通电极170-2。凸块焊盘180-2可包括Al、Cu、Ni、钨(W)、铂(Pt)和Au中的至少一种，但不限于此。
钝化层190-2可形成在第二衬底101-2的底表面101-2B上。钝化层190-2可暴露凸块焊盘180-2。
贯通电极170-2可穿透第二衬底101-2，从第二衬底101-2的顶表面101-2T朝着底表面101-2B延伸，并且可连接到第二金属布线层160-2。贯通电极170-2可具有圆柱形状。例如，贯通电极170-2可包括硅通孔(TSV)。
凸块结构BS可接触凸块焊盘180-2。半导体封装件1100P可通过凸块结构BS接收用于第一半导体芯片1100-1和第二半导体芯片1100-2的操作的控制信号、电源信号和接地信号，或者接收待存储在第一半导体芯片1100-1和第二半导体芯片1100-2中的数据信号，或者可将存储在第一半导体芯片1100-1和第二半导体芯片1100-2中的数据提供给外部。例如，凸块结构BS可具有柱结构、球结构或焊料层。
在一些实施例中，半导体封装件1100P可包括凸块结构BS以用于与外部装置(例如，印刷电路板或插入件)连接。
第一半导体芯片1100-1可被布置为使得第一半导体芯片1100-1的顶表面面向第二半导体芯片1100-2的顶表面。第一半导体芯片1100-1可经由结合焊盘130A电连接到第二半导体芯片1100-2。
此外，聚合物层140A可介于第一半导体芯片1100-1和第二半导体芯片1100-2之间，因此，第一半导体芯片1100-1和第二半导体芯片1100-2可彼此组合(耦接)，同时维持非常强的结合力。如所示出的，聚合物层140A可围绕结合焊盘130A。
图12是示出根据本发明构思的技术思想的半导体封装件1200P的剖视图。
下面要描述的构成半导体封装件1200P的组件以及包括在组件中的材料的大部分可与参照图11描述的那些基本上相同或相似。因此，为了描述方便，下面将主要描述与上述半导体封装件1100P(参照图11)的不同之处。
参照图12，半导体封装件1200P可使用第三半导体芯片1200-3、第四半导体芯片1200-4、结合焊盘130B和聚合物层140B形成直接结合结构。
第三半导体芯片1200-3可由上述晶片100-3制造，第四半导体芯片1200-4可由上述晶圆100-4制造。因此，由于构成第三半导体芯片1200-3和第四半导体芯片1200-4的组件的大部分与上面描述的那些相同或相似，所以下面仅描述不同之处。
第四半导体芯片1200-4可包括穿过第四衬底101-4的贯通电极170-4。底部结合焊盘180-4可与第四衬底101-4的底表面101-4B接触以连接到贯通电极170-4。底部结合焊盘180-4可包括Cu，但不限于此。
半导体封装件1200P可通过底部结合焊盘180-4接收用于第三半导体芯片1200-3和第四半导体芯片1200-4的操作的控制信号、电源信号和接地信号，或者接收待存储在第三半导体芯片1200-3和第四半导体芯片1200-4中的数据信号，或者可将存储在第三半导体芯片1200-3和第四半导体芯片1200-4中的数据提供给外部。例如，底部结合焊盘180-4可形成类似结合焊盘130B的直接结合结构。
在一些实施例中，半导体封装件1200P可包括底部结合焊盘180-4以用于与其它半导体芯片直接结合。
第三半导体芯片1200-3可被布置为使得第三半导体芯片1200-3的顶表面面向第四半导体芯片1200-4的顶表面。第三半导体芯片1200-3可通过结合焊盘130B电连接到第四半导体芯片1200-4。
此外，聚合物层140B可介于第三半导体芯片1200-3和第四半导体芯片1200-4之间，因此，第三半导体芯片1200-3和第四半导体芯片1200-4可彼此组合(耦接)，同时维持非常强的结合力。如所示出的，聚合物层140B可围绕结合焊盘130B。
尽管参考本发明的实施例具体地示出和描述了本发明构思，但是将理解，在不脱离所附权利要求的精神和范围的情况下，可对其进行形式和细节上的各种改变。

Claims (20)

1.一种晶片至晶圆结合结构，所述结构包括：
晶片，其包括第一测试焊盘、形成在所述第一测试焊盘上的第一结合焊盘以及第一绝缘层，所述第一结合焊盘穿透所述第一绝缘层；
晶圆，其包括第二测试焊盘、形成在所述第二测试焊盘上的第二结合焊盘以及第二绝缘层，所述第二结合焊盘穿透所述第二绝缘层；以及
聚合物层，其围绕所述第一结合焊盘的所有侧表面和所述第二结合焊盘的所有侧表面，所述聚合物层被布置在所述晶片和所述晶圆之间，
其中，所述晶圆和所述晶片被结合在一起。
2.根据权利要求1所述的结构，其中，所述聚合物层包括在所述晶片上的第一聚合物层以及在所述晶圆上的第二聚合物层，所述第一聚合物层和所述第二聚合物层直接结合在一起。
3.根据权利要求1所述的结构，其中，当从剖面图看时，
所述第一测试焊盘的水平宽度大于所述第一结合焊盘的水平宽度，并且
所述第二测试焊盘的水平宽度大于所述第二结合焊盘的水平宽度。
4.根据权利要求1所述的结构，其中，构成所述第一测试焊盘和所述第二测试焊盘的材料不同于构成所述第一结合焊盘和所述第二结合焊盘的材料。
5.根据权利要求1所述的结构，还包括：
包括所述第一测试焊盘的多个第一测试焊盘，
其中，所述多个第一测试焊盘中的至少一个第一测试焊盘上未形成对应的第一结合焊盘，并且
其中，不平坦部分被形成在其上未形成对应的第一结合焊盘的所述至少一个第一测试焊盘的表面上。
6.根据权利要求5所述的结构，其中，所述聚合物层填充所述不平坦部分。
7.根据权利要求1所述的结构，还包括：
包括所述第一测试焊盘的多个第一测试焊盘，
其中，所述多个第一测试焊盘中的每个第一测试焊盘具有对应的第一结合焊盘，并且
其中，不平坦部分被形成在所述多个第一测试焊盘中的至少一个的表面上。
8.根据权利要求7所述的结构，其中，所述不平坦部分被所述第一结合焊盘之一填充。
9.根据权利要求1所述的结构，其中，所述第一绝缘层的侧表面、所述第二绝缘层的侧表面以及所述第一绝缘层和所述第二绝缘层的面向彼此的水平表面由聚合物层围绕。
10.根据权利要求1所述的结构，还包括围绕所述第一结合焊盘和所述第二结合焊盘的阻挡金属层。
11.一种晶片至晶圆结合结构，所述结构包括：
晶片，其包括在第一衬底上的第一集成电路层、连接到所述第一集成电路层的第一金属布线层、在所述第一金属布线层上的多个第一测试焊盘、第一绝缘层以及形成在所述多个第一测试焊盘上的多个第一结合焊盘，所述多个第一结合焊盘穿透所述第一绝缘层；
晶圆，其包括在第二衬底上的第二集成电路层、连接到所述第二集成电路层的第二金属布线层、在所述第二金属布线层上的多个第二测试焊盘、第二绝缘层以及形成在所述多个第二测试焊盘上的多个第二结合焊盘，所述多个第二结合焊盘穿透所述第二绝缘层；以及
聚合物层，其围绕所述第一结合焊盘的所有侧表面和所述第二结合焊盘的所有侧表面，该聚合物层布置在所述晶片和所述晶圆之间，
其中，不平坦部分被形成在所述多个第一测试焊盘中的至少一个第一测试焊盘的表面上，并且
所述多个第一结合焊盘和所述多个第二结合焊盘面向彼此并且彼此结合。
12.根据权利要求11所述的结构，其中，所述聚合物层包括聚酰亚胺、聚酰胺、聚丙烯酸酯和聚芳酰胺中的至少一个。
13.根据权利要求11所述的结构，其中
所述第一测试焊盘和所述第二测试焊盘包括铝(Al)，并且
所述第一结合焊盘和所述第二结合焊盘包括铜(Cu)。
14.根据权利要求11所述的结构，其中，当从剖面图看时，
所述第一绝缘层和所述第二绝缘层的竖直厚度分别为约0.5μm至约10μm，
所述聚合物层的最大竖直厚度为约2μm至约40μm，并且
所述聚合物层的最大竖直厚度是所述第一绝缘层和所述第二绝缘层的竖直厚度之和的两倍或更多倍。
15.根据权利要求11所述的结构，还包括：
包括所述晶片的多个晶片，并且
其中，所述多个晶片中的至少一个是虚拟晶片。
16.一种半导体封装件，包括：
第一金属布线层，其在第一衬底上；
第一测试焊盘，其在所述第一金属布线层上；
第一绝缘层，其在所述第一测试焊盘上；
聚合物层，其在所述第一测试焊盘和所述第一绝缘层上；
第二绝缘层，其在所述聚合物层上；
第二测试焊盘，其在所述聚合物层和所述第二绝缘层上；
第二金属布线层，其在所述第二测试焊盘上；
第二衬底，其在所述第二金属布线层上；以及
结合焊盘，其穿透所述聚合物层并连接所述第一测试焊盘和所述第二测试焊盘，所述结合焊盘被所述聚合物层围绕。
17.根据权利要求16所述的半导体封装件，还包括：
包括所述第一测试焊盘的多个第一测试焊盘，并且
其中，不平坦部分被形成在所述多个第一测试焊盘中的至少一个的表面上。
18.根据权利要求16所述的半导体封装件，还包括穿透所述第二衬底并连接所述第二金属布线层的贯通电极。
19.根据权利要求18所述的半导体封装件，还包括在所述第二衬底上电连接到所述贯通电极的外部连接端子。
20.根据权利要求18所述的半导体封装件，还包括在所述第二衬底上电连接到所述贯通电极的底部结合焊盘。
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