CN112864145A - 集成电路装置 - Google Patents
集成电路装置 Download PDFInfo
- Publication number
- CN112864145A CN112864145A CN202011263779.8A CN202011263779A CN112864145A CN 112864145 A CN112864145 A CN 112864145A CN 202011263779 A CN202011263779 A CN 202011263779A CN 112864145 A CN112864145 A CN 112864145A
- Authority
- CN
- China
- Prior art keywords
- metal
- die
- insulator
- capacitor
- ultra
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 219
- 239000002184 metal Substances 0.000 claims abstract description 219
- 239000003990 capacitor Substances 0.000 claims abstract description 166
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 239000004020 conductor Substances 0.000 description 93
- 238000002161 passivation Methods 0.000 description 57
- 238000000034 method Methods 0.000 description 39
- 238000004519 manufacturing process Methods 0.000 description 30
- 239000003989 dielectric material Substances 0.000 description 26
- 230000008569 process Effects 0.000 description 16
- 239000000463 material Substances 0.000 description 12
- 230000008901 benefit Effects 0.000 description 10
- 238000005137 deposition process Methods 0.000 description 10
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 2
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- KUVFGOLWQIXGBP-UHFFFAOYSA-N hafnium(4+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Hf+4] KUVFGOLWQIXGBP-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QQDBFAKOVGNARI-UHFFFAOYSA-N [O-2].[O-2].[Hf+4].[O-2].[Al+3] Chemical compound [O-2].[O-2].[Hf+4].[O-2].[Al+3] QQDBFAKOVGNARI-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- MJGARAGQACZIPN-UHFFFAOYSA-N aluminum hafnium(4+) oxygen(2-) Chemical compound [O--].[O--].[Al+3].[Hf+4] MJGARAGQACZIPN-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
- H01L2224/03616—Chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05657—Cobalt [Co] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8003—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8003—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area
- H01L2224/80047—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area by mechanical means, e.g. severing, pressing, stamping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8034—Bonding interfaces of the bonding area
- H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9202—Forming additional connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
- H01L2225/06531—Non-galvanic coupling, e.g. capacitive coupling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
本发明提供一种集成电路装置。集成电路装置包括第一裸片与第二裸片。第一、第二裸片各自包括:各自包含第一、第二电路系统的第一、第二基底;各自置于第一、第二基底的上方的第一、第二互连结构;各自置于上述第一互连结构的上方的第一、第二介电层;各自置于第一、第二介电层的上方的第一、第二连接垫。第一裸片的第一连接垫连接于第二裸片的第二连接垫,第一裸片与第二裸片的至少一个包括金属─绝缘体─金属电容器,金属─绝缘体─金属电容器包括逐一向上方堆叠的超过两层的金属层。
Description
技术领域
本发明实施例涉及集成电路技术,尤其涉及集成电路装置及其形成方法。
背景技术
半导体集成电路(integrated circuitry;IC)产业已经历快速成长。集成电路材料与设计的技术进展,使每一代的集成电路比前一代具有更小且更复杂的电路。在集成电路演进的过程中,功能密度(比如单位芯片面积的内连线装置数目)通常随着几何尺寸(比如采用的制作工艺所能产生的最小构件(或线))的缩小而增加。
随着半导体装置的尺寸持续缩减,在制造方面的挑战亦增加。例如,用于在集成电路芯片形成电容器装置的现有工艺已经不够简单或不够便宜。因此虽然现有的半导体制造方法通常符合其预期目的,但无法完全满足所有方面的需求。
发明内容
本发明的目的在于提供一种集成电路装置,以解决上述至少一个问题。
本发明的一实施例是关于一种集成电路装置,其包括一第一裸片与一第二裸片。上述第一裸片包括一第一基底、一第一互连结构、一第一介电层及多个第一连接垫。上述第一基底包含第一电路系统,上述第一互连结构置于上述第一基底的上方,上述第一介电层置于上述第一互连结构的上方,上述第一连接垫置于上述第一介电层的上方。上述第二裸片包括一第二基底、一第二互连结构、一第二介电层及多个第二连接垫。上述第二基底包含第二电路系统,上述第二互连结构置于上述第二基底的上方,上述第二介电层置于上述第二互连结构的上方,上述第二连接垫置于上述第二介电层的上方。上述第一裸片的上述第一连接垫连接于上述第二裸片的上述第二连接垫,上述第一裸片与上述第二裸片的至少一个包括一金属─绝缘体─金属电容器,上述金属─绝缘体─金属电容器包括逐一向上方堆叠的超过两层的金属层。
另一实施例是关于一种集成电路装置,其包括一第一裸片、一第二裸片与一电容器。上述第一裸片与上述第二裸片经由多个连接垫而连接在一起,上述电容器嵌于上述第一裸片与上述第二裸片的至少一个。上述电容器包括超过二个金属层,上述金属层的一第一子集是电性且物理性连接于一第一导体构件,上述金属层的一第二子集是电性且物理性连接于一第二导体构件,上述第二导体构件不同于上述第一导体构件。
又另一实施例是关于一种集成电路装置的形成方法,其包括:提供一第一裸片,上述第一裸片包括一第一基底与一第一互连结构,上述第一互连结构形成在上述第一基底的上方;在上述第一互连结构形成一第一介电层;在上述第一介电层的上方形成一或多个第一连接垫;提供一第二裸片,上述第二裸片包括一第二基底与一第二互连结构,上述第二互连结构形成在上述第二基底的上方;在上述第二互连结构形成一第二介电层;在上述第二介电层的上方形成一或多个第二连接垫;以及将上述一或多个第一连接垫连接于上述一或多个第二连接垫。上述第一裸片与上述第二裸片的至少一个包括嵌于其中的一金属─绝缘体─金属电容器。
附图说明
根据以下的详细说明并配合所附附图做完整公开。应注意的是,根据本产业的一般作业,图示并未必按照比例绘制。事实上,可能任意的放大或缩小元件的尺寸,以做清楚的说明。
图1是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图2是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图3是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图4是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图5是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图6是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图7是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图8是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图9是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图10是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图11是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图12是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图13是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图14是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图15是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图16是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图17是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图18是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图19是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图20是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图21是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图22是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图23是一集成电路装置(或其一部分)的一剖面侧视图,根据本发明实施例的各种面向,在各种制造阶段所建构。
图24是制造一集成电路装置的方法的一流程图,根据本发明实施例的一实施形态。
附图标记如下:
100:集成电路结构
110:集成电路基底
115,315,415:电路系统
120,320,420:互连结构
130,330,430,610:金属线
140:介电材料
150,270,350,450:钝化膜
160,210,260,700,710,720,800,810,820:导体层
180:光刻工艺
190,220:沉积工艺
200:介电层
265,395,495,895:超高密度金属─绝缘体─金属电容器
290,390,490,491:导体垫
300,400:裸片
310,410:基底
335,570,571,580,581:基底贯穿孔
340,440,500,510,520,530,600,740,750,840,850:介电层
380A,380B,480A,480B:钝化膜层
550,560,620:连接垫
585:膜框
590:填隙材料
630:导体凸块
650:部分
1000:方法
1010,1020,1030,1040,1050,1060,1070:步骤
具体实施方式
要了解的是,以下的公开内容提供许多不同的实施例或范例以实现本发明实施例的不同构件。以下的公开内容叙述各个构件及其排列方式的特定实施例或范例,以简化本发明实施例的说明。当然,这些特定的范例并非用以限定。例如,元件的尺寸并非受限于所公开的范围或值,但可能依存于工艺条件及/或装置所需求的性质。此外,若是本发明实施例叙述了一第一构件形成于一第二构件之上或上方,即表示其可能包括上述第一构件与上述第二构件是直接接触的实施例,亦可能包括了有附加构件形成于上述第一构件与上述第二构件之间,而使上述第一构件与第二构件可能未直接接触的实施例。为了简洁,可能以任意的比例示出各种构件。此外,本发明实施例可能会在各种实施例重复使用相同的元件符号。这样的重复是为了叙述上的简化与明确,而非意指所讨论的不同实施例及/或结构之间的关系。
此外,空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件,而非局限于图示方向。举例来说,若翻转附图中的装置,原本在其他单元或结构之下的单元将转为在其他单元或结构之上。因此,例示性的用语“之下”可指之上与之下两种方向。装置亦可转动90°或其他角度,因此方向性用语仅用以说明图示中的方向。
此外,当数值或数值范围的描述有“约”、“近似”、或类似用语时,如所属技术领域中技术人员所理解,其意图包含一合理的数值范围,此范围包括上述数字,例如包含所述数值的+/-10%的范围内或其他数值。举例来说,用语“约5nm”包含的尺寸范围介于4.5nm至5.5nm之间。
集成电路芯片包括复数种不同形式的微电子构件,例如晶体管、电阻器、电感器、电容器等等。对于每一种这些形式的微电子构件,可能会有各式各样的制造方法,结果得到这些构件的不同结构。本发明实施例涉及一独特形式的电容器——称为超高密度金属─绝缘体─金属(super high-density metal-insulator-metal;SHDMIM)电容器以及如何将其整合进一封装架构,例如小外型集成电路(Small Outline Integrated Circuitry;SOIC),后文参考附图图1至图24而作详细讨论。
图1~图9显示一集成电路结构100的一系列的示意性的局部剖面侧视图,根据本发明实施例在一实施形态的各种面向所建构。请参考图1,集成电路结构100包括一集成电路基底110。在一些实施形态中,集成电路基底110包括一半导体基底,例如一硅基底。集成电路基底110亦可包括各种装置,例如场效晶体管(field-effect transistors;FETs)、存储器单元(memory cells)、图像感测器、无源元件、其他装置或上述的组合。在一些实施形态中,集成电路基底110包括具有例如平面场效晶体管等的各种集成电路装置的多个平面有源区。在一些其他的实施形态中,集成电路基底110包括多个鳍式(举例来说,垂直突起的)有源区,其具有形成于其上的各种集成电路装置。作为一非限制性的例子,如图1所示的形成在集成电路基底110的电路系统115。电路系统115可包括平面式的晶体管或鳍式场效晶体管类型的晶体管。
集成电路基底110亦包括一互连结构120,互连结构120形成在上述半导体基底的上方。互连结构120包括各种导体构件,例如金属线(举例来说,多个金属线130)、接触物、导孔等等,以提供水平与垂直的电路布线。例如金属线130等的上述多个金属线分布在多层金属层中,例如一第一金属层(举例来说,一M1层)、一第二金属层(举例来说,一M2层)、……以及一顶部金属层。除了其他事项,互连结构120的上述导体构件提供到达电路系统115的电性连接。互连结构120亦包括一介电材料140,以提供各种导体构件之间的电性隔离,以避免电路的短路。
现在请参考图2,在互连结构120的上方,例如在互连结构120的一顶部金属层的上方,形成一钝化膜150。钝化膜150可对集成电路基底110提供保护。在一些实施形态中,钝化膜150包括一氮化硅(SiN)膜及上述氮化硅膜上的一非掺杂的硅酸盐玻璃(un-dopedsilica glass;USG)膜。这些膜是通过一适当的沉积工艺所形成,例如通过高密度化学气相沉积(high density plasma chemical vapor deposition;HDPCVD)等。
现在请参考图3,在钝化膜150的上方形成一导体层160。在一些实施形态中,导体层160包括一金属、一金属合金或一金属化合物。例如,导体层160可包括氮化钛。导体层160的形成可使用一或多道的沉积工艺,例如化学气相沉积(chemical vapor deposition;CVD)、物理气相沉积(physical vapor deposition;PVD)、原子层沉积(atomic layerdeposition;ALD)或上述的组合。要了解的是,这个导体层160的一部分将作为本发明实施例的超高密度金属─绝缘体─金属电容器的多个电极中的一个(或是,多个导体片中的一个)。
现在请参考图4,施行一光刻工艺180以将导体层160导体层160图形化。作为光刻工艺180的一部分,可以在导体层160的上方形成一图形化的光刻胶层。使用此图形化的光刻胶层作为一掩模,可以对导体层160进行蚀刻。导体层160的未被上述图形化的光刻胶层保护的部分会被蚀除,而导体层160在上述图形化的光刻胶层下的部分则受到保护而在进行上述蚀刻工艺之后留下。导体层160的留下来的部分则作为上述超高密度金属─绝缘体─金属电容器的电极或导体片。
现在请参考图5,施行一沉积工艺190,以在导体层160的留下来的部分的上方以及钝化膜150的暴露的表面的上方形成一介电层200。沉积工艺190可包括化学气相沉积、物理气相沉积、原子层沉积或上述的组合。在一些实施形态中,介电层200可包括具有高k值(high-k)的介电常数的一介电材料。例如一高k值的介电材料可以是具有大于约4(举例来说,大于氧化硅的介电常数)的介电常数的介电材料。作为上述高k值的介电材料的适当选项包括但不限于:氧化铪(hafnium oxide)、氧化锆(zirconium oxide)、氧化铝(aluminumoxide)、二氧化铪-氧化铝掺合物(hafnium dioxide-alumina alloy)、氧化铪硅(hafniumsilicon oxide)、氮氧化铪硅(hafnium silicon oxynitride)、氧化铪钽(hafniumtantalum oxide)、氧化铪钛(hafnium titanium oxide)、氧化铪锆(hafnium zirconiumoxide)、其类似物或上述的组合。
现在请参考图6,在介电层200的上方形成一导体层210。在一些实施形态中,导体层210包括一金属材料,例如具有与导体层160实质上类似的材料成分的一金属材料。导体层210的形成可通过使用一适当的沉积工艺来沉积一导体层,之后将所沉积的导体层图形化,以形成导体层210的各种区段。导体层210的上述各种区段亦可作为上述超高密度金属─绝缘体─金属电容器的电极或导体片。介电层200提供在导体层160与导体层210的区段之间的电性隔离或绝缘。
现在请参考图7,施行一沉积工艺220以将介电层200扩张到导体层210上方。沉积工艺220可包括化学气相沉积、物理气相沉积、原子层沉积或上述的组合。在一些实施形态中,所沉积的材料可包括一高k值介电材料。
现在请参考图8,在介电层200的上方形成一导体层260。在一些实施形态中,导体层260包括一金属材料,例如具有与导体层160或210(举例来说,氮化钛)实质上类似的材料成分的一金属材料。导体层260的形成可通过使用一适当的沉积工艺来沉积一导体层,之后将所沉积的导体层图形化,以形成导体层260的各种区段。导体层260的上述各种区段亦可作为一超高密度金属─绝缘体─金属电容器265的电极或导体片。介电层200的材料可作为超高密度金属─绝缘体─金属电容器265的介电材料。
要注意的是,超高密度金属─绝缘体─金属电容器265是一多片电容器(multi-plate capacitor),其可包括不只二个导体片(或是,超过二个金属层)。例如,示于图8的超高密度金属─绝缘体─金属电容器265可包括垂直逐一向上堆叠的三个导体层160、210与260。由于一电容器包括二个电极,有些导体片可电性耦合在一起而作为一个电极。例如,导体层210的一个区段可作为超高密度金属─绝缘体─金属电容器265的一个电极;导体层160的一个区段可电性耦合于导体层260的一个区段,一起作为超高密度金属─绝缘体─金属电容器265的另一个电极。也是要了解的是,第1至8图仅示出用于一超高密度金属─绝缘体─金属电容器265的制造过程的一非限制性的例子。示于图8的超高密度金属─绝缘体─金属电容器265的各种导体层160、210、260的排列或架构并无限定于所示情况的意思。在其他实施形态中,超高密度金属─绝缘体─金属电容器265可具有其他形状或架构、或是其他数量的导体或金属层(举例来说,超过三个)。
现在请参考图9,在导体层260的上方以及在介电层200的暴露的表面的上方形成一钝化膜270。在一些实施形态中,钝化膜270可包括与钝化膜150实质上类似的材料,例如钝化膜270可包括氮化硅或非掺杂的硅酸盐玻璃。钝化膜270的形成,将超高密度金属─绝缘体─金属电容器265嵌于钝化膜150与270中。
其后,可形成多个导体垫290。可使用一或多道的图形化、蚀刻及沉积工艺来形成导体垫290。例如,可蚀刻出多个开口或沟槽,以垂直穿过钝化膜150与270及介电层200的选定区域以及导体层160、210与260的选定区域。然后,可以以一导体材料(举例来说,铝)填充上述开口或沟槽,以形成导体垫290。导体垫290提供到达超高密度金属─绝缘体─金属电容器265的各个电极或导体片的电性连接,例如到达导体层160、210与260的一子集(subset)。在所示出的实施形态中,有些导体垫290亦电性耦合于互连结构120的金属线130的一子集,由此将超高密度金属─绝缘体─金属电容器265的电极或导体片与互连结构120电性互连。
图10~图16显示一系列的示意性的局部剖面侧视图,显示如何将包含一或多个超高密度金属─绝缘体─金属电容器(例如超高密度金属─绝缘体─金属电容器265)的集成电路裸片接合或封装,其根据本发明实施例在一实施形态的各种面向。现在请参考图10,提供一裸片300。裸片300可以是尚未被单片化(singulate)的一晶片的一部分。裸片300包括一基底310。基底310可类似于前文参考第1至9图所讨论的集成电路基底110。裸片300可包括一电路系统315。电路系统315可类似于前文参考图1至图9所讨论的电路系统115。
裸片300亦可包括一互连结构320。互连结构320可类似于前文参考图1至图9所讨论的互连结构120。例如,互连结构320可包括多个金属层,多个金属线(例如金属线330)形成于上述金属层。通过一介电材料340将金属线330彼此电性隔离,而介电材料340可类似于前文参考图1至图9所讨论的介电材料140。
亦可形成多个导孔或多个接触件,使其电性耦合于金属线330中的一或多个。作为一范例,可形成一基底贯穿孔(through substrate via;TSV)335,使其延伸而至少部分地垂直贯穿基底310。将基底贯穿孔335的一端形成为与金属线330中的一个有物理性接触。如此,基底贯穿孔335可用来提供到达互连结构320的电性连接,并反过来提供到达裸片300的装置或构件的其余部分(例如电路系统315)的电性连接。作为另一个例子,可形成一导体垫390,使其与金属线330中的另一个有电性及物理性接触。导体垫390可类似于前文参考图9所讨论的导体垫290。导体垫390亦可用来提供到达互连结构320的电性连接,并反过来提供到达裸片300的装置或构件的其余部分(例如电路系统315)的电性连接。
裸片300亦可包括嵌于其中的一超高密度金属─绝缘体─金属电容器395。例如,可使用类似于前文参考图1至图9所讨论的工艺流程来制造超高密度金属─绝缘体─金属电容器395。超高密度金属─绝缘体─金属电容器395可包括多个金属片(举例来说,对应于图9的导体层160、210与260的上述区段的金属片),但是为了简化的缘故,在图10中并未将这些金属片分开示出。可将超高密度金属─绝缘体─金属电容器395嵌于类似于前文参考图5至图9所讨论的钝化膜150或270的一钝化膜,其中可将上述钝化膜形成在互连结构320的上方。为了简化的缘故,被超高密度金属─绝缘体─金属电容器395嵌入的上述钝化膜未在此具体讨论。在一个取代的方案,可将超高密度金属─绝缘体─金属电容器395嵌于互连结构320的介电材料340。
现在请参考图11,亦提供一裸片400。在许多方面,裸片400可实质上类似于裸片300。例如,裸片400亦可以是尚未被单片化的一晶片的一部分,并可包括一基底410、电路系统415、一互连结构420(举例来说,包含多个金属线430与一介电层440)、一导体垫490与嵌入的一超高密度金属─绝缘体─金属电容器495,其中基底410类似于裸片300的基底310,电路系统415类似于裸片300的电路系统315,互连结构420类似于裸片300的互连结构320,导体垫490类似于裸片300的导体垫390,嵌入的超高密度金属─绝缘体─金属电容器495类似于裸片300的嵌入的超高密度金属─绝缘体─金属电容器395。亦要了解的是,为了简化的缘故,被超高密度金属─绝缘体─金属电容器495嵌入的钝化膜未在此具体讨论。然而,与裸片300不同的是,裸片400并未包括基底贯穿孔(举例来说,裸片300的基底贯穿孔335)。
现在请参考图12与图13,分别在裸片300的互连结构320的上方与裸片400的互连结构420的上方,形成介电层500与510。在一些实施形态中,介电层500与510可各包括氧化硅材料。介电层500与510的上表面可各自历经一平坦化工艺,例如一化学机械研磨(chemical mechanical polishing;CMP)工艺。其后,可分别在介电层500与510的上方,形成介电层520与530。在一些实施形态中,介电层520与530可包括氧化硅、氮化硅、碳化硅、氮氧化硅(silicon oxynitride)或上述的组合。然后,可以在介电层520与530形成多个连接垫。例如,可以在介电层520形成多个连接垫550,而在介电层530形成多个连接垫560。可通过分别在介电层520与530蚀刻出多个沟槽,后续以例如铜、铝、钛、钴或上述的组合等的一导体材料填入上述沟槽,而形成连接垫550与560。
亦在裸片300形成一基底贯穿孔570,也在裸片400形成一基底贯穿孔580。基底贯穿孔570垂直延伸而穿过介电层500,并电性且物理性耦合于金属线330中的一个与连接垫550中的一个。基底贯穿孔580垂直延伸而穿过介电层510,并电性且物理性耦合于金属线430中的一个与连接垫560中的一个。
现在请参考图14,例如经由一粘着材料,将包含裸片300的上述晶片贴附于一膜框585。然后,上述晶片历经一单片化工艺(singulation process)(举例来说,锯切(sawing)或切割(dicing)),以将多个裸片300彼此分离。换句话说,上述单片化工艺将尚未单片化的晶片变成多个单一的裸片300。类似地,可以将包含裸片400的上述晶片单片化,以形成多个单一的裸片400。
现在请参考图15,将裸片300与裸片400接合在一起。例如,可以将裸片300垂直翻转而接合于裸片400,而使裸片300的连接垫550接合于裸片400的连接垫560。当裸片300与400的横向尺寸不相等时,可以在裸片300的侧面上形成一填隙材料590。换句话说,填隙材料590可填充由裸片300与裸片400之间的尺寸差异所造成的空隙或空间。可以对裸片300施行一研磨或蚀刻工艺,以部分地移除基底310,直到露出基底贯穿孔335。亦可视需求施行另一个平坦化工艺,以使基底310与基底贯穿孔335的暴露的表面平坦化。
现在请参考图16,可以在基底310的上方与基底贯穿孔335的上方形成一介电层600。在一些实施形态中,介电层600可包括一钝化层,例如其可包括一材料,此材料实质上类似于前文讨论的钝化膜150或钝化膜270。可以在介电层600形成一或多个金属线,例如金属线610。亦可将这些金属线610中的一个形成为与基底贯穿孔335电性连接。亦可在介电层600形成多个连接垫620。其后,可以在连接垫620上形成多个导体凸块630(或是,软焊凸块)。在一些实施形态中,导体凸块630可以各包括一金属材料,而得以使其电性接续于裸片300与400的各种构件(举例来说,电路系统315或415或是超高密度金属─绝缘体─金属电容器395或495)。
图17显示包括一超高密度金属─绝缘体─金属电容器的一封装结构的另一个实施形态。为了明确与一致性的缘故,出现在图16与图17的类似元件将会被赋予相同的符号。如图17所示,裸片300包括一钝化膜350,钝化膜350是置于介电层500与互连结构320之间;而裸片400包括一钝化膜450,钝化膜450是置于介电层510与互连结构420之间。钝化膜350与450可类似于前文参考图2至图9所讨论的钝化膜150或270。
超高密度金属─绝缘体─金属电容器495是嵌于钝化膜450中。为了有助于了解超高密度金属─绝缘体─金属电容器495的结构,在图18显示裸片400包含超高密度金属─绝缘体─金属电容器495的部分650的放大的剖面图。超高密度金属─绝缘体─金属电容器495是嵌于钝化膜450中,钝化膜450可包括多层,例如包括一钝化膜层450A与一钝化膜层450B,钝化膜层450B是置于钝化膜层450A的上方。超高密度金属─绝缘体─金属电容器495可以亦包括逐一向上方垂直堆叠的多个导体层(举例来说,多个金属片)。例如,超高密度金属─绝缘体─金属电容器495可包括一导体层700、一导体层710与一导体层720,其中导体层710形成在导体层700的上方,导体层720形成在导体层710的上方。导体层700、710与720可被形成为类似于前文参考图4至图9所讨论的导体层160、210与260。导体层700、710与720亦通过介电层740与750而被彼此电性分离或隔离。例如,介电层740将导体层700与导体层710彼此分离,而介电层750则将导体层710与导体层720彼此分离。介电层740与750可被形成为类似于前文参考图4至图9所讨论的介电层200。例如,介电层740与750可各自包含一高k值介电材料。
要注意的是,在示于图18的实施形态中,导体层710是部分地形成在导体层700的上方。例如,导体层710的一个区段是形成在导体层700的一“左”部的上方,而导体层710的另一个区段则是形成在导体层700的一“右”部的上方。导体层710的这二个区段也通过例如介电层740与750而被彼此电性隔离。还有,可将导体层720形成在导体层710的这二个区段之间。
如图18所示,超高密度金属─绝缘体─金属电容器495的导体层700与720各自电性连接于一导体垫491(举例来说,经由其侧表面),导体垫491垂直延伸而穿过钝化膜450。如此,导体垫491可用来提供一电性连接而到达超高密度金属─绝缘体─金属电容器495的一个电极——包含于导体层700与720的电极而作为其金属片。同时,超高密度金属─绝缘体─金属电容器495的导体层710的“左”区段是电性连接于一导体垫490(举例来说,经由其侧表面),导体垫490垂直延伸而穿过钝化膜450。如此,导体垫490可用来提供一电性连接而到达超高密度金属─绝缘体─金属电容器495的其他电极——包含于导体层710的电极而作为其金属片。在这个类型,超高密度金属─绝缘体─金属电容器495可包括多个金属层或片(举例来说,超过二个),其中上述金属层的一第一子集(举例来说,导体层700与720)是用来形成一个电极,而上述金属层的一第二子集(举例来说,导体层710)是用来形成另一个电极。在一些实施形态中,如用于图18的实施形态的例子,上述金属层的上述第一子集与上述第二字集互为零交集。也要了解的是,类似于超高密度金属─绝缘体─金属电容器495的其他的超高密度金属─绝缘体─金属电容器可被形成来嵌于钝化膜450。例如,可将一或多个额外的超高密度金属─绝缘体─金属电容器495形成至超高密度金属─绝缘体─金属电容器495的“左边”或“右边”,而使这些超高密度金属─绝缘体─金属电容器仍然嵌于钝化膜450且电性连接至类似于导体垫490、491的导体垫。然而,为了简化的缘故,这些额外的超高密度金属─绝缘体─金属电容器并未具体示出于此。
图19~图20显示包括一超高密度金属─绝缘体─金属电容器的一封装结构的另一个实施形态。再一次,为了明确与一致性的缘故,在图19~图20中,出现在图17~图18的类似元件将会被赋予相同的符号。现在请参考图19,超高密度金属─绝缘体─金属电容器495是经由另一个基底贯穿孔581而电性耦合于连接垫560中的一个。再一次,在图20显示裸片400包含超高密度金属─绝缘体─金属电容器495的部分650的放大的剖面图。超高密度金属─绝缘体─金属电容器495包括导体层700、710与720作为其金属片。超高密度金属─绝缘体─金属电容器495亦包括介电层740与750作为其介电材料。作为超高密度金属─绝缘体─金属电容器495的一个电极,导体层700与720电性连接于导体垫491。作为超高密度金属─绝缘体─金属电容器495的另一个电极,导体层710是电性连接于基底贯穿孔581。由于基底贯穿孔581是电性连接于连接垫560,连接垫560亦用来获得到达超高密度金属─绝缘体─金属电容器495的电性接续。换句话说,导体垫491与基底贯穿孔581可各自作为超高密度金属─绝缘体─金属电容器495的一控制端子。再一次,要了解的是,类似于超高密度金属─绝缘体─金属电容器495的其他的超高密度金属─绝缘体─金属电容器(其包括类似于基底贯穿孔581的多个基底贯穿孔)可被形成来嵌于钝化膜450。例如,可将一或多个额外的超高密度金属─绝缘体─金属电容器495形成至超高密度金属─绝缘体─金属电容器495的“左边”或“右边”,而使这些超高密度金属─绝缘体─金属电容器仍然嵌于钝化膜450且电性连接至类似于导体垫490、491的导体垫。然而,为了简化的缘故,这些额外的超高密度金属─绝缘体─金属电容器并未具体示出于此。
与示于图17~图18的实施形态比较,示于图19~图20的实施形态提供了控制端子面积的减少。这是因为基底贯穿孔581(作为用于超高密度金属─绝缘体─金属电容器495的一控制端子)可以明显地小于导体垫490,导体垫490在示于图18的实施形态是用来作为用于超高密度金属─绝缘体─金属电容器495的一控制端子。在控制端子面积的减少可增加芯片占用面积(chip estate)的效率及/或有助于减少整体封装结构的尺寸,而较佳。
图21~图22显示包括一超高密度金属─绝缘体─金属电容器的一封装结构的又另一个实施形态。再一次,为了明确与一致性的缘故,在图21~图22中,出现在图17~图18的类似元件将会被赋予相同的符号。现在请参考图21,裸片300包括超高密度金属─绝缘体─金属电容器395,而裸片400则包括超高密度金属─绝缘体─金属电容器495。超高密度金属─绝缘体─金属电容器395是嵌于钝化膜350内并经由一基底贯穿孔571而电性耦合于连接垫550中的一个,而超高密度金属─绝缘体─金属电容器495则经由基底贯穿孔581而电性耦合于连接垫560中的一个。由于连接垫550与560是接合在一起,超高密度金属─绝缘体─金属电容器395与495是以并联的方式电性耦合在一起。
超高密度金属─绝缘体─金属电容器395与超高密度金属─绝缘体─金属电容器495之间的并联是更详细地示出于图22,图22是裸片300与400的一部分650的一放大视图。在裸片400的超高密度金属─绝缘体─金属电容器495的排列可以是实质上类似于示于图20的实施形态。在裸片300的超高密度金属─绝缘体─金属电容器395的排列可以是在裸片400的超高密度金属─绝缘体─金属电容器495的排列的实质上的镜像。例如,超高密度金属─绝缘体─金属电容器395是嵌于钝化膜350,其中钝化膜350可包括复数层,例如一钝化膜层350A与一钝化膜层350B。超高密度金属─绝缘体─金属电容器395可以亦包括超过二个导体层(举例来说,金属片),例如分别类似于导体层700、710与720的导体层800、810与820。通过分别类似于介电层740与750的介电层840与850,亦将导体层800、810与820彼此电性分离或隔离。
作为超高密度金属─绝缘体─金属电容器395的一个电极,导体层800与820是电性连接于导体垫391。作为超高密度金属─绝缘体─金属电容器395的其他电极,导体层810是电性连接于基底贯穿孔571。由于基底贯穿孔571是连接于导体垫550且基底贯穿孔581是连接于导体垫560而且导体垫550与560是接合在一起,导体层810与710亦是电性耦合在一起。如此,超高密度金属─绝缘体─金属电容器395与超高密度金属─绝缘体─金属电容器495是以并联的方式电性耦合在一起。
通过超高密度金属─绝缘体─金属电容器395与495的并联耦合而提供的一项效益是电容值的增加。例如,若是超高密度金属─绝缘体─金属电容器395与495各提供C1的电容值,然后通过并联耦合的超高密度金属─绝缘体─金属电容器395与495提供的合计电容值为约C2=2*C1。要注意的是,上述合计电容值C2并不限于2*C1,而可通过调整超高密度金属─绝缘体─金属电容器395的电容值或超高密度金属─绝缘体─金属电容器495的电容值而弹性调配。再一次,要了解的是,类似于超高密度金属─绝缘体─金属电容器495的其他的超高密度金属─绝缘体─金属电容器(其包括类似于基底贯穿孔571与581的多个基底贯穿孔)可被形成来嵌于钝化膜450。例如,可将一或多个额外的超高密度金属─绝缘体─金属电容器495形成至超高密度金属─绝缘体─金属电容器495的“左边”或“右边”,而使这些超高密度金属─绝缘体─金属电容器仍然嵌于钝化膜450且电性连接至类似于导体垫490与基底贯穿孔571及581的导体结构。然而,为了简化的缘故,这些额外的超高密度金属─绝缘体─金属电容器并未具体示出于此。
图23显示包括一超高密度金属─绝缘体─金属电容器的一封装结构的又另一个实施形态。再一次,为了明确与一致性的缘故,在图23中,出现在图17~图22的类似元件将会被赋予相同的符号。示于图23的实施形态与示于图17~图22的实施形态之间的一项不同点是超高密度金属─绝缘体─金属电容器895是装置在介电层600而不是在钝化膜350或450。在形成于介电层600的上方或下方的一钝化膜,亦可形成超高密度金属─绝缘体─金属电容器895。这样的钝化膜可以类似于钝化膜350或450,并可包括多个钝化膜层。超高密度金属─绝缘体─金属电容器895的导体层与介电层的配置可实质上类似于示于图18的超高密度金属─绝缘体─金属电容器495。在一些实施形态中,超高密度金属─绝缘体─金属电容器895的至少一个电极可以电性耦合于导体凸块630中的至少一个。因此,导体凸块630亦可以作为超高密度金属─绝缘体─金属电容器895的控制端子。
图24是一流程图,显示根据本发明实施例的一实施形态的一方法1000。方法1000包括一步骤1010,步骤1010提供一第一裸片,其包括一第一基底与形成在上述第一基底上方的一第一互连结构。在一些实施形态中,提供上述第一裸片包括提供包含上述第一裸片的一第一晶片。
方法1000包括一步骤1020,步骤1020是在上述第一互连结构的上方形成一第一介电层。
方法1000包括一步骤1030,步骤1030是在上述第一介电层的上方形成一或多个第一接合垫。
方法1000包括一步骤1040,步骤1040提供一第二裸片,其包括一第二基底与形成在上述第二基底上方的一第二互连结构。在一些实施形态中,提供上述第二裸片包括提供包含上述第二裸片的一第二晶片。
方法1000包括一步骤1050,步骤1050是在上述第二互连结构的上方形成一第二介电层。
方法1000包括一步骤1060,步骤1060是在上述第二介电层的上方形成一或多个第二接合垫。
方法1000包括一步骤1070,步骤1070是将上述一或多个第一接合垫接合于上述一或多个第二接合垫。
上述第一裸片与上述第二裸片的至少一个包括嵌于其中的一金属─绝缘体─金属电容器。在一些实施形态中,上述金属─绝缘体─金属电容器包括一第一导体层、一第一介电材料、一第二导体层、一第二介电材料及一第三导体层,上述第一介电材料置于上述第一导体层的上方,上述第二导体层置于上述第一介电材料的上方,上述第二介电材料置于上述第二导体层的上方,上述第三导体层置于上述第二介电材料的上方。
要了解的是,可以在方法1000的步骤1010、1020、1030、1040、1050、1060、1070之前、过程中或之后施行额外的工艺。例如,方法1000可包括在上述第一裸片或上述第二裸片形成上述金属─绝缘体─金属电容器的一步骤。作为另一个例子,方法1000可包括:将上述第一导体层与上述第三导体层,与上述第一裸片或上述第二裸片的一第一导体构件电性耦合的步骤;以及将上述第二导体层,与上述第一裸片或上述第二裸片的一第二导体构件电性耦合的步骤。上述第二导体构件不同于上述第一导体构件。作为又另一个例子,方法100可包括:在上述第一裸片形成一第一金属─绝缘体─金属电容器的步骤并在上述第二裸片形成一第二金属─绝缘体─金属电容器的步骤;以及以并联的形式将上述第一金属─绝缘体─金属电容器与上述第二金属─绝缘体─金属电容器电性耦合在一起的步骤。作为又一个例子,在接合的步骤1070之前,方法1000包括将上述第一晶片单片化与将上述第二晶片单片化的步骤。为了简化的缘故,在此不详细讨论其他额外步骤。
综上所述,本发明实施例包括一封装结构,其中将一超高密度金属─绝缘体─金属电容器嵌于三次元集成电路结构。例如,上述三次元集成电路结构包括接合在一起的二个裸片,其中一基底贯穿孔可用来提供上述二个已接合的裸片的构件之间的电性连接。上述超高密度金属─绝缘体─金属电容器可嵌于上述已接合的裸片中的任一个或二者。在一些实施形态中,上述超高密度金属─绝缘体─金属电容器可嵌于上述已接合的裸片的二者且可以以并联的形式电性耦合在一起。在其他实施例中,上述超高密度金属─绝缘体─金属电容器可嵌于上述导体凸块下(或是另外邻接于上述导电凸块)的一介电层。
基于以上的讨论,可了解本发明实施例提供了超越传统的鳍式场效晶体管的优点。然而,要了解的是,其他实施形态可提供额外的优点,且并非所有的优点都需要在此公开,且没有所有实施例都需要的特定优点。一项优点是,上述超高密度金属─绝缘体─金属电容器提供在调整一所需的电容值时的弹性,由于其多片多个介电层可获得额外的电容值调整参数(或是自由度)。另一个优点是将上述超高密度金属─绝缘体─金属电容器嵌于一钝化层,是意味着不需要额外的芯片的实际占用面积(chip real estate)。又另一个优点是,由于一超高密度金属─绝缘体─金属电容器可装置在每一个已接合的裸片,而可达成电容值的增加。又另一个优点是,上述裸片的不同种类的导体构件,例如连接垫、基底贯穿孔、金属线等等,都可以用来作为上述超高密度金属─绝缘体─金属电容器的控制端子,在此处可达成超高密度金属─绝缘体─金属电容器的简单的电性接续。其他优点包括与现有的制造及/或封装的工艺相容,而使本发明实施例不需要额外的加工且因此可容易且便宜地设置。
关于一些实施例,是提供一种集成电路装置,其包括一第一裸片与一第二裸片。上述第一裸片包括一第一基底、一第一互连结构、一第一介电层及多个第一连接垫。上述第一基底包含第一电路系统,上述第一互连结构置于上述第一基底的上方,上述第一介电层置于上述第一互连结构的上方,上述第一连接垫置于上述第一介电层的上方。上述第二裸片包括一第二基底、一第二互连结构、一第二介电层及多个第二连接垫。上述第二基底包含第二电路系统,上述第二互连结构置于上述第二基底的上方,上述第二介电层置于上述第二互连结构的上方,上述第二连接垫置于上述第二介电层的上方。上述第一裸片的上述第一连接垫连接于上述第二裸片的上述第二连接垫,上述第一裸片与上述第二裸片的至少一个包括一金属─绝缘体─金属(metal-insulator-metal;MIM)电容器,上述金属─绝缘体─金属电容器包括逐一向上方堆叠的超过两层的金属层。
在一实施例中,上述第一介电层或上述第二介电层包括一钝化层,上述金属─绝缘体─金属电容器是嵌于上述钝化层中。
在一实施例中,上述金属─绝缘体─金属电容器包括一第一金属层、一第一介电材料、一第二金属层、一第二介电材料及一第三金属层,上述第一介电材料置于上述第一金属层的上方,上述第二金属层置于上述第一介电材料的上方,上述第二介电材料置于上述第二金属层的上方,上述第三金属层置于上述第二介电材料的上方。
在一实施例中,上述第二金属层置于上述第一金属层的一部分的上方,但非上述第一金属层的全部的上方。
在一实施例中,上述第一裸片或上述第二裸片包括一第一导体垫与一第二导体垫,上述金属─绝缘体─金属电容器的上述第一金属层与上述第三金属层均电性耦合于上述第一导体垫,上述金属─绝缘体─金属电容器的上述第二金属层电性耦合于上述第二导体垫。
在一实施例中,上述第一裸片或上述第二裸片包括一导体垫与一基底贯穿导孔(through substrate via;TSV),上述金属─绝缘体─金属电容器的上述第一金属层与上述第三金属层均电性耦合于上述导体垫,上述金属─绝缘体─金属电容器的上述第二金属层电性耦合于上述基底贯穿导孔。
在一实施例中,上述金属─绝缘体─金属电容器是嵌于上述第一裸片的一第一金属─绝缘体─金属电容器,上述第二裸片包括一第二金属─绝缘体─金属电容器。在本实施例中,上述第二金属─绝缘体─金属电容器包括一第四金属层、一第五金属层及一第六金属层,上述第五金属层置于上述第四金属层的上方,上述第六金属层置于上述第五金属层的上方。在本实施例中,上述第一金属─绝缘体─金属电容器与上述第二金属─绝缘体─金属电容器是以并联的方式电性耦合。
在一实施例中,上述第一裸片还包括一第一导体垫与一第一基底贯穿导孔(through substrate via;TSV),上述第二裸片还包括一第二导体垫与一第二基底贯穿导孔,上述第一金属─绝缘体─金属电容器的上述第一金属层与上述第三金属层均电性耦合于上述第一导体垫,上述第一金属─绝缘体─金属电容器的上述第二金属层电性耦合于上述第一基底贯穿导孔,上述第二金属─绝缘体─金属电容器的上述第四金属层与上述第六金属层均电性耦合于上述第二导体垫,上述第一金属─绝缘体─金属电容器的上述第五金属层电性耦合于上述第二基底贯穿导孔,上述第一基底贯穿导孔与上述第二基底贯穿导孔电性耦合在一起。
在一实施例中,上述集成电路装置还包括一第三介电层与多个导体凸块。在本实施例中,上述第三介电层置于上述第一基底的上方,上述第一互连结构置于上述第一基底的两侧。在本实施例中,上述多个导体凸块置于上述第三介电层的上方。在本实施例中,上述金属─绝缘体─金属电容器嵌于上述第三介电层中。
关于一些实施例,是提供一种集成电路装置,其包括一第一裸片、一第二裸片与一电容器。上述第一裸片与上述第二裸片经由多个连接垫而连接在一起,上述电容器嵌于上述第一裸片与上述第二裸片的至少一个。上述电容器包括超过二个金属层,上述金属层的一第一子集是电性且物理性连接于一第一导体构件,上述金属层的一第二子集是电性且物理性连接于一第二导体构件,上述第二导体构件不同于上述第一导体构件。
在一实施例中,上述第一导体构件与上述第二导体构件的至少一个包括一导体垫。
在一实施例中,上述第一导体构件与上述第二导体构件的至少一个包括一基底贯穿导孔(through substrate via;TSV)。
在一实施例中,上述电容器是嵌于上述第一裸片的一钝化层或上述第二裸片的一钝化层。
在一实施例中,上述金属层的上述第一子集与上述第二子集互为零交集。
在一实施例中,上述电容器是嵌于上述第一裸片的一第一电容器。在本实施例中,上述集成电路装置还包括一第二电容器,上述第二电容器嵌于上述第二裸片。在本实施例中,上述第一电容器与上述第二电容器是以并联的方式电性耦合。
关于一些实施例,是提供一种集成电路装置的形成方法,其包括:提供一第一裸片,上述第一裸片包括一第一基底与一第一互连结构,上述第一互连结构形成在上述第一基底的上方;在上述第一互连结构形成一第一介电层;在上述第一介电层的上方形成一或多个第一连接垫;提供一第二裸片,上述第二裸片包括一第二基底与一第二互连结构,上述第二互连结构形成在上述第二基底的上方;在上述第二互连结构形成一第二介电层;在上述第二介电层的上方形成一或多个第二连接垫;以及将上述一或多个第一连接垫连接于上述一或多个第二连接垫。上述第一裸片与上述第二裸片的至少一个包括嵌于其中的一金属─绝缘体─金属(metal-insulator-metal;MIM)电容器。
在一实施例中,上述集成电路装置的形成方法还包括将上述金属─绝缘体─金属电容器形成在上述第一裸片或上述第二裸片。在本实施例中,上述金属─绝缘体─金属电容器包括一第一导体层、一第一介电材料、一第二导体层、一第二介电材料及一第三导体层,上述第一介电材料形成在上述第一导体层的上方,上述第二导体层形成在上述第一介电材料的上方,上述第二介电材料形成在上述第二导体层的上方,上述第三导体层形成在上述第二介电材料的上方。
在一实施例中,上述集成电路装置的形成方法还包括:以上述第一裸片或上述第二裸片的一第一导体构件电性耦合上述第一导体层与上述第三导体层;以及以上述第一裸片或上述第二裸片的一第二导体构件电性耦合上述第二导体层。在本实施例中,上述第二导体层不同于上述第一导体层。
在一实施例中,上述集成电路装置的形成方法还包括在上述第一裸片形成一第一金属─绝缘体─金属电容器,在上述第二裸片形成一第二金属─绝缘体─金属电容器;以及将上述第一电容器与上述第二电容器以并联的方式电性耦合。
在一实施例中,上述第一裸片的提供包括提供包含上述第一裸片的一第一晶片,上述第二裸片的提供包括提供包含上述第二裸片的一第二晶片。在本实施例中,上述集成电路装置的形成方法还包括在接合之前,将上述第一晶片单片化以及将上述第二晶片单片化。
前述内文概述了许多实施例的特征,使所属技术领域中技术人员可以从各个方面更佳地了解本发明实施例。所属技术领域中技术人员应可理解,且可轻易地以本发明实施例为基础来设计或修饰其他工艺及结构,并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。所属技术领域中技术人员也应了解这些均等的结构并未背离本发明实施例的发明精神与范围。在不背离本发明实施例的发明精神与范围的前提下,可对本发明实施例进行各种改变、置换或修改。
Claims (1)
1.一种集成电路装置,包括:
一第一裸片,其包括一第一基底、一第一互连结构、一第一介电层及多个第一连接垫,该第一基底包含第一电路系统,该第一互连结构置于该第一基底的上方,该第一介电层置于该第一互连结构的上方,多个所述第一连接垫置于该第一介电层的上方;以及
一第二裸片,其包括一第二基底、一第二互连结构、一第二介电层及多个第二连接垫,该第二基底包含第二电路系统,该第二互连结构置于该第二基底的上方,该第二介电层置于该第二互连结构的上方,多个所述第二连接垫置于该第二介电层的上方;其中
该第一裸片的多个所述第一连接垫连接于该第二裸片的多个所述第二连接垫;
该第一裸片与该第二裸片的至少一个包括一金属─绝缘体─金属电容器;以及
该金属─绝缘体─金属电容器包括逐一向上方堆叠的超过两层的金属层。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/697,797 | 2019-11-27 | ||
US16/697,797 US11133304B2 (en) | 2019-11-27 | 2019-11-27 | Packaging scheme involving metal-insulator-metal capacitor |
Publications (1)
Publication Number | Publication Date |
---|---|
CN112864145A true CN112864145A (zh) | 2021-05-28 |
Family
ID=75975056
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202011263779.8A Pending CN112864145A (zh) | 2019-11-27 | 2020-11-12 | 集成电路装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11133304B2 (zh) |
CN (1) | CN112864145A (zh) |
TW (1) | TW202133455A (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109285825B (zh) * | 2017-07-21 | 2021-02-05 | 联华电子股份有限公司 | 芯片堆叠结构及管芯堆叠结构的制造方法 |
US11437344B2 (en) * | 2020-03-27 | 2022-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wafer bonding method |
US11594506B2 (en) * | 2020-09-23 | 2023-02-28 | Advanced Semiconductor Engineering, Inc. | Semiconductor package |
US11699629B2 (en) * | 2021-03-26 | 2023-07-11 | Qorvo Us, Inc. | Integrated circuit die stacked with backer die including capacitors and thermal vias |
US11626366B2 (en) * | 2021-06-22 | 2023-04-11 | Silicon Laboratories Inc. | Shielding using layers with staggered trenches |
US11854928B2 (en) * | 2021-08-27 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and manufacturing method thereof |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7564115B2 (en) | 2007-05-16 | 2009-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tapered through-silicon via structure |
US7973413B2 (en) | 2007-08-24 | 2011-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate via for semiconductor device |
US8227902B2 (en) | 2007-11-26 | 2012-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structures for preventing cross-talk between through-silicon vias and integrated circuits |
US7843064B2 (en) | 2007-12-21 | 2010-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and process for the formation of TSVs |
US8278152B2 (en) | 2008-09-08 | 2012-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding process for CMOS image sensor |
US7825024B2 (en) | 2008-11-25 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming through-silicon vias |
US8158456B2 (en) | 2008-12-05 | 2012-04-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming stacked dies |
US8183579B2 (en) | 2010-03-02 | 2012-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | LED flip-chip package structure with dummy bumps |
US8183578B2 (en) | 2010-03-02 | 2012-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double flip-chip LED package components |
US8426961B2 (en) | 2010-06-25 | 2013-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded 3D interposer structure |
US8581418B2 (en) | 2010-07-21 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-die stacking using bumps with different sizes |
US8105875B1 (en) | 2010-10-14 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Approach for bonding dies onto interposers |
US8803316B2 (en) | 2011-12-06 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSV structures and methods for forming the same |
US8803292B2 (en) | 2012-04-27 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias and methods for forming the same |
US9443783B2 (en) | 2012-06-27 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC stacking device and method of manufacture |
US8912844B2 (en) * | 2012-10-09 | 2014-12-16 | United Microelectronics Corp. | Semiconductor structure and method for reducing noise therein |
US8802504B1 (en) | 2013-03-14 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US8993380B2 (en) | 2013-03-08 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D IC package |
JPWO2014184988A1 (ja) * | 2013-05-16 | 2017-02-23 | パナソニックIpマネジメント株式会社 | 半導体装置及びその製造方法 |
KR20150042612A (ko) * | 2013-10-11 | 2015-04-21 | 삼성전자주식회사 | 디커플링 캐패시터를 갖는 반도체 소자 및 그 형성 방법 |
JP6295863B2 (ja) * | 2014-07-16 | 2018-03-20 | 富士通株式会社 | 電子部品、電子装置及び電子装置の製造方法 |
US10811388B2 (en) * | 2015-09-28 | 2020-10-20 | Invensas Corporation | Capacitive coupling in a direct-bonded interface for microelectronic devices |
US10141392B2 (en) * | 2017-02-23 | 2018-11-27 | International Business Machines Corporation | Microstructure modulation for 3D bonded semiconductor structure with an embedded capacitor |
US10276651B2 (en) * | 2017-09-01 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low warpage high density trench capacitor |
US11120941B2 (en) * | 2018-01-24 | 2021-09-14 | Semiconductor Components Industries, Llc | Methods of forming capacitors |
US11195805B2 (en) * | 2018-03-30 | 2021-12-07 | Intel Corporation | Capacitor die embedded in package substrate for providing capacitance to surface mounted die |
US10796990B2 (en) * | 2018-09-19 | 2020-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure, package structure, and manufacturing method thereof |
-
2019
- 2019-11-27 US US16/697,797 patent/US11133304B2/en active Active
-
2020
- 2020-10-19 TW TW109136080A patent/TW202133455A/zh unknown
- 2020-11-12 CN CN202011263779.8A patent/CN112864145A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
US20210159224A1 (en) | 2021-05-27 |
US11133304B2 (en) | 2021-09-28 |
TW202133455A (zh) | 2021-09-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11296011B2 (en) | Through-substrate vias with improved connections | |
KR102404490B1 (ko) | 후면 커패시터 기법 | |
CN112864145A (zh) | 集成电路装置 | |
US9984971B2 (en) | Methods of forming metal pad structures over TSVS to reduce shorting of upper metal layers | |
JP5246831B2 (ja) | 電子デバイス及びそれを形成する方法 | |
US7943473B2 (en) | Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme | |
TW201539696A (zh) | 半導體裝置及半導體裝置製造方法 | |
CN113053855A (zh) | 半导体结构和集成电路以及用于形成三维沟槽电容器的方法 | |
US9978637B2 (en) | Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs) | |
JP2010530128A (ja) | 超高密度のキャパシタ及び基板貫通ビアを有する集積基板 | |
US10141394B2 (en) | Integrated circuit comprising a metal-insulator-metal capacitor and fabrication method thereof | |
TWI812168B (zh) | 三維元件結構及其形成方法 | |
CN112447664A (zh) | 封装 | |
US8907459B2 (en) | Three-dimensional semiconductor integrated circuit device and method of fabricating the same | |
TW202310186A (zh) | 三維裝置結構 | |
Detalle et al. | Interposer technology for high band width interconnect applications | |
US10439021B2 (en) | Capacitor structure | |
CN112956023B (zh) | 倒装芯片堆叠结构及其形成方法 | |
US20220173077A1 (en) | Stacked die structure and method of fabricating the same | |
US20140147984A1 (en) | Semiconductor device and method of fabricating through silicon via structure | |
CN113644039A (zh) | 半导体结构及其形成方法 | |
US20230163087A1 (en) | Semiconductor package | |
US20240162035A1 (en) | Multilayer stacking wafer bonding structure and method of manufacturing the same | |
US20220367364A1 (en) | Semiconductor device and method for fabricating the same | |
CN115775773A (zh) | 半导体封装 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20210528 |