CN112447664A - 封装 - Google Patents

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Publication number
CN112447664A
CN112447664A CN202010304236.XA CN202010304236A CN112447664A CN 112447664 A CN112447664 A CN 112447664A CN 202010304236 A CN202010304236 A CN 202010304236A CN 112447664 A CN112447664 A CN 112447664A
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China
Prior art keywords
die
layer
bonding
tiv
encapsulant
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Pending
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CN202010304236.XA
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English (en)
Inventor
陈明发
叶松峯
洪建玮
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN112447664A publication Critical patent/CN112447664A/zh
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Abstract

一种封装包括半导体载板、第一管芯、第二管芯、第一包封体、第二包封体、第一绝缘层穿孔(TIV)以及第二绝缘层穿孔。半导体载板具有嵌置在其中的接触通孔。接触通孔被电接地。第一管芯设置在半导体载板上。第二管芯堆叠在第一管芯上。第一包封体在侧向上包封第一管芯。第二包封体在侧向上包封第二管芯。第一TIV位于第一管芯旁。第一TIV穿透过第一包封体且电连接到接触通孔。第二TIV位于第二管芯旁。第二TIV穿透过第二包封体且电连接到接触通孔及第一TIV。

Description

封装
技术领域
本发明实施例涉及一种封装。更具体来说，本发明实施例涉及一种在载板内具有接触通孔的封装。
背景技术
各种电子装置(例如，手机及其他移动电子设备)中所使用的半导体装置及集成电路通常是在单个半导体晶片(semiconductor wafer)上制造。晶片的管芯可以晶片级(wafer level)来与其他半导体装置或管芯一起进行处理及封装，且已针对晶片级封装(wafer level packaging)开发了各种技术及应用。多个半导体装置的集成已成为此领域中的挑战。
发明内容
一种封装包括半导体载板、第一管芯、第二管芯、第一包封体、第二包封体、第一绝缘层穿孔(through insulating via，TIV)及第二TIV。所述半导体载板具有嵌置在其中的接触通孔。所述接触通孔被电接地。所述第一管芯设置在所述半导体载板上。所述第二管芯堆叠在所述第一管芯上。所述第一包封体在侧向上包封所述第一管芯。所述第二包封体在侧向上包封所述第二管芯。所述第一TIV位于所述第一管芯旁。所述第一TIV穿透过所述第一包封体且电连接到所述接触通孔。所述第二TIV位于所述第二管芯旁。所述第二TIV穿透过所述第二包封体且电连接到所述接触通孔及所述第一TIV。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为使论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A到图1P是根据本公开的一些实施例的封装的制造工艺的示意性剖视图。
图2是根据本公开的一些替代实施例的封装的示意性剖视图。
图3A到图3B是根据本公开的一些替代实施例的封装的制造工艺的示意性剖视图。
图4A到图4H是根据本公开的一些替代实施例的封装的制造工艺的示意性剖视图。
图5是根据本公开的一些替代实施例的封装的示意性剖视图。
附图标号说明
10、20、30、40、50：封装
110：载板
120、132、522、530、702、902、1310：介电层
130、520：对位层
134、524：对位标记
140、300、540、700、900：接合层
200、800：管芯
200a、800a：有源表面
200b、800b、800c、800d：后表面
210、810：半导体衬底
220、820：内连结构
222、822：介电间层
224、824：导电图案
230、830：钝化层
240、840：导电垫
250、860：接合通孔
400、1000：包封体
400’：包封体材料
510：半导体载板
512：接触通孔
600、1100：绝缘层穿孔
704、904：接合垫
706：连接垫
708：辅助连接垫
850：半导体穿孔
850a、1000a、1100a、1500a：顶表面
1200：保护层
1300：重布线结构
1320：重布线导电层
1330：凸块下金属图案
1400：导电端子
1500：辅助绝缘层穿孔
DR：管芯区
R：凹槽
SR：切割道区
S700、S900：接合表面
ST：薄化平台
W200、W800：宽度
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及布置的具体实例以简化本公开。当然，这些仅为实例而非旨在进行限制。举例来说，以下说明中将第一特征形成在第二特征之上或第二特征上可包括其中第一特征与第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征从而使得所述第一特征与所述第二特征可不直接接触的实施例。另外，本公开可能在各种实例中重复使用参考编号和/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身指示所论述的各种实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在...之下(beneath)”、“在...下方(below)”、“下部的(lower)”、“在...上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括器件在使用或操作中的不同取向。装置可具有其他取向(旋转90度或处于其他取向)，且本文中所使用的空间相对性描述语可同样相应地进行解释。
本公开也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(three-dimensional，3D)封装或三维集成电路(three-dimensional integratedcircuit，3DIC)装置进行验证测试。所述测试结构可包括例如在重布线层中或在衬底上形成的测试垫，以使得能够对3D封装或3DIC进行测试、对探针及/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可与包括对已知良好管芯(known good die)进行中间验证的测试方法一起使用，以提高良率并降低成本。
图1A到图1P是根据本公开的一些实施例的封装10的制造工艺的示意性剖视图。参考图1A，提供载板110。在一些实施例中，载板110包含半导体材料。举例来说，载板110可由以下半导体制成：合适的元素半导体，例如晶体硅、金刚石或锗；合适的化合物半导体，例如砷化镓、碳化硅、砷化铟或磷化铟；或者合适的合金半导体，例如碳化硅锗、磷化镓砷或磷化镓铟。在一些实施例中，载板110不含有源组件及无源组件。在一些实施例中，载板110也不包括布线。举例来说，载板110可为空白衬底(blank substrate)，其仅用作支撑元件，而不提供任何信号传输功能。
如图1A所示，介电层120、对位层130及接合层140依序地设置在载板110上。换句话说，对位层130夹置在介电层120与接合层140之间。在一些实施例中，对位层130包括介电层132及嵌置在介电层132中的多个对位标记134。举例来说，介电层132环绕对位标记134。在一些实施例中，介电层120及介电层132可通过合适的制作技术(例如气相沉积、旋转涂布(spin coating)、原子层沉积(atomic layer deposition，ALD)、热氧化、一些其他合适的沉积或生长工艺、或其组合)形成。气相沉积可包括例如化学气相沉积(chemical vapordeposition，CVD)、物理气相沉积(physical vapor deposition，PVD)、等离子体增强化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)、一些其他合适的气相沉积工艺或其组合。在一些实施例中，介电层120的材料与介电层132的材料可相同。举例来说，介电层120及介电层132可为聚酰亚胺、聚苯并恶唑(polybenzoxazole，PBO)、苯并环丁烯(benzocyclobutene，BCB)、氮化物(例如，氮化硅)、氧化物(例如，氧化硅)、未掺杂的硅酸盐玻璃(undoped silicate glass，USG)、磷硅酸盐玻璃(phosphosilicate glass，PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、硼掺杂的磷硅酸盐玻璃(boron-dopedphosphosilicate glass，BPSG)、其组合等。然而，本公开并不限于此。在一些替代实施例中，介电层120的材料可不同于介电层132的材料。举例来说，介电层120的材料可包括未掺杂的硅酸盐玻璃(USG)，而介电层132的材料可包括氮化物(例如氮化硅)。
在一些实施例中，对位标记134可为图案化铜层(patterned copper layer)或其他合适的图案化金属层。在一些实施例中，对位标记134可通过电镀或沉积形成。应注意的是，对位标记134的形状及数目在本公开中不受限制，且可基于需求及/或设计布局来定。在一些实施例中，介电层132的顶表面实质上与对位标记134的顶表面齐平。在一些实施例中，对位标记134与其他组件电隔离。换句话说，对位标记134是电浮动的(electricallyfloating)。
在一些实施例中，接合层140是具有连续均匀表面的平滑层，且上覆在对位层130上。在一些实施例中，接合层140的材料可包括氮氧化硅(SiON)、氧化硅、氮化硅等。在一些实施例中，接合层140可通过沉积等形成。在一些实施例中，接合层140具有实质上均一且均匀的厚度。
参考图1B，在载板110上放置多个管芯200。在一些实施例中，每一管芯200包括半导体衬底210、内连结构220、钝化层230及导电垫240。在一些实施例中，内连结构220设置在半导体衬底210上。半导体衬底210可由以下半导体制成：合适的元素半导体，例如晶体硅、金刚石或锗；合适的化合物半导体，例如砷化镓、碳化硅、砷化铟或磷化铟；或者合适的合金半导体，例如碳化硅锗、磷化镓砷或磷化镓铟。在一些实施例中，半导体衬底210可包括形成在其中的有源组件(例如，晶体管等)及/或无源组件(例如，电阻器、电容器、电感器等)。
在一些实施例中，内连结构220包括介电间层(inter-dielectric layer)222及嵌置在介电间层222中的多个导电图案224。在一些实施例中，内连结构220的导电图案224电连接到嵌置在半导体衬底210中的有源组件及/或无源组件。在一些实施例中，介电间层222的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、BCB、PBO、其组合或其他合适的介电材料。介电间层222可通过合适的制作技术(例如旋转涂布、叠层(lamination)、CVD等)形成。在一些实施例中，导电图案224的材料包括铝、钛、铜、镍、钨及/或其合金。导电图案224可通过例如电镀、沉积及/或光刻及刻蚀来形成。为了简明起见，在图1B中内连结构220被示出为具有一层介电间层222及一层导电图案224。然而，本公开并不限于此。在一些替代实施例中，介电间层222的层数及导电图案224的层数可根据布线要求来调整。举例来说，可在内连结构220中存在多层介电间层222及多层导电图案224，且导电图案224与介电间层222可交替堆叠。
在一些实施例中，导电垫240设置在内连结构220上。在一些实施例中，导电垫240电连接到内连结构220的导电图案224。在一些实施例中，导电垫240可为铝垫、铜垫或其他合适的金属垫。应注意的是，可基于需求来选择导电垫240的数目及形状。
在一些实施例中，钝化层230形成在内连结构220上以密封导电垫240。在一些实施例中，钝化层230的材料包括氧化物(例如氧化硅)等。作为另外一种选择，钝化层230可包含聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、BCB、PBO或任何其他合适的聚合物系介电材料。钝化层230例如可通过合适的制作技术(例如旋转涂布、CVD、PECVD等)形成。
在一些实施例中，管芯200能够执行逻辑功能。举例来说，管芯200可为中央处理器(Central Process Unit，CPU)管芯、图形处理单元(Graphic Process Unit，GPU)管芯、现场可编程门阵列(Field-Programmable Gate Array，FPGA)等。
在一些实施例中，每一管芯200具有有源表面200a及与有源表面200a相对的后表面200b。在一些实施例中，在放置管芯200之前，在每一管芯200的有源表面200a上形成接合层300。举例来说，接合层300形成在管芯200的钝化层230上。在一些实施例中，接合层300是具有连续均匀表面的平滑层。在一些实施例中，接合层300的材料可包括氮氧化硅(SiON)、氧化硅、氮化硅等。在一些实施例中，接合层300可通过沉积等形成。
在一些实施例中，上面形成有接合层300的管芯200被拾取并放置(picked-and-placed)在接合层140上，使得接合层300通过熔融接合(fusion bonding)粘附到接合层140。熔融接合工艺可包括亲水性熔融接合工艺(hydrophilic fusion bonding process)，其中可用的工作温度约大于或实质上等于约100℃，且可用的工作压力约大于或实质上等于约1kg/cm2。在一些实施例中，熔融接合工艺不涉及金属对金属接合。如图1B所示，管芯200以面朝下的方式接合到载板110。也就是说，管芯200的有源表面200a面向载板110。在一些实施例中，管芯200以阵列方式排列。在一些实施例中，借助对位标记143，可有效地提高管芯200的放置精度。
参考图1C，在接合层140上形成包封体材料400’，以共形地覆盖管芯200。在一些实施例中，包封体材料400’包括模制化合物或聚合材料(例如聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、BCB、PBO、其组合或其他合适的聚合物系介电材料)。在一些替代实施例中，包封体材料400’可包括氧化硅及/或氮化硅。在一些实施例中，包封体材料400’还包括填料(filler)。作为另外一种选择，包封体材料400’可不含填料。在一些实施例中，包封体材料400’可通过模制工艺(例如压缩模制工艺(compression molding process))、旋转涂布工艺、CVD工艺、PECVD工艺、ALD工艺等形成。如图1C所示，管芯200并未被显露出且被包封体材料400’良好地保护住。
参考图1C及图1D，对包封体材料400’进行薄化以形成包封体400。也就是说，对包封体材料400’进行薄化直到暴露出管芯200的半导体衬底210。在一些实施例中，在半导体衬底210被显露出之后，可进一步对半导体衬底210及包封体400进行薄化以减小管芯200的总厚度。在一些实施例中，可通过研磨工艺(例如机械研磨工艺(mechanical grindingprocess)、化学机械抛光(chemical mechanical polishing，CMP)工艺等)对包封体材料400’及半导体衬底210进行薄化或平坦化。在一些实施例中，包封体400在侧向上包封管芯200及接合层300。也就是说，管芯200的后表面200b实质上与包封体400的顶表面共面。在一些实施例中，包封体400覆盖管芯200的侧壁及接合层300的侧壁。在一些实施例中，包封体400可被称为“间隙填充氧化物(gap fill oxide)”。
参考图1E，管芯200及包封体400被贴合到半导体载板510。举例来说，在管芯200的后表面200b及包封体400上依序地形成接合层540、介电层530、对位层520及半导体载板510。在一些实施例中，接合层540是具有连续均匀表面的平滑层，且上覆在管芯200及包封体400上。在一些实施例中，接合层540的材料可包括氮氧化硅(SiON)、氧化硅、氮化硅等。在一些实施例中，接合层540可通过沉积等形成。在一些实施例中，接合层540具有实质上均一且均匀的厚度。
在一些实施例中，介电层530位于对位层520与包封体400之间。举例来说，介电层530夹置在对位层520与接合层540之间。在一些实施例中，介电层530可通过合适的制作技术(例如气相沉积、旋转涂布、ALD、热氧化、一些其它合适的沉积或生长工艺或其组合)形成。气相沉积可包括例如CVD、PVD、PECVD、一些其他合适的气相沉积工艺或其组合。在一些实施例中，介电层530可为聚酰亚胺、PBO、BCB、氮化物(例如氮化硅)、氧化物(例如氧化硅)、USG、PSG、BSG、BPSG、其组合等。
如图1E所示，对位层520位于半导体载板510与管芯200之间以及半导体载板510与包封体400之间。在一些实施例中，对位层520包括介电层522及嵌置在介电层522中的多个对位标记524。举例来说，介电层522环绕对位标记524。对位层520的介电层522及对位标记524分别类似于对位层130的介电层132及对位标记134，因此在此不再对其予以赘述。在一些实施例中，介电层522的顶表面实质上与对位标记524的顶表面齐平。类似地，介电层522的底表面也实质上与对位标记524的底表面齐平。
在一些实施例中，半导体衬底510设置在对位层520上。在一些实施例中，半导体载板510可由以下半导体制成：合适的元素半导体，例如晶体硅、金刚石或锗；合适的化合物半导体，例如砷化镓、碳化硅、砷化铟或磷化铟；或者合适的合金半导体，例如碳化硅锗、磷化镓砷或磷化镓铟。在一些实施例中，半导体载板510不含有源组件及无源组件。在一些实施例中，半导体载板510具有多个管芯区DR及多个切割道区SR。每一切割道区SR位于两个相邻的管芯区DR之间。为了简明起见，图1E中示出两个管芯区DR及一个切割道区SR。在一些实施例中，借助对位标记134及对位标记524，可有效地提高半导体衬底510的接合精度。
在一些实施例中，多个接触通孔512嵌置在半导体载板510中。在一些实施例中，接触通孔512由金属制成。举例来说，接触通孔512可包括铝、钛、铜、镍、钨及/或其合金。如图1E所示，接触通孔512位于管芯区DR中。在一些实施例中，接触通孔512的底表面与半导体载板510的底表面共面。然而，本公开并不限于此。在一些替代实施例中，接合层(未示出)可可选地存在于半导体载板510与对位层520之间，以进一步增强这两个元件之间的接合。当存在这种接合层时，接触通孔512穿透过接合层。也就是说，接触通孔512的底表面与接合层的底表面共面。在一些实施例中，接触通孔512被电接地。举例来说，接触通孔512电连接到地电压(ground voltage)。在一些实施例中，接触通孔512直接接触半导体载板510。举例来说，接触通孔512的侧壁及顶表面直接接触半导体载板510。
如图1E所示，接触通孔512的底表面直接接触一些对位标记524。在一些实施例中，一些对位标记524电连接到接触通孔512。举例来说，一些对位标记524通过接触通孔512被电接地。另一方面，其余的对位标记524是电浮动的。在一些实施例中，对位标记524及管芯200也位于管芯区DR内。
参考图1E及图1F，从包封体400及接合层300移除载板110、介电层120、对位层130及接合层140。举例来说，如图1F所示，包封体400及接合层300被暴露出。在一些实施例中，通过平坦化工艺、刻蚀工艺、剥除工艺、相似工艺或其组合来移除载板110、介电层120、对位层130及接合层140。在移除这些层之后，将结构上下倒置，使得管芯200设置在半导体衬底510上。
参考图1G，在包封体400、接合层540及介电层530中形成多个绝缘层穿孔(throughinsulating via，TIV)600。在一些实施例中，TIV 600形成在管芯200旁。在一些实施例中，TIV 600穿透过包封体400、接合层540及介电层530，以直接接触一些对位标记524。也就是说，一些对位标记524位于TIV 600与接触通孔512之间。在一些实施例中，TIV 600电连接到对位标记524及接触通孔512。换句话说，TIV 600通过对位标记524及接触通孔512被电接地。在一些实施例中，TIV 600的材料包括铝、钛、铜、镍、钨及/或其合金。在一些实施例中，TIV 600可通过以下步骤形成。首先，对包封体400、接合层540及介电层530执行激光钻孔或刻蚀工艺以形成多个开口(未示出)。所述开口暴露出一些对位标记524的至少一部分。此后，执行镀覆工艺以填充开口，从而形成TIV 600。
参考图1H，形成多个接合通孔250及接合层700。在一些实施例中，接合通孔250被形成为穿透过接合层300及管芯200的钝化层230，以建立与内连结构220的导电图案224的电连接。接合层700形成在管芯200、接合层300、包封体400及TIV 600上。在一些实施例中，接合层700是与接合层540相对地形成在管芯200上。在一些实施例中，接合层700包括介电层702、多个接合垫704及多个连接垫706。在一些实施例中，接合垫704及连接垫706嵌置在介电层702中。在一些实施例中，接合垫704形成在接合通孔250上，而连接垫706形成在TIV600上。也就是说，接合垫704连接到接合通孔250，且连接垫706连接到TIV 600。举例来说，连接垫706通过TIV 600、对位标记524及接触通孔512被电接地。另一方面，接合通孔250电连接内连结构220与接合垫704。
在一些实施例中，接合通孔250及接合垫704可通过双镶嵌工艺(dual damasceneprocess)形成。举例来说，介电层702首先形成在接合层300、包封体400及TIV 600上。在一些实施例中，介电层702的材料包括氧化物，例如氧化硅等。作为另外一种选择，介电层702可包含聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、BCB、PBO或任何其他合适的聚合物系介电材料。举例来说，介电层702可通过合适的制作技术(例如旋转涂布、CVD、PECVD等)形成。随后，通过移除这些层的一些部分而在介电层702中形成沟槽(未示出)，且在接合层300及钝化层230中形成介层孔(via hole，未示出)。在一些实施例中，沟槽的宽度大于介层孔的宽度。此后，将导电材料(未示出)填充到沟槽及介层孔中，以分别形成接合垫704及接合通孔250。在一些实施例中，通过同时填充介层孔及上覆的沟槽(未示出)来形成接合通孔250及接合垫704。在一些替代实施例中，可在形成接合层700之前形成接合通孔250。在一些实施例中，每一接合垫704的宽度可大于每一下伏的接合通孔250的宽度。在一些实施例中，接合通孔250及接合垫704包含相同的材料。用于接合通孔250及接合垫704的材料例如是铝、钛、铜、镍、钨或其合金。在一些实施例中，接合通孔250可被认为是管芯200的一部分。
在一些实施例中，接合垫704及连接垫706包含相同的材料。举例来说，连接垫706可由铝、钛、铜、镍、钨或其合金制成。在一些实施例中，接合垫704及连接垫706可同时形成。
在一些实施例中，介电层702的顶表面、接合垫704的顶表面与连接垫706的顶表面可被统称为接合表面S700。如图1H所示，介电层702的顶表面、接合垫704的顶表面与连接垫706的顶表面实质上位于相同的水平高度处，以提供用于混合接合(hybrid bonding)的合适的接合表面S700。
参考图1I，在管芯200上堆叠多个管芯800。在一些实施例中，每一管芯800包括半导体衬底810、内连结构820、钝化层830、导电垫840、多个半导体穿孔(throughsemiconductor via，TSV)850及多个接合通孔860。在一些实施例中，图1I中的半导体衬底810类似于图1B中的半导体衬底210，因此在此不再对其予以赘述。如图1I所示，内连结构820设置在半导体衬底810上。在一些实施例中，内连结构820包括介电间层822及多个导电图案824。内连结构820的介电间层822及导电图案824分别类似于内连结构220的介电间层222及导电图案224，因此在此不再对其予以赘述。
在一些实施例中，导电垫840设置在内连结构820上且电连接到内连结构820。另一方面，钝化层830形成在内连结构820上以密封导电垫840。管芯800的钝化层830及导电垫840分别类似于管芯200的钝化层230及导电垫240，因此在此不再对其予以赘述。如图1I所示，TSV 850嵌置在半导体衬底810中。在一些实施例中，TSV 850的材料可包括铝、钛、铜、镍、钨或其合金。在一些实施例中，TSV 850直接接触导电图案824，以使得与内连结构820电连接。
在一些实施例中，接合通孔860穿透过钝化层830以建立与内连结构820的导电图案824的电连接。在一些实施例中，接合通孔860的材料可包括铝、钛、铜、镍、钨或其合金。在一些实施例中，接合通孔860可通过镀覆工艺等形成。
在一些实施例中，管芯800能够执行存储功能。举例来说，管芯800可为动态随机存取存储器(Dynamic Random Access Memory，DRAM)、电阻式随机存取存储器(ResistiveRandom Access Memory，RRAM)、静态随机存取存储器(Static Random Access Memory，SRAM)等。然而，本公开并不仅限于此。在一些替代实施例中，管芯800可为中央处理器(CPU)管芯、图形处理单元(GPU)管芯、现场可编程门阵列(FPGA)等。
在一些实施例中，每一管芯800的大小可实质上与对应的管芯200的大小相同。举例来说，每一管芯800的宽度W800可实质上等于每一管芯200的宽度W200。在一些实施例中，每一管芯800具有有源表面800a及与有源表面800a相对的后表面800b。在一些实施例中，在放置管芯800之前，在每一管芯800的有源表面800a上形成接合层900。举例来说，接合层900形成在管芯800的钝化层830及接合通孔860上。在一些实施例中，接合层900包括介电层902及嵌置在介电层902中的多个接合垫904。在一些实施例中，接合层900的接合垫904电连接到接合通孔860。也就是说，接合通孔860电连接内连结构820与接合层900的接合垫904。图1I中的介电层902及接合垫904分别类似于图1H中的介电层702及接合垫704，因此在此不再对其予以赘述。
在一些实施例中，介电层902的底表面与接合垫904的底表面可被统称为接合表面S900。如图1I所示，介电层902的底表面与接合垫904的底表面实质上位于相同的水平高度处，以提供适合于混合接合的接合表面S900。
如图1I所示，各个管芯800被单独放置在对应的管芯200上，使得每一管芯800通过接合层700及接合层900而接合到对应的管芯200。举例来说，接合层900夹置在接合层700与管芯800之间。在一些实施例中，接合层700通过混合接合工艺接合到接合层900。在一些实施例中，混合接合工艺的温度介于从约150℃到约400℃的范围内。混合接合工艺将在下文详细阐述。
在一些实施例中，上面形成有接合层900的管芯800可被拾取并放置到接合层700的接合表面S700上，使得管芯800电连接到管芯200。在一些实施例中，接合层900的接合表面S900与接合层700的接合表面S700接触。举例来说，接合层900的接合垫904实质上与接合层700的对应的接合垫704对齐且直接接触。在一些实施例中，为了促进接合层700与接合层900之间的混合接合，可执行对接合层700与接合层900的接合表面(即，接合表面S700与接合表面S900)的表面准备。举例来说，表面准备可包括表面清洁及活化。可对接合表面S700及接合表面S900执行表面清洁，以移除介电层702的接合表面、接合垫704的接合表面、介电层902的接合表面及接合垫904的接合表面上的颗粒。在一些实施例中，例如，可通过湿式清洁(wet cleaning)来清洁接合表面S700及接合表面S900。不仅颗粒被移除，而且形成在接合垫704与接合垫904的接合表面上的原生氧化物(native oxide)也可被移除。举例来说，可通过在湿式清洁工艺中使用的化学品来移除形成在接合垫704的接合表面及接合垫904的接合表面上的原生氧化物。
在清洁接合层700的接合表面S700及接合层900的接合表面S900之后，可执行介电层702的接合表面及介电层902的接合表面的活化，以形成高接合强度。在一些实施例中，可执行等离子体活化来处理介电层702的接合表面及介电层902的接合表面。当介电层702的经活化的接合表面接触介电层902的经活化的接合表面时，接合层700的介电层702与接合层900的介电层902被预接合。
在将接合层900预接合到接合层700上之后，执行接合层700与接合层900的混合接合。接合层700与接合层900的混合接合可包括用于介电质接合的热处理及用于导体接合的热退火(thermal annealing)。在一些实施例中，执行用于介电质接合的热处理以强化介电层702与介电层902之间的接合。举例来说，用于介电质接合的热处理可在介于从约200℃到约400℃的范围内的温度下执行。在执行用于介电质接合的热处理之后，执行用于导体接合的热退火以促进接合垫704与接合垫904之间的接合。举例来说，用于导体接合的热退火可在介于从约150℃到约400℃的范围内的温度下执行。在执行用于导体接合的热退火之后，介电层702被混合接合到介电层902且接合垫704被混合接合到接合垫904。举例来说，介电层702直接接触介电层902。类似地，接合垫704直接接触接合垫904。因此，接合层700被混合接合到接合层900。尽管图1I示出接合垫704及接合垫904具有尖角(侧壁垂直于顶表面/底表面)，但本公开并不限于此。在一些替代实施例中，在接合垫704被混合接合到接合垫904之后，可发生接合垫的角圆化(corner rounding)。举例来说，面向接合垫904的接合垫704的角为圆角。类似地，面向接合垫704的接合垫904的角也为圆角。也就是说，每一接合垫704的顶表面的边缘为弧形的。类似地，每一接合垫904的底表面的边缘也为弧形的。此外，尽管图1I示出接合垫704与接合垫904具有相同的宽度且接合垫704的侧壁与接合垫904的侧壁对齐，但本公开并不限于此。在一些替代实施例中，每一接合垫704的宽度可小于或大于每一接合垫904的宽度。
在一些实施例中，由于图1H中的结构是晶片形式(wafer form)，且在上面形成有接合层900的管芯800是芯片形式(chip form)，因此图1I中的混合接合工艺可被称为“晶片上芯片接合工艺(chip-on-wafer bonding process)”。
参考图1J，在接合层700上形成包封体1000，以在侧向上包封管芯800及接合层900。也就是说，管芯800的后表面800b实质上与包封体1000的顶表面共面，且包封体1000覆盖管芯800的侧壁及接合层900的侧壁。在一些实施例中，包封体1000可被称为“间隙填充氧化物”。在一些实施例中，图1J中的包封体1000的材料及形成方法类似于图1D中的包封体400，因此在此不再对其予以赘述。
参考图1K，在包封体1000中形成多个TIV 1100。在一些实施例中，TIV 1100形成在管芯800旁。在一些实施例中，TIV 1100穿透过包封体1000以直接接触连接垫706。在一些实施例中，TIV 1100电连接到连接垫706。换句话说，TIV 1100通过连接垫706、TIV 600、对位标记524及接触通孔512被电接地。如图1K所示，TIV 1100实质上与TIV 600对齐。在一些实施例中，TIV 1100的材料包括铝、钛、铜、镍、钨及/或其合金。在一些实施例中，TIV 1100可通过以下步骤形成。首先，对包封体1000执行激光钻孔或刻蚀工艺，以形成多个开口(未示出)。所述开口暴露出每一连接垫706的至少一部分。此后，可执行镀覆工艺以填充开口，从而形成TIV 1100。
参考图1K及图1L，将图1K所示的结构放置在薄化平台ST上。在一些实施例中，薄化平台ST可被电连接到地(ground)。随后，对管芯800、包封体1000及TIV 1100进行薄化，直到暴露出管芯800的TSV 850。也就是说，管芯800从后表面800b进行薄化。在一些实施例中，可通过研磨工艺(例如机械研磨工艺、CMP工艺等)对管芯800、包封体1000及TIV 1100进行薄化或平坦化。在一些实施例中，在暴露出TSV 850之后，可进一步对管芯800、包封体1000及TIV 1100进行薄化，以减小管芯800的总厚度。在薄化工艺之后，管芯800的后表面800c实质上与包封体1000的顶表面1000a及TIV 1100的顶表面1100a共面。如图1L所示，在薄化工艺之后，TSV 850穿透过管芯800的半导体衬底810。
在一些实施例中，在薄化工艺期间，电子会在研磨表面(即，管芯800的后表面800c、包封体1000的顶表面1000a及TIV 1100的顶表面1100a)产生并累积。电子的累积会导致TSV 850及TIV 1100的腐蚀问题(corrosion issue)。不过，由于TIV 1100被电接地，所以TIV 1100能够建立使所累积的电子耗尽(deplete)的路径。换句话说，如图1L所示，所累积的电子将被下拉且依序经过TIV 1100、连接垫706、TIV 600及对位标记524而到达接触通孔512。接触通孔512中的电子可进一步被转移出所述结构。因此，由电子累积引起的腐蚀问题可得到解决。
参考图1M，移除每一管芯800的一部分以形成多个凹槽R。举例来说，移除每一管芯800的半导体衬底810的一部分以形成凹槽R。如图1M所示，TSV 850局部地位于凹槽R中。在一些实施例中，每一TSV 850的至少一部分从管芯800的半导体衬底810突出。也就是说，TSV850的顶表面850a、包封体1000的顶表面1000a及TIV 1100的顶表面1100a位于比管芯800的后表面800d高的水平高度处。在一些实施例中，可通过刻蚀工艺局部地移除半导体衬底810。刻蚀工艺包括例如各向同性刻蚀工艺(isotropic etching process)及/或各向异性刻蚀工艺(anisotropic etching process)。举例来说，可通过湿式刻蚀工艺、干式刻蚀工艺或其组合局部地移除半导体衬底810。
参考图1N，形成保护层1200以填充凹槽R。在一些实施例中，保护层1200包括模制化合物、模制底部填充胶等。作为另外一种选择，保护层1200可由聚合材料(例如聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、BCB、PBO或其他合适的聚合物系介电材料)制成。在一些实施例中，保护层1200可包含填料。作为另外一种选择，保护层1200可不含填料。如图1N所示，每一TSV 850的突出部分由保护层1200在侧向上包封。在一些实施例中，保护层1200可通过以下步骤形成。首先，保护材料层(未示出)形成在凹槽R中以及包封体1000及TIV 1100上。随后，对保护材料层执行研磨或薄化工艺，直到显露出TSV 850及TIV 1100。薄化工艺包括例如机械研磨工艺、CMP工艺等。类似于图1L所示的工艺，在薄化工艺期间，会在研磨表面产生且累积电子。再次，被电接地的TIV 1100能够建立使所累积的电子耗尽的路径，从而解决由电子累积引起的腐蚀问题。
参考图1N及图1O，从薄化平台ST分离所述结构。此后，在管芯800、包封体1000、保护层1200及TIV 1100上依序地形成重布线结构1300及多个导电端子1400。在一些实施例中，重布线结构1300包括多个介电层1310及多个重布线导电层1320。重布线导电层1320可包括多个重布线导电图案。在一些实施例中，每一重布线导电层1320夹置在两个相邻的介电层1310之间。重布线导电层1320的一些部分可在介电层1310内垂直延伸，以建立与其他上覆的或下伏的重布线导电层1320的电连接。在一些实施例中，重布线导电层1320的材料包括铝、钛、铜、镍、钨、其组合或其他合适的导电材料。举例来说，最底部的重布线导电层1320可包括多条铜迹线，而最顶部的重布线导电层1320可包括多个铝垫。然而，本公开并不限于此。重布线导电层1320可通过例如电镀、沉积及/或光刻及刻蚀来形成。在一些实施例中，介电层1310的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、BCB、PBO或任何其他合适的聚合物系介电材料。介电层1310可通过例如合适的制作技术(例如旋转涂布、CVD、PECVD等)形成。应注意的是，图1O中示出的介电层1310的数目及重布线导电层1320的数目仅是为说明目的，且本公开并不限于此。在一些替代实施例中，介电层1310的数目及重布线导电层1320的数目可根据电路设计而变化。在一些实施例中，重布线结构1300电连接到TSV850。举例来说，最底部的重布线导电层1320在实体上接触TSV 850，以建立与管芯800的电连接。
在一些实施例中，重布线结构1300还包括多个凸块下金属(under-bumpmetallurgy，UBM)图案1330。UBM图案1330电连接到重布线导电层1320。在一些实施例中，UBM图案1330通过重布线导电层1320电连接到TSV850。在一些实施例中，UBM图案1330中的每一者局部地嵌置在最顶部的介电层1310中。
如图1O所示，导电端子1400设置在UBM图案1330上。在一些实施例中，导电端子1400通过焊剂(solder flux)贴合到UBM图案1330。在一些实施例中，导电端子1400例如是焊料球、球栅阵列(ball grid array，BGA)球或受控塌陷芯片连接(controlled collapsechip connection，C4)凸块。在一些实施例中，导电端子1400由具有低电阻率的导电材料(例如Sn、Pb、Ag、Cu、Ni、Bi或其合金)制成。
参考图1O及图1P，在切割道区SR上执行单体化工艺以形成多个封装10。在一些实施例中，切割工艺(dicing process)或单体化工艺通常涉及使用旋转刀片(rotatingblade)或激光束进行切割。换句话说，切割或单体化工艺举例来说是激光切削工艺、机械切削工艺或其他合适的工艺。如图1P所示，管芯800堆叠在管芯200上。换句话说，多个管芯200、800被集成到单个封装10中。因此，封装10可被称为“集成电路级系统(system onintegrated circuit，SOIC)封装”。在一些实施例中，封装10可用于其他模组/应用，例如衬底上晶片上芯片(chip on wafer on substrate，CoWoS)封装、倒装芯片(flip-chip)封装、集成扇出(integrated fan-out，InFO)封装、扇出晶片级封装(fan-out wafer levelpackaging，fan-out WLP)等。
图2是根据本公开的一些替代实施例的封装20的示意性剖视图。参照图2，图2中的封装20类似于图1P中的封装10，因此其类似的元件由相同的附图标号表示，且在此不再对其予以赘述。然而，图1P的封装10中所示的介电层530在图2的封装20中被省略。也就是说，对位标记524直接接触接合层540。如图2所示，管芯800堆叠在管芯200上。换句话说，多个管芯200、800被集成到单个封装20中。因此，封装20可被称为“SOIC封装”。在一些实施例中，封装20可用于其他模组/应用中，例如CoWoS封装、倒装芯片封装、InFO封装、扇出WLP等。
图3A到图3B是根据本公开的一些替代实施例的封装30的制造工艺的示意性剖视图。参考图3A，图3A中的结构类似于图1O中的结构，因此其类似的元件由相同的附图标号表示，且在此不再对其予以赘述。换句话说，图3A中的结构可通过执行图1A到图1O中所示的步骤来获得。然而，在图3A中，接触通孔512、连接到接触通孔512的对位标记524、TIV600、连接垫706及TIV 1100形成在切割道区SR中。
参考图3A及图3B，在切割道区SR上执行单体化工艺以形成多个封装30。换句话说，移除位于切割道区SR中的接触通孔512、连接到接触通孔512的对位标记524、TIV 600、连接垫706及TIV 1100。如图3B所示，管芯800堆叠在管芯200上。换句话说，多个管芯200、800被集成到单个封装30中。因此，封装30可被称为“SOIC封装”。在一些实施例中，封装30可用于其他模组/应用中，例如CoWoS封装、倒装芯片封装、InFO封装、扇出WLP等。
图4A到图4H是根据本公开的一些替代实施例的封装40的制造工艺的示意性剖视图。参考图4A，图4A中的结构类似于图1I中的结构，因此其类似的元件由相同的附图标号表示，且在此不再对其予以赘述。换句话说，图4A中的结构可通过执行图1A到图1I中所示的步骤来获得。然而，如图4A所示，接合层700还包括多个辅助连接垫708。另外，每一管芯800的大小不同于对应的管芯200的大小。在一些实施例中，每一管芯800的大小小于对应的管芯200的大小。举例来说，每一管芯800的宽度W800小于每一管芯200的宽度W200。在一些实施例中，将管芯800放置成使得辅助连接垫708被暴露出。在一些实施例中，辅助连接垫708可由与接合垫704及连接垫706相同的材料制成。举例来说，辅助连接垫708可由铝、钛、铜、镍、钨或其合金制成。在一些实施例中，接合垫704、连接垫706及辅助连接垫708可同时形成。
参考图4B，形成包封体1000以在侧向上包封管芯800及接合层900。图4B中的步骤类似于图1J中所示的步骤，因此其类似的元件由相同的附图标号表示，且在此不再对其予以赘述。
参考图4C，在包封体1000中形成多个TIV 1100及多个辅助绝缘层穿孔(TIV)1500。在一些实施例中，TIV 1100及辅助TIV 1500形成在管芯800旁。在一些实施例中，TIV 1100穿透过包封体1000以直接接触连接垫706。在一些实施例中，TIV 1100电连接到连接垫706。换句话说，TIV 1100通过连接垫706、TIV 600、对位标记524及接触通孔512被电接地。如图4C所示，TIV 1100实质上与TIV 600对齐。在一些实施例中，辅助TIV 1500穿透过包封体1000以直接接触辅助连接垫708。举例来说，辅助TIV 1500电连接到辅助连接垫708。在一些实施例中，TIV 1100及辅助TIV 1500可由相同的材料形成。举例来说，TIV 1100及辅助TIV1500的材料包括铝、钛、铜、镍、钨及/或其合金。在一些实施例中，TIV 1100及辅助TIV 1500可同时形成。举例来说，TIV 1100及辅助TIV 1500可通过以下步骤形成。首先，对包封体1000执行激光钻孔或刻蚀工艺，以形成多个开口(未示出)。所述开口暴露出每一连接垫706的至少一部分及每一辅助连接垫708的至少一部分。此后，可执行镀覆工艺以填充开口，从而形成TIV 1100及辅助TIV 1500。然而，本公开并不限于此。在一些替代实施例中，辅助TIV1500可在TIV 1100形成之前或之后形成。
参考图4C及图4D，将图4C所示的结构放置在薄化平台ST上。在一些实施例中，薄化平台ST可被电连接到地。随后，对管芯800、包封体1000、TIV 1100及辅助TIV 1500进行薄化，直到暴露出管芯800的TSV 850。也就是说，管芯800从后表面800b进行薄化。在一些实施例中，可通过研磨工艺(例如机械研磨工艺、CMP工艺等)对管芯800、包封体1000、TIV 1100及辅助TIV 1500进行薄化或平坦化。在一些实施例中，在暴露出TSV 850之后，可进一步对管芯800、包封体1000、TIV 1100及辅助TIV 1500进行薄化，以减小管芯800的总厚度。在薄化工艺之后，管芯800的后表面800c实质上与包封体1000的顶表面1000a、TIV 1100的顶表面1100a及辅助TIV1500的顶表面1500a共面。如图4D所示，在薄化工艺之后，TSV 850穿透过管芯800的半导体衬底810。
在一些实施例中，在薄化工艺期间，电子会在研磨表面(即，管芯800的后表面800c、包封体1000的顶表面1000a、TIV 1100的顶表面1100a及辅助TIV 1500的顶表面1500a)产生并累积。电子的累积会导致TSV 850、TIV 1100及辅助TIV 1500的腐蚀问题。不过，由于TIV 1100被电接地，所以TIV 1100能够建立使所累积的电子耗尽的路径。换句话说，如图4D所示，所累积的电子将被下拉且依序经过TIV 1100、连接垫706、TIV 600及对位标记524而到达接触通孔512。接触通孔512中的电子可进一步被转移出所述结构。因此，由电子累积引起的腐蚀问题可得到解决。
参考图4E到图4G，图4E到图4G中的步骤类似于图1M及图1O中所示的步骤，因此其类似的元件由相同的附图标号表示，且在此不再对其予以赘述。如图4G所示，最底部的重布线导电层1320直接接触辅助TIV1500。换句话说，重布线结构1300电连接到辅助TIV 1500。在一些实施例中，辅助TIV 1500电连接辅助连接垫708与重布线结构1300。
参考图4G及图4H，在切割道区SR上执行单体化工艺以形成多个封装40。如图4H所示，管芯800堆叠在管芯200上。换句话说，多个管芯200、800被集成到单个封装40中。因此，封装40可被称为“集成电路系统(SOIC)封装”。在一些实施例中，封装40可用于其他模组/应用，例如衬底上晶片上芯片(CoWoS)封装、倒装芯片封装、集成扇出(InFO)封装、扇出晶片级封装(WLP)等。
图5是根据本公开的一些替代实施例的封装50的示意性剖视图。参考图5，图5中的封装50类似于图4H中的封装40，因此其类似的元件由相同的附图标号表示，且在此不再对其予以赘述。然而，图4H的封装40中所示的介电层530在图5的封装50中被省略。也就是说，对位标记524直接接触接合层540。如图5所示，管芯800堆叠在管芯200上。换句话说，多个管芯200、800被集成到单个封装50中。因此，封装50可被称为“SOIC封装”。在一些实施例中，封装50可用于其他模组/应用中，例如CoWoS封装、倒装芯片封装、InFO封装、扇出WLP等。
根据本公开的一些实施例，一种封装包括半导体载板、第一管芯、第二管芯、第一包封体、第二包封体、第一绝缘层穿孔(TIV)及第二TIV。所述半导体载板具有嵌置在其中的接触通孔。所述接触通孔被电接地。所述第一管芯设置在所述半导体载板上。所述第二管芯堆叠在所述第一管芯上。所述第一包封体在侧向上包封所述第一管芯。所述第二包封体在侧向上包封所述第二管芯。所述第一TIV位于所述第一管芯旁。所述第一TIV穿透过所述第一包封体且电连接到所述接触通孔。所述第二TIV位于所述第二管芯旁。所述第二TIV穿透过所述第二包封体且电连接到所述接触通孔及所述第一TIV。
根据本公开的一些实施例，所述接触通孔直接接触所述半导体载板。
根据本公开的一些实施例，所述封装还包括第一接合层、第二接合层以及重布线结构。所述第一接合层位于所述第一管芯、所述第一包封体及所述第一绝缘层穿孔上。所述第一接合层包括第一接合垫及连接垫，且所述第一绝缘层穿孔连接到所述连接垫。所述第二接合层夹置在所述第一接合层与所述第二管芯之间，其中所述第二接合层包括第二接合垫，且所述第一接合垫被混合接合到所述第二接合垫。所述重布线结构位于所述第二管芯及所述第二包封体上。
根据本公开的一些实施例，所述第一管芯包括第一半导体衬底、第一内连结构、第一钝化层以及第一接合通孔。所述第一内连结构位于所述第一半导体衬底上。所述第一钝化层位于所述第一内连结构上。所述第一接合通孔穿透过所述第一钝化层，其中所述第一接合通孔电连接所述第一内连结构与所述第一接合垫。
根据本公开的一些实施例，所述第二管芯包括第二半导体衬底、半导体穿孔、第二内连结构、第二钝化层以及第二接合通孔。所述半导体穿孔穿透过所述第二半导体衬底且电连接到所述重布线结构。所述第二内连结构位于所述第二半导体衬底上且电连接到所述半导体穿孔。所述第二钝化层位于所述第二内连结构上。所述第二接合通孔穿透过所述第二钝化层，其中所述第二接合通孔电连接所述第二内连结构与所述第二接合垫。
根据本公开的一些实施例，所述第一接合层还包括辅助连接垫，所述封装还包括穿透过所述第二包封体的辅助绝缘层穿孔，且所述辅助绝缘层穿孔电连接所述辅助连接垫与所述重布线结构。
根据本公开的一些实施例，所述封装还包括位于所述半导体载板与所述第一管芯之间的对位层，其中所述对位层包括对位标记。
根据本公开的一些实施例，所述对位标记中的至少一者位于所述接触通孔与所述第一绝缘层穿孔之间且电连接到所述接触通孔及所述第一绝缘层穿孔。
根据本公开的一些实施例，所述封装还包括位于所述对位层与所述第一包封体之间的介电层，其中所述第一绝缘层穿孔穿透过所述介电层。
根据本公开的一些实施例，一种封装的制造方法包括至少以下步骤。提供第一管芯。由第一包封体在侧向上包封所述第一管芯。将所述第一管芯及所述第一包封体贴合到其中嵌置有接触通孔的半导体载板。所述接触通孔被电接地。在所述第一包封体中形成第一绝缘层穿孔(TIV)。所述第一TIV通过所述接触通孔被电接地。将第二管芯接合到所述第一管芯。所述第二管芯包括半导体衬底及嵌置在所述半导体衬底中的半导体穿孔(TSV)。由第二包封体在侧向上包封所述第二管芯。在所述第二包封体中形成第二TIV。所述第二TIV通过所述第一TIV及所述接触通孔被电接地。对所述第二管芯、所述第二包封体及所述第二TIV进行研磨，直到暴露出所述第二管芯的所述TSV。在所述第二管芯及所述第二包封体上形成重布线结构。
根据本公开的一些实施例，将所述第二管芯接合到所述第一管芯包括至少以下步骤。在所述第一管芯、所述第一包封体及所述第一绝缘层穿孔上形成第一接合层。将上面形成有第二接合层的所述第二管芯堆叠在所述第一接合层上，其中所述第一接合层被混合接合到所述第二接合层。
根据本公开的一些实施例，所述封装的制造方法还包括形成穿透过所述第二包封体的辅助绝缘层穿孔，其中所述辅助绝缘层穿孔电连接到所述重布线结构。
根据本公开的一些实施例，所述辅助绝缘层穿孔及所述第二绝缘层穿孔是同时形成的。
根据本公开的一些实施例，所述封装的制造方法还包括在所述半导体载板与所述第一包封体之间形成对位层，其中所述对位层包括对位标记。
根据本公开的一些实施例，所述对位标记形成在所述接触通孔与所述第一绝缘层穿孔之间且电连接到所述接触通孔及所述第一绝缘层穿孔。
根据本公开的一些实施例，所述封装的制造方法还包括在所述对位层与所述第一包封体之间形成介电层，其中所述第一绝缘层穿孔穿透过所述介电层。
根据本公开的一些实施例，在对所述第二管芯、所述第二包封体及所述第二绝缘层穿孔进行所述研磨期间，因所述研磨而产生的电子从研磨表面依序经过所述第二绝缘层穿孔及所述第一绝缘层穿孔而行进到所述接触通孔。
根据本公开的一些替代实施例，一种封装的制造方法包括至少以下步骤。提供载板。在载板上以阵列方式放置第一管芯。由第一包封体在侧向上包封所述第一管芯。将所述第一管芯及所述第一包封体贴合到其中嵌置有接触通孔的半导体载板。所述半导体载板具有管芯区及位于两个相邻的管芯区之间的切割道区。所述第一管芯位于所述管芯区中。所述接触通孔位于所述切割道区中且被电接地。移除所述载板。在所述第一包封体中形成第一绝缘层穿孔(TIV)。所述第一TIV位于所述切割道区中且通过所述接触通孔被电接地。将第二管芯接合到所述第一管芯。所述第二管芯中的每一第二管芯包括半导体衬底及嵌置在所述半导体衬底中的半导体穿孔(TSV)。由第二包封体在侧向上包封所述第二管芯。在所述第二包封体中形成第二TIV。所述第二TIV位于所述切割道区且通过所述第一TIV及所述接触通孔被电接地。对所述第二管芯、所述第二包封体及所述第二TIV进行研磨，直到暴露出所述第二管芯的所述TSV。执行单体化工艺，以移除位于所述切割道区中的所述接触通孔、所述第一TIV及所述第二TIV。
根据本公开的一些替代实施例，所述封装的制造方法还包括形成穿透过所述第二包封体的辅助绝缘层穿孔，其中所述辅助绝缘层穿孔与所述第二绝缘层穿孔是同时形成的。
根据本公开的一些替代实施例，所述封装的制造方法还包括至少以下步骤。在所述半导体载板与所述第一包封体之间形成对位层，其中所述对位层包括形成在所述接触通孔与所述第一绝缘层穿孔之间且电连接到所述接触通孔及所述第一绝缘层穿孔的对位标记。在所述对位层与所述第一包封体之间形成介电层，其中所述第一绝缘层穿孔穿透过所述介电层以电连接到所述对位标记。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解，他们可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这种等效构造并不背离本公开的精神及范围，且他们可在不背离本公开的精神及范围的条件下在本文中作出各种改变、代替及变更。

Claims (1)

1.一种封装，包括：
半导体载板，具有嵌置在所述半导体载板中的接触通孔，其中所述接触通孔被电接地；
第一管芯，设置在所述半导体载板上；
第二管芯，堆叠在所述第一管芯上；
第一包封体，在侧向上包封所述第一管芯；
第二包封体，在侧向上包封所述第二管芯；
第一绝缘层穿孔，位于所述第一管芯旁，其中所述第一绝缘层穿孔穿透过所述第一包封体且电连接到所述接触通孔；以及
第二绝缘层穿孔，位于所述第二管芯旁，其中所述第二绝缘层穿孔穿透过所述第二包封体且电连接到所述接触通孔及所述第一绝缘层穿孔。
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