CN109830490A - 混合接合结构及其制造方法 - Google Patents

混合接合结构及其制造方法 Download PDF

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Publication number
CN109830490A
CN109830490A CN201810959903.0A CN201810959903A CN109830490A CN 109830490 A CN109830490 A CN 109830490A CN 201810959903 A CN201810959903 A CN 201810959903A CN 109830490 A CN109830490 A CN 109830490A
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conductor
dielectric layer
internal connection
integrated circuit
wire structure
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CN109830490B (zh
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蔡伯宗
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭露提供包括第一集成电路组件与第二集成电路组件的混合接合结构。第一集成电路组件包括第一介电层、第一导体与隔离结构。第一导体与隔离结构嵌入于第一介电层中。隔离结构与第一导体电性绝缘，且隔离结构围绕第一导体。第二集成电路组件包括第二介电层与第二导体。第二导体嵌入于第二介电层中。第一介电层接合至第二介电层，且第一导体接合至第二导体。

Description

混合接合结构及其制造方法
技术领域
本发明涉及一种混合接合结构及其制造方法。
背景技术
制造三维集成电路(three-dimensional integrated circuit，3D-IC)组件的方法包括通过晶片级混合接合(wafer level hybrid bonding)技术以进行晶片对晶片的接合(wafer-to-wafer bonding)。三维集成电路例如是背侧照明式互补金氧半导体影像感测器(back-side illuminated complementary metal-oxide semiconductor imagesensor，BSI-CIS)。在制造BSI-CIS时，提供包括阵列排列的背照明式集成电路的感测器晶片以及包括阵列排列的逻辑电路芯片的逻辑电路晶片。通过晶片级混合接合技术将感测器晶片与逻辑电路晶片对接，以使逻辑电路晶片堆迭于感测器晶片上。随后，封装经混合接合的感测器晶片与逻辑电路晶片，且进行单体化以形成BSI-CIS器件。在感测器晶片与逻辑电路晶片的混合接合工艺期间，在两晶片的接合介面处可能产生铜突出(copper extrusion)及/或铜迁移(copper migration)。如此一来，混合接合的晶片的可靠度因上述的铜突出及/或铜迁移而降低。
发明内容
根据本揭露的一些实施例，提供第一集成电路组件，其中所述第一集成电路组件包括其中具有多个第一半导体器件的第一半导体衬底、设置于所述第一半导体衬底上的第一内连线结构、覆盖所述第一内连线结构的第一介电层以及至少一第一导体群组，所述至少一第一导体群组包括经由所述第一内连线结构而彼此电性连接的多个第一导体；提供第二集成电路组件，其中所述第二集成电路组件包括其中具有多个第二半导体器件的第二半导体衬底、设置于所述第二半导体衬底上的第二内连线结构、覆盖所述第二内连线结构的第二介电层以及至少一第二导体群组，所述至少一第二导体群组包括经由所述第二内连线结构而彼此电性连接的多个第二导体；以及进行混合接合工艺以接合所述第一集成电路组件与所述第二集成电路组件，以使所述第一介电层接合至所述第二介电层，且所述多个第一导体接合至所述多个第二导体。
根据本揭露的一些实施例，提供混合接合结构的制造方法，包括下列步骤：提供第一集成电路组件，其中所述第一集成电路组件包括第一半导体衬底、第一内连线结构、第一介电层以及多个第一导体群组，所述第一半导体衬底包括位于其中的多个第一半导体器件，所述第一内连线结构设置于所述第一半导体衬底上并电性连接至所述第一半导体器件，所述第一介电层覆盖所述第一内连线结构，所述多个第一导体群组嵌入于所述第一介电层中并经由所述第一内连线结构而电性连接至所述第一半导体器件，且所述多个第一导体群组中的至少一第一导体群组包括彼此电性连接的多个第一导体；提供第二集成电路组件，其中所述第二集成电路组件包括第二半导体衬底、第二内连线结构、第二介电层以及多个第二导体群组，所述第二半导体衬底包括位于其中的多个第二半导体器件，所述第二内连线结构设置于所述第二半导体衬底上并电性连接至所述第二半导体器件，所述第二介电层覆盖所述第二内连线结构，所述多个第二导体群组嵌入于所述第二介电层中并经由所述第二内连线结构而电性连接至所述第二半导体器件，且所述多个第二导体群组中的至少一第二导体群组包括彼此电性连接的多个第二导体；进行混合接合工艺以接合所述第一集成电路组件与所述第二集成电路组件，以使所述第一介电层接合至所述第二介电层，且所述至少一第一导体群组电性连接至所述至少一第二导体群组，其中所述至少一第一导体群组、所述至少一第二导体群组、所述第一内连线结构以及所述第二内连线结构提供分流路径。
根据本揭露的一些实施例，提供包括第一集成电路芯片与第二集成电路芯片的混合接合结构。第一集成电路芯片包括其中具有多个第一半导体器件的第一半导体衬底、设置于所述第一半导体衬底上的第一内连线结构、覆盖所述第一内连线结构的第一介电层以及至少一第一导体群组，所述至少一第一导体群组包括经由所述第一内连线结构而彼此电性连接的多个第一导体。第二集成电路芯片包括其中具有多个第二半导体器件的第二半导体衬底、设置于所述第二半导体衬底上的第二内连线结构、覆盖所述第二内连线结构的第二介电层以及至少一第二导体群组，所述至少一第二导体群组包括经由所述第二内连线结构而彼此电性连接的多个第二导体。
附图说明
包含附图以便进一步理解本发明，且附图并入本说明书中并构成本说明书的一部分。附图说明本发明的实施例，并与描述一起用于解释本发明的原理。
图1至图7根据本揭露的一些实施例绘示用以制造BSI-CIS器件的工艺流程。
图8与图9是根据本揭露的一些实施例绘示的晶片的混合接合工艺的剖视图。
图10是根据本揭露的一些实施例的混合接合结构的剖视图。
图11与图12是根据本揭露的一些替代实施例绘示的晶片的混合接合工艺的剖视图。
图13至图18是根据本揭露的各种实施例绘示的混合接合结构的剖视图。
图19至图28是根据本揭露的各种实施例分别绘示的第一集成电路组件及/或第二集成电路组件的一导体群组的上视图。
具体实施方式
以下揭露内容提供用于实作本发明的不同特征的诸多不同的实施例或实例。以下阐述组件及配置的具体实例以简化本揭露内容。当然，该些仅为实例且不旨在进行限制。举例而言，以下说明中将第一特征形成于第二特征「之上」或第二特征「上」可包括其中第一特征与第二特征被形成为直接接触的实施例，且亦可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本揭露内容可能在各个实例中重复使用参考编号及/或字母。此种重复使用是出于简洁及清晰的目的，但自身并不表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如「位于…之下(beneath)」、「位于...下面(below)」、「下部的(lower)」、「位于...上方(above)」、「上部的(upper)」等空间相对性用语来阐述图中所示一个部件或特征与另一(其他)部件或特征的关系。所述空间相对性用语旨在除图中所绘示的定向外亦囊括器件在使用或操作中的不同定向。装置可具有其他定向(旋转90度或处于其他定向)，且本文中所用的空间相对性描述语可同样相应地进行解释。
图1至图7根据本揭露的一些实施例绘示用以制造BSI-CIS器件的工艺流程。
请参照图1，提供第一集成电路组件100与第二集成电路组件200。第一集成电路组件100可包括其中形成有多个第一半导体器件的第一半导体衬底110、设置于第一半导体衬底110上的第一内连线结构120、覆盖第一内连线结构120的第一介电层130以及至少一第一导体群组140。至少一第一导体群组140可包括经由第一内连线结构120相互电性连接的多个第一导体142。至少一第一导体群组140嵌入于第一介电层130中。第二集成电路组件200可包括其中形成有多个第二半导体器件的第二半导体衬底210、设置于第二半导体衬底210上的第二内连线结构220、覆盖第二内连线结构220的第二介电层230以及至少一第二导体群组240。至少一第二导体群组40可包括经由第二内连线结构220相互电性连接的多个第二导体242。至少一第二导体群组240嵌入于第二介电层230中。
如图1所示，在一些实施例中，第一集成电路组件100可为包括阵列排列的多个影像感测芯片102的第一半导体晶片(亦即感测器晶片)，且第二集成电路组件200可为包括阵列排列的多个逻辑集成电路芯片202的第二半导体晶片(亦即逻辑电路晶片)。换言之，上述的第一半导体衬底110、第一内连线结构120、第一介电层130以及至少一第一导体群组140可形成第一半导体晶片内的多个影像感测芯片102，且上述的第二半导体衬底210、第二内连线结构220、第二介电层230以及至少一第二导体群组240可形成第二半导体晶片内的多个逻辑集成电路芯片202。
在一些实施例中，第一导体142与第二导体242的材料可为铜或其他适合的金属材料，而第一介电层130与第二介电层230的材料可为氧化硅(SiOx，其中x大于零)、氮化硅(SiNx，其中x大于零)、氮氧化硅(SiOxNy，其中x大于零，且y大于零)或其他适合的介电材料。可通过沈积工艺形成第一导体142，且接着进行化学机械研磨(chemical mechanicalpolishing，CMP)。相似地，可通过另一沈积工艺形成第二导体242，且接着进行化学机械研磨。第一导体142与第二导体242有助于调整导体密度，以减少腐蚀(corrosion)及/或碟形凹陷(dishing)的问题。
在一些实施例中，对第一集成电路组件100与第二集成电路组件200的接合表面进行表面处理(surface preparation)，以协助晶片对晶片混合接合(wafer-to-waferhybrid bonding)。举例而言，表面处理可包括表面清洁与活化(activation)。可在第一集成电路组件100与第二集成电路组件200的接合表面上进行表面清洁，以移除第一导体142、第一介电层130、第二导体242以及第二介电层230的顶面上的微粒(particle)。举例而言，可通过湿式清洁来清洁第一集成电路组件100与第二集成电路组件200的接合表面。除了移除微粒之外，也可移除形成于第一导体142与第二导体242的顶面上的原生氧化层(nativeoxide)。举例而言，可通过使用湿式清洁工艺中的化学品移除形成于第一导体142与第二导体242的顶面上的原生氧化层。
在清洁第一集成电路组件100与第二集成电路组件200的接合表面之后，可对第一介电层130与第二介电层230的顶面进行活化，以用于发展出高接合强度。在一些实施例中，可进行电浆活化，以对第一介电层130与第二介电层230的顶面进行处理。
请参照图1与图2，第一集成电路组件100与第二集成电路组件200相互对齐，且可达到次微米级的对位精度(sub-micron alignment precision)。一旦第一集成电路组件100与第二集成电路组件200精确地相互对齐，将第一集成电路组件100放置且接触于第二集成电路组件200上。第一介电层130的经活化的顶面接触第二介电层230的经活化的顶面时，第一集成电路组件100的第一介电层130与第二集成电路组件200的第二介电层230被预接合(pre-bond)。换言之，经由第一介电层130与第二介电层230预接合第一集成电路组件100与第二集成电路组件200。在第一介电层130与第二介电层230预接合之后，第一导体142接触第二导体242。
在将第一集成电路组件100预接合至第二集成电路组件200上之后，进行第一集成电路组件100与第二集成电路组件200的混合接合。第一集成电路组件100与第二集成电路组件200的混合接合可包括用于介电层接合(dielectric bonding)的处理以及用于导体接合(conductor bonding)的热退火(thermal annealing)。在一些实施例中，进行用于介电层接合的处理以增强第一介电层130与第二介电层230之间的接合。举例而言，可在约摄氏100度至约摄氏150度的温度范围进行用于介电层接合的处理。在进行用于介电层接合的处理之后，进行用于导体接合的热退火以协助第一导体142与第二导体242之间的接合。举例而言，可在约摄氏300度至约摄氏400度的温度范围进行用于导体接合的热退火。用于导体接合的热退火的工艺温度高于用于介电层接合的处理的工艺温度。由于在较高的温度下进行用于导体接合的热退火，故金属的扩散与晶粒成长(grain growth)可能会发生于第一导体142与第二导体242之间的接合接面。另一方面，在进行用于导体接合的热退火时，第一导体142与第二导体242可能承受由导体(第一导体142与第二导体242)与介电层(第一介电层130与第二介电层230)之间的热膨胀系数差异造成的压力。在进行用于导体接合的热退火之后，第一介电层130接合至第二介电层230，且第一导体140接合至第二导体240。在一些实施例中，第一导体140可为导电通孔(例如是铜通孔)、导电接垫(例如是铜接垫)或其组合，而第二导体240可为导电通孔(例如是铜通孔)、导电接垫(例如是铜接垫)或其组合。举例而言，第一导体140与第二导体240之间的导体接合可为通孔对通孔接合(via-to-viabonding)、接垫对接电接合(pad-to-pad bonding)或通孔对接垫接合(via-to-padbonding)。
在进行第一集成电路组件100与第二集成电路组件200的混合接合之后，第一内连线结构120与第二内连线结构220经由第一导体142与第二导体242而彼此电性连接。
如图2所示，在混合接合第一集成电路组件100与第二集成电路组件200之后，完成包括彼此堆迭且混合接合的晶片的混合接合结构HB1。在一些实施例中，若有需要，可将混合接合结构HB1单体化为经单体化的多个混合接合结构HB2。每一经单体化的混合接合结构HB2包括彼此堆迭且混合接合的芯片。换言之，每一经单体化的混合接合结构HB2可包括逻辑集成电路芯片与影像感测芯片，其中影像感测芯片堆迭且混合接合于逻辑集成电路芯片上。在以上所述的实施例中，混合接合结构HB1包括混合接合晶片，且混合接合结构HB2包括混合接合芯片。然而，本揭露并不以此为限。在一些替代实施例中，混合接合结构(未绘示)可包括晶片以及堆迭且混合接合于晶片上的至少一芯片。
请参照图3与图4，在第一半导体衬底110的背面上形成接着层(adhesive)300。举例而言，接着层300经形成以覆盖影像感测芯片102的边缘区域，从而环绕影像感测芯片102的感测区域。提供盖板400。盖板400具有设置于盖板400的底面上的间隔件500。可应用盖板400以覆盖混合接合结构HB1，且间隔件500的位置对应于接着层300的分布位置。通过形成于混合接合结构HB1上的接着层300，间隔件500附接于混合接合结构HB1，且在盖板400与混合接合结构HB1之间形成间隙。由于盖板400通过间隔件500与间隙而与混合接合结构HB1隔开，形成于混合接合结构HB1上的组件不与盖板400接触，且可被良好地保护。举例而言，接着层300的材料可为具有适当的绝缘特性的有机材料。盖板400可为具有光学涂层(例如是抗反射涂层)或不具有光学涂层的盖玻璃(cover glass)，且间隔件500可为环氧树脂或其他适合的材料。
在一些实施例中，在盖板400与间隔件500附接至混合接合结构HB1之后，可在第二半导体衬底210的背面上进行研磨工艺，以进一步降低混合接合结构HB1的厚度。
请参照图5，在盖板400与间隔件500经由接着层300附接于混合接合结构HB1之后，在第二半导体衬底210中形成多个穿孔TH。举例而言，可通过硅穿孔(through siliconvia，TSV)工艺形成多个穿孔TH，直至第二集成电路组件200的第二内连线结构220暴露出来为止。随后，在第二半导体衬底210的背面(亦即底面)上形成重布线层250。重布线层250经由穿孔TH而电性连接至第二内连线结构220。在形成重布线层250之前，可在第二半导体衬底210的背面以及穿孔TH的侧壁上形成绝缘层(未绘示)，从而使重布线层250与第二半导体衬底210电性绝缘。如图5所示，重布线层250将第一内连线结构120与第二内连线结构220重分布至第二半导体衬底210的背面。在一些实施例中，尽管未绘示于图式中，内连线结构220可包括着陆接垫(landing pad)。着陆接垫可被穿孔TH暴露，且重布线层250可经由穿孔TH而电性连接至着陆接垫。
请参照图6，在第二半导体衬底210的背面上形成钝化层260，以部分地覆盖重布线层250。钝化层260可包括多个开口，以部分地暴露出重布线层250(例如是暴露出重布线层250的焊球接垫(ball pad))。在形成钝化层260之后，在重布线层250的被钝化层260的开口暴露的部分上形成阵列排列的多个导电端子270(例如是导电焊球)。导电端子270可为通过植球(ball placement)与回流(reflow)工艺形成的焊球。
请参照图6与图7，在形成导电端子270之后，沿着切割线SL进行切割工艺(dicingprocess)以单体化图6所得的结构，以形成多个BSI-CIS器件。如图7所示，经单体化的BSI-CIS器件可为球栅阵列(ball grid array，BGA)器件。
混合接合结构HB1可影响BSI-CIS器件的可靠度。由于突出(例如是铜突出)及/或迁移(例如是电迁移、热迁移及/或应力迁移)可能发生于混合接合的介面，第一集成电路组件100与第二集成电路组件200之间的电性连接可能因此失效。需要第一内连线结构120与第二内连线结构220的新颖设计以解决突出与迁移的问题。接下来，将参照图8至图18而描述第一内连线结构120与第二内连线结构220的细节。
图8与图9是根据本揭露的一些实施例绘示的晶片的混合接合工艺的剖视图。
请参照图8与图9，在一些实施例中，第一集成电路组件100可包括形成于第一半导体衬底100上或第一半导体衬底100中的多个第一半导体器件112(例如是光二极管(photodiode)、晶体管、电容等)以及形成于第一半导体衬底110的背面(例如是顶面)的微透镜阵列(micro-lens array)ML。形成于第一半导体衬底110中的第一半导体器件112可阵列排列，且形成于第一半导体衬底110的背面上的微透镜阵列ML可覆盖第一半导体器件112。在一些替代实施例中，第一集成电路组件100更可包括形成于微透镜阵列ML与第一半导体器件112之间的多个滤光层(color filter)CF。换言之，滤光层CF形成于第一半导体衬底110的背面上，而微透镜阵列ML形成于滤光层CF上。基于实际的设计需求，可形成其他光学组件(例如是黑色矩阵(black matrix))，以改善第一集成电路组件100中的第一半导体器件112的光学特性。
此外，在一些实施例中，第二集成电路组件200可包括形成于第二半导体衬底210中或第二半导体衬底210上的多个第二半导体器件212(例如是晶体管、电容等)。在一些实施例中，第二半导体器件212与第一内连线结构120可构成逻辑电路系统(logiccircuitry)。
如图8与图9所示，尽管示出第一导体142的两个群组以及第二导体242的两个群组，本揭露并不以形成于第一集成电路组件100上的第一导体142的群组数量与形成于第二集成电路组件200上的第二导体242的群组数量为限。再者，本揭露并不以各个导体群组(第一导体群组140或第二导体群组240)包括的导体(第一导体142或第二导体242)的数量为限。在此实施例中，举例而言，一个第一导体群组140包括两个第一导体142，且一个第二导体群组240包括两个第二导体242。
第一导体群组140可经由第一内连线结构120中的第一分流走线ST1电性连接至第一半导体器件112。换言之，至少一第一导体群组140可经由第一内连线结构120中的一个对应的第一分流走线ST1而电性连接至第一半导体器件112中的一者。第一分流走线ST1的数量可等同于第一导电群组140的数量。在一些实施例中，第一内连线结构120可包括层间介电层(inter-dielectric layer)122以及内连线金属层124。内连线金属层124电性连接于第一导体群组140与第一半导体器件112之间。第一内连线结构120中的第一分流走线ST1可由内连线金属层124的一些部分形成。相似地，第二导体群组240可经由第二内连线结构220中的第二分流走线ST2而电性连接至第二半导体器件212。换言之，至少一第二导体群组240可经由第二内连线结构220中的一个对应的第二分流走线ST2而电性连接至第二半导体器件212中的一者。第二分流走线ST2的数量可等同于第二导体群组240的数量。在一些实施例中，第二内连线结构220可包括层间介电层222以及内连线金属层224。内连线金属层224电性连接于第二导体群组240与第二半导体器件212之间。第二内连线结构220中的第二分流走线ST2可由内连线金属层224的一些部分形成。
第一导体群组140中的一者所包括的第一导体142直接接触且连接于内连线金属层124的的一个最顶层的金属图案(亦即最底层的金属层)。相似地，第二导体群组240中的一者所包括的第二导体242直接接触且连接于内连线金属层224的一个最顶层金属图案(亦即最上层金属层)。换言之，第一导体142与第二导体242位于内连线金属层124的最顶层金属图案与内连线金属层224的最顶层金属图案之间。
如图8所示，在混合接合第一集成电路组件100与第二集成电路组件200之前，清洁第一集成电路组件100与第二集成电路组件200，且将第一集成电路组件100与第二集成电路组件200相互对齐，以用于预接合。换言之，在第一集成电路组件100上的第一导体群组140以及在第二集成电路组件200上的第二导体群组240在进行混合接合之前已相互对齐。
如图9所示，在混合接合第一集成电路组件100与第二集成电路组件200之后，第一分流走线ST1、第二分流走线ST2、第一导体142(亦即第一导体群组140)以及第二导体242(亦即第二导体群组240)在第一集成电路组件100与第二集成电路组件200中提供多条分流路径SP1。第一半导体器件112可经由分流路径SP1而电性连接至第二半导体器件212。在此实施例中，每一分流路径SP1包括用于在第一半导体器件112与第二半导体器件212之间传输电流的两连接路径。然而，本揭露并不以每一分流路径SP1中的连接路径的数量为限。在一些替代实施例中，不同分流路径SP1中的连接路径的数量可彼此相同，或彼此相异。
第一分流走线ST1与第二分流走线ST2可分散(spread)在第一半导体器件112与第二半导体器件212之间流动的电流，以降低第一分流走线ST1与第二分流走线ST2的电流密度。第一分流走线ST1与第二分流走线ST2中电流密度的下降可减少发生于第一集成电路组件100与第二集成电路组件200之间的混合接合介面的电迁移(例如是铜迁移)。第一分流走线ST1与第二分流走线ST2以及混合接合导体(第一导体142/第二导体242)可提供低的电阻。再者，第一分流走线ST1与第二分流走线ST2可分散在混合接合期间第一导体142与第二导体242所承受的应力。分散第一导体142与第二导体242所承受的应力可减少发生于第一集成电路组件100与第二集成电路组件200之间的混合接合介面的应力迁移。如此一来，基于第一分流走线ST1与第二分流走线ST2，可提高混合接合的良率(yield)。
在上述的用于介电层接合的处理期间，第一内连线结构120与第二内连线结构220的设计可减少由热迁移导致的断路及/或短路的问题。在上述用于导体接合的热退火期间，第一内连线结构120与第二内连线结构220的设计不只是可减少由热迁移导致的断路及/或短路的问题，更可减少热膨胀系数差异导致的突出问题。在上述的用于减低混合接合结构(如图4所示)的厚度的研磨工艺期间，第一内连线结构120与第二内连线结构220的设计可减少应力所导致的突出问题与应力迁移。在BSI-CIS器件的操作期间，第一内连线结构120与第二内连线结构220的设计可减少电迁移造成的断路/短路问题。综上所述，第一内连线结构120与第二内连线结构220的设计可减少上述的突出与迁移。
图10是根据本揭露的一些实施例的混合接合结构的剖视图。
请参照图9与图10，图10所示的混合接合结构相似于图9所示的混合接合结构，惟每一第一导体群组140包括3个第一导体142，且每一第二导体群组240包括3个第二导体242。此外，在此实施例中，每一分流路径SP2例如是包括用于在第一半导体器件112与第二半导体器件212之间传输电流的3个连接路径。然而，本揭露并不以每一分流路径SP2中的连接路径的数量为限。在一些替代实施例中，不同分流路径SP2中的连接路径的数量可彼此相同，或彼此相异。
图11与图12是根据本揭露的一些替代实施例绘示的晶片的混合接合工艺的剖视图。
请参照图8、图9、图11与图12，图11及图12所绘示的第一内连线结构120与第二内连线结构220相似于图8及图9所示的第一内连线结构120与第二内连线结构220，惟第一导体群组140的一者所包括的第一导体142接触于内连线金属层124的多个顶层金属图案(亦即最下层的金属层)，且第一导体群组140的一者所包括的第一导体142通过位于顶层金属图案上方的一金属图案而彼此电性连接。相似地，第二导体群组240的一者所包括的第二导体242接触于内连线金属层224的多个顶层金属图案(亦即最上层的金属层)，且第二导体群组240的一者所包括的第二导体242通过位于顶层金属图案上方的一金属图案而彼此电性连接。
第一导体群组140可经由第一内连线结构120中的第一分流走线ST1而电性连接至第一半导体器件112。换言之，至少一第一导体群组140可经由第一内连线结构120中的一对应的第一分流走线ST1而电性连接至第一半导体器件112的一者。第一分流走线ST1的数量可等同于第一导体群组140的数量。在一些实施例中，第一内连线结构120可包括层间介电层122与内连线金属层124。内连线金属层124电性连接于第一导体群组140与第一半导体器件112之间。第一内连线结构120中的第一分流走线ST1可由内连线金属层124的一些部分形成。相似地，第二导体群组240可经由第二内连线结构220中的第二分流走线ST2而电性连接至第二半导体器件212。换言之，至少一第二导体群组240可经由第二内连线结构220中的一对应的第二分流走线ST2而电性连接至第二半导体器件212的一者。第二分流走线ST2的数量可等同于第二导体群组240的数量。在一些实施例中，第二内连线结构220可包括层间介电层222与内连线金属层224。内连线金属层224电性连接于第二导体群组240与第二半导体器件212之间。第二内连线结构220中的第二分流走线ST2可由内连线金属层224的一些部分形成。换言之，除了第一导体142与第二导体242位于内连线金属层124的顶层金属图案与内连线金属层224的顶层金属图案之间之外，内连线金属层124与内连线金属层224的一些部分夹设于内连线金属层124的顶层金属图案与内连线金属层224的顶层金属图案之间。
图13至图18是根据本揭露的各种实施例绘示的混合接合结构的剖视图。
请参照图13，图13中的第一内连线结构120与第二内连线结构220相似于图11与图12中的第一内连线结构120与第二内连线结构220，惟第一内连线结构120还包括多个隔离结构。每一隔离结构包括隔离部分128A与隔离部分128B。隔离结构的隔离部分128A与第一导体142电性绝缘，且隔离部分128A的一者环绕第一导体142。此外，隔离结构的多个隔离部分128B与第二导体242电性绝缘，且隔离部分128B的一者环绕第二导体242。隔离部分128A嵌入于第一介电层130中，且隔离部分128B嵌入于第二介电层230中。隔离部分128A为电性浮置(electrically floated)并彼此分离，且隔离部分128B为电性浮置并彼此分离。如图13所示，每一隔离部分128A分别混合接合于隔离结构128B的一者。在一些实施例中，可通过相同的工艺与相同的材料形成隔离部分128A与第一导体142，且可通过相同的工艺与相同的材料形成隔离部分128B与第二导体242。举例而言，隔离部分128A、第一导体142、隔离部分128B与第二导体242由相同的材料构成，所述材料例如是铜或其他适合的金属材料。
可通过沈积工艺与随后的化学机械研磨形成第一导体142与隔离部分128A。相似地，可通过另一沈积工艺与随后的化学机械研磨形成第二导体242与隔离部分128B。第一导体142、隔离部分128A、第二导体242与隔离部分128B有助于调整导体密度，以减少腐蚀及/或碟形凹陷的问题。此外，电性浮置的隔离部分128A与隔离部分128B可抑制第一导体142与第二导体242的迁移问题所导致的断路/短路问题。
请参照图14，图14所示的第一内连线结构120与第二内连线结构220相似于图13所示的第一内连线结构120与第二内连线结构220，惟省略第一内连线结构120中的隔离部分128A(如图13所示)。在一些实施例中，可通过相同的工艺与相同的材料形成隔离部分128B与第二导体242。举例而言，隔离部分128B、第一导体142与第二导体242可由相同的材料构成，所述材料例如是铜或其他适合的金属材料。
请参照图15，图15所示的第一内连线结构120与第二内连线结构220相似于图13所示的第一内连线结构120与第二内连线结构220，惟省略第二内连线结构220中的隔离部分128B(如图13所示)。在一些实施例中，可通过相同的工艺与相同的材料形成隔离部分128A与第一导体142。举例而言，隔离部分128A、第一导体142与第二导体242可由相同的材料构成，所述材料例如是铜或其他适合的金属材料。
请参照图16至图18，图16、图17与图18所示的第一内连线结构120与第二内连线结构220相似于图13、图14与图15所示的第一内连线结构120与第二内连线结构220，惟第一内连线结构120与第二内连线结构220中不具有第一分流走线ST1与第二分流走线ST2。换言之，分流走线的设计不需要与隔离结构结合。
图19至图28是根据本揭露的各种实施例分别绘示的第一集成电路组件及/或第二集成电路组件的一导体群组的上视图。
请参照图19至图22，在一导体群组(第一导体群组140/第二导体群组240)中，可包括多个(例如是2个、3个或4个)导体(第一导体142/第二导体242)。每一导体(第一导体142/第二导体242)被一隔离部分128A及/或隔离部分128B环绕。在此实施例中，隔离部分128A或隔离部分128B可为矩形环。属于一导体群组(第一导体群组140/第二导体群组240)的导体(第一导体142/第二导体242)可沿着列方向或行方向排列，或阵列排列。
如图23与图24所示，在一些替代实施例中，通过一内连线金属层(内连线金属层124/内连线金属层224)而彼此电性连接的导体(第一导体142/第二导体242)可具有例如是圆形的形状，且隔离部分128A或隔离部分128B可例如是圆环。在一些替代实施例中，如图25与图26所示，通过一内连线金属层(内连线金属层124/内连线金属层224)而彼此电性连接的导体(第一导体142/第二导体242)可具有例如是矩形的形状，且隔离部分128A或隔离部分128B可例如是包括多个彼此分离的隔离条(isolation stripe)，其中多个隔离条例如是经配置以环绕导体(第一导体142/第二导体242)。在一些其他实施例中，如图27与图28所示，通过一内连线金属层(内连线金属层124/内连线金属层224)而彼此电性连接的导体(第一导体142/第二导体242)可例如是具有矩形的形状，且隔离部分128A或隔离部分128B可具有六边形的形状。
根据本揭露的一些实施例，提供第一集成电路组件，其中所述第一集成电路组件包括其中具有多个第一半导体器件的第一半导体衬底、设置于所述第一半导体衬底上的第一内连线结构、覆盖所述第一内连线结构的第一介电层以及至少一第一导体群组，所述至少一第一导体群组包括经由所述第一内连线结构而彼此电性连接的多个第一导体；提供第二集成电路组件，其中所述第二集成电路组件包括其中具有多个第二半导体器件的第二半导体衬底、设置于所述第二半导体衬底上的第二内连线结构、覆盖所述第二内连线结构的第二介电层以及至少一第二导体群组，所述至少一第二导体群组包括经由所述第二内连线结构而彼此电性连接的多个第二导体；以及进行混合接合工艺以接合所述第一集成电路组件与所述第二集成电路组件，以使所述第一介电层接合至所述第二介电层，且所述多个第一导体接合至所述多个第二导体。
在一些实施例中，所述混合接合工艺包括：进行用于所述第一介电层与所述第二介电层之间的介电层接合的处理；以及进行用于所述多个第一导体与所述多个第二导体之间的导体接合的热退火。在一些实施例中，用于导体接合的所述热退火的工艺温度高于用于介电层接合的所述处理的工艺温度。在一些实施例中，在约摄氏100度至约摄氏150度的温度范围进行用于介电层接合所述第一介电层与所述第二介电层的所述处理。在一些实施例中，在约摄氏300度至约摄氏400度的温度范围进行用于导体接合的所述热退火。在一些实施例中，所述多个第一导体与所述多个第二导体之间的导体接合包括通孔对通孔接合、接垫对接垫接合或通孔对接垫接合。在一些实施例中，混合接合结构的制造方法还包括：单体化彼此混合接合的所述第一集成电路组件与所述第二集成电路组件，以形成经单体化的多个混合接合结构。
根据本揭露的一些实施例，提供混合接合结构的制造方法，包括下列步骤：提供第一集成电路组件，其中所述第一集成电路组件包括第一半导体衬底、第一内连线结构、第一介电层以及多个第一导体群组，所述第一半导体衬底包括位于其中的多个第一半导体器件，所述第一内连线结构设置于所述第一半导体衬底上并电性连接至所述第一半导体器件，所述第一介电层覆盖所述第一内连线结构，所述多个第一导体群组嵌入于所述第一介电层中并经由所述第一内连线结构而电性连接至所述第一半导体器件，且所述多个第一导体群组中的至少一第一导体群组包括彼此电性连接的多个第一导体；提供第二集成电路组件，其中所述第二集成电路组件包括第二半导体衬底、第二内连线结构、第二介电层以及多个第二导体群组，所述第二半导体衬底包括位于其中的多个第二半导体器件，所述第二内连线结构设置于所述第二半导体衬底上并电性连接至所述第二半导体器件，所述第二介电层覆盖所述第二内连线结构，所述多个第二导体群组嵌入于所述第二介电层中并经由所述第二内连线结构而电性连接至所述第二半导体器件，且所述多个第二导体群组中的至少一第二导体群组包括彼此电性连接的多个第二导体；进行混合接合工艺以接合所述第一集成电路组件与所述第二集成电路组件，以使所述第一介电层接合至所述第二介电层，且所述至少一第一导体群组电性连接至所述至少一第二导体群组，其中所述至少一第一导体群组、所述至少一第二导体群组、所述第一内连线结构以及所述第二内连线结构提供分流路径。
在一些实施例中，所述混合接合工艺包括：进行用于所述第一介电层与所述第二介电层之间的介电层接合的处理；进行用于所述多个第一导体与所述多个第二导体之间的导体接合的热退火。在一些实施例中，用于导体接合的所述热退火的工艺温度高于用于介电层接合的所述处理的工艺温度。在一些实施例中，在约摄氏100度至约摄氏150度的温度范围进行用于介电层接合所述第一介电层与所述第二介电层的所述处理。在一些实施例中，在约摄氏300度至约摄氏400度的温度范围进行用于导体接合的所述热退火。在一些实施例中，所述多个第一导体与所述多个第二导体之间的导体接合包括通孔对通孔接合、接垫对接垫接合或通孔对接垫接合。在一些实施例中，混合接合结构的制造方法还包括：单体化彼此混合接合的所述第一集成电路组件与所述第二集成电路组件，以形成经单体化的多个混合接合结构。
根据本揭露的一些实施例，提供包括第一集成电路芯片与第二集成电路芯片的混合接合结构。第一集成电路芯片包括其中具有多个第一半导体器件的第一半导体衬底、设置于所述第一半导体衬底上的第一内连线结构、覆盖所述第一内连线结构的第一介电层以及至少一第一导体群组，所述至少一第一导体群组包括经由所述第一内连线结构而彼此电性连接的多个第一导体。第二集成电路芯片包括其中具有多个第二半导体器件的第二半导体衬底、设置于所述第二半导体衬底上的第二内连线结构、覆盖所述第二内连线结构的第二介电层以及至少一第二导体群组，所述至少一第二导体群组包括经由所述第二内连线结构而彼此电性连接的多个第二导体。
在一些实施例中，所述多个第一导体包括导电通孔及/或导电接垫。在一些实施例中，所述至少一第一导体群组经由所述第一内连线结构中的第一分流走线而电性连接至所述多个第一半导体器件中的一者，所述至少一第二导体群组经由所述第二内连线结构中的第二分流走线而电性连接至所述多个第二半导体器件中的一者，以使所述第一分流走线、所述第二分流走线、所述多个第一导体与所述多个第二导体提供所述第一集成电路芯片与所述第二集成电路芯片中的分流路径。在一些实施例中，混合接合结构还包括多个隔离结构，其中所述隔离结构与所述多个第一导体电性绝缘，且所述隔离结构环绕所述多个第一导体。在一些实施例中，所述多个隔离结构为电性浮置且彼此分离。在一些实施例中，所述第一集成电路芯片为影像感测芯片，且所述第二集成电路芯片为逻辑集成电路芯片。
前文概述若干实施例的特征，使得熟习此项技术者可更佳地理解本揭露的态样。熟习此项技术者应理解，其可易于使用本揭露作为设计或修改用于实现本文中所引入的实施例的相同目的及/或达成相同优势的其他处理程序及结构的基础。熟习此项技术者亦应认识到，此类等效构造并不脱离本揭露的精神及范畴，且熟习此项技术者可在不脱离本揭露的精神及范畴的情况下在本文中进行改变、替代及更改。

Claims (12)

1.一种混合接合结构的制造方法，其特征在于，包括：
提供第一集成电路组件，其中所述第一集成电路组件包括其中具有多个第一半导体器件的第一半导体衬底、设置于所述第一半导体衬底上的第一内连线结构、覆盖所述第一内连线结构的第一介电层以及至少一第一导体群组，所述至少一第一导体群组包括经由所述第一内连线结构而彼此电性连接的多个第一导体；
提供第二集成电路组件，其中所述第二集成电路组件包括其中具有多个第二半导体器件的第二半导体衬底、设置于所述第二半导体衬底上的第二内连线结构、覆盖所述第二内连线结构的第二介电层以及至少一第二导体群组，所述至少一第二导体群组包括经由所述第二内连线结构而彼此电性连接的多个第二导体；以及
进行混合接合工艺以接合所述第一集成电路组件与所述第二集成电路组件，以使所述第一介电层接合至所述第二介电层，且所述多个第一导体接合至所述多个第二导体。
2.根据权利要求1所述的混合接合结构的制造方法，其特征在于，所述混合接合工艺包括：
进行用于所述第一介电层与所述第二介电层之间的介电层接合的处理；以及
进行用于所述多个第一导体与所述多个第二导体之间的导体接合的热退火。
3.根据权利要求2所述的混合接合结构的制造方法，其特征在于，用于导体接合的所述热退火的工艺温度高于用于介电层接合的所述处理的工艺温度。
4.根据权利要求2所述的混合接合结构的制造方法，其特征在于，
在摄氏100度至摄氏150度的温度范围进行用于介电层接合所述第一介电层与所述第二介电层的所述处理；或
在摄氏300度至摄氏400度的温度范围进行用于导体接合的所述热退火。
5.根据权利要求1所述的混合接合结构的制造方法，其特征在于，所述多个第一导体与所述多个第二导体之间的导体接合包括通孔对通孔接合、接垫对接垫接合或通孔对接垫接合。
6.根据权利要求1所述的混合接合结构的制造方法，其特征在于，还包括：
单体化彼此混合接合的所述第一集成电路组件与所述第二集成电路组件，以形成经单体化的多个混合接合结构。
7.一种混合接合结构的制造方法，其特征在于，包括：
提供第一集成电路组件，其中所述第一集成电路组件包括第一半导体衬底、第一内连线结构、第一介电层以及多个第一导体群组，所述第一半导体衬底包括位于其中的多个第一半导体器件，所述第一内连线结构设置于所述第一半导体衬底上并电性连接至所述第一半导体器件，所述第一介电层覆盖所述第一内连线结构，所述多个第一导体群组嵌入于所述第一介电层中并经由所述第一内连线结构而电性连接至所述第一半导体器件，且所述多个第一导体群组中的至少一第一导体群组包括彼此电性连接的多个第一导体；
提供第二集成电路组件，其中所述第二集成电路组件包括第二半导体衬底、第二内连线结构、第二介电层以及多个第二导体群组，所述第二半导体衬底包括位于其中的多个第二半导体器件，所述第二内连线结构设置于所述第二半导体衬底上并电性连接至所述第二半导体器件，所述第二介电层覆盖所述第二内连线结构，所述多个第二导体群组嵌入于所述第二介电层中并经由所述第二内连线结构而电性连接至所述第二半导体器件，且所述多个第二导体群组中的至少一第二导体群组包括彼此电性连接的多个第二导体；
进行混合接合工艺以接合所述第一集成电路组件与所述第二集成电路组件，以使所述第一介电层接合至所述第二介电层，且所述至少一第一导体群组电性连接至所述至少一第二导体群组，其中所述至少一第一导体群组、所述至少一第二导体群组、所述第一内连线结构以及所述第二内连线结构提供分流路径。
8.一种混合接合结构，其特征在于，包括：
第一集成电路芯片，包括其中具有多个第一半导体器件的第一半导体衬底、设置于所述第一半导体衬底上的第一内连线结构、覆盖所述第一内连线结构的第一介电层以及至少一第一导体群组，所述至少一第一导体群组包括经由所述第一内连线结构而彼此电性连接的多个第一导体；以及
第二集成电路芯片，包括其中具有多个第二半导体器件的第二半导体衬底、设置于所述第二半导体衬底上的第二内连线结构、覆盖所述第二内连线结构的第二介电层以及至少一第二导体群组，所述至少一第二导体群组包括经由所述第二内连线结构而彼此电性连接的多个第二导体。
9.根据权利要求8所述的混合接合结构，其特征在于，所述至少一第一导体群组经由所述第一内连线结构中的第一分流走线而电性连接至所述多个第一半导体器件中的一者，所述至少一第二导体群组经由所述第二内连线结构中的第二分流走线而电性连接至所述多个第二半导体器件中的一者，以使所述第一分流走线、所述第二分流走线、所述多个第一导体与所述多个第二导体提供所述第一集成电路芯片与所述第二集成电路芯片中的分流路径。
10.根据权利要求8所述的混合接合结构，其特征在于，还包括多个隔离结构，其中所述隔离结构与所述多个第一导体电性绝缘，且所述隔离结构环绕所述多个第一导体。
11.根据权利要求10所述的混合接合结构，其特征在于，所述多个隔离结构为电性浮置且彼此分离。
12.根据权利要求8所述的混合接合结构，其特征在于，所述第一集成电路芯片为影像感测芯片，且所述第二集成电路芯片为逻辑集成电路芯片。
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