TWI641094B - 基板結構及其製法 - Google Patents

基板結構及其製法 Download PDF

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TWI641094B
TWI641094B TW103132038A TW103132038A TWI641094B TW I641094 B TWI641094 B TW I641094B TW 103132038 A TW103132038 A TW 103132038A TW 103132038 A TW103132038 A TW 103132038A TW I641094 B TWI641094 B TW I641094B
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Taiwan
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layer
substrate structure
insulating layer
wiring
carrier
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TW103132038A
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English (en)
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TW201613045A (en
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張辰安
孫崧桓
吳建宏
陳以婕
廖文楷
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矽品精密工業股份有限公司
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Priority to TW103132038A priority Critical patent/TWI641094B/zh
Priority to CN201410612179.6A priority patent/CN105633053B/zh
Priority to US14/667,795 priority patent/US9877386B2/en
Publication of TW201613045A publication Critical patent/TW201613045A/zh
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Abstract

一種基板結構，係包括：定義有複數佈線區之承載件、設於各該佈線區之部分表面上之第一絕緣層、設於各該佈線區上之該第一絕緣層上之一線路層、以及設於該佈線區上之第二絕緣層，藉由縮小該第一與第二絕緣層之佈設面積，以減少該承載件與該絕緣層間之接觸面積及熱膨脹係數差異，使該基板結構不易發生翹曲。本發明復提供該基板結構之製法。

Description

基板結構及其製法
本發明係有關一種基板結構，尤指一種提升可靠度之基板結構及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)或多晶片模組封裝(Multi-Chip Module,MCM)等覆晶型態的封裝模組、或將晶片立體堆疊化整合為三維積體電路(3D IC)晶片堆疊技術等。
目前習知3D晶片堆疊之半導體封裝件，係提供一矽中介板(Through Silicon interposer,TSI)，該矽中介板具有貫穿之複數導電矽穿孔(Through-silicon via,TSV)，且該該板之一側具有一線路重佈層(Redistribution layer，簡稱RDL)，以於該線路重佈層上電性結合間距較小之半導體晶片之電極墊，再於該板之另一側上電性結合間距較大之封裝基板之銲墊。
如第1圖所示，習知矽中介板之基板結構1係包括一 承載件10、設於該承載件10全部表面上之第一絕緣層11、設於該第一絕緣層11上之一線路層13、設於該線路層13與該第一絕緣層11上並外露部分該線路層13之第二絕緣層12、以及設於該線路層13上之導電元件14。
第1A至1E圖係為第1圖之製法之上視示意圖。
如第1及1A圖所示，提供一如矽晶圓之承載件10，且於該承載件10上設有電性連接墊101。
如第1B圖所示，形成一第一絕緣層11於該承載件10之全部表面上，且該第一絕緣層11外露該電性連接墊101之部分表面。
如第1C圖所示，形成一如RDL之線路層13於該第一絕緣層11上，且該線路層13電性連接該電性連接墊101。
如第1D圖所示，形成一第二絕緣層12於該線路層13與該第一絕緣層11上，且該第二絕緣層12外露該線路層13之部分表面。
如第1E圖所示，先形成凸塊底下金屬層(Under bump metallurgy，簡稱UBM)15於該線路層13之外露表面上，再形成如銲錫凸塊之導電元件14於該凸塊底下金屬層15上。
惟，習知基板結構1之製法中，該承載件10與該第一絕緣層11兩者之接觸面積極大，且兩者之熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)差異極大，故於進行熱處理製程期間(thermal cycle)，該基板結構1難以均勻釋放熱應力(thermal stress)，導致該基板結構1容 易發生翹曲(warpage)之問題，且該導電元件14之應力可靠性(reliability)不佳，因而造成難以載運該基板結構1或無法進行後續製程。
因此，如何克服習知技術之種種缺失，實為一重要課題。
為克服習知技術之種種缺失，本發明係提供一種基板結構，係包括：一承載件，其定義有複數佈線區；第一絕緣層，係形成於各該佈線區之部分表面上；以及一線路層，係形成於各該佈線區上之該第一絕緣層上。
本發明復提供一種基板結構之製法，係包括：提供一承載件，其定義有複數佈線區；形成第一絕緣層於各該佈線區之部分表面上；以及形成一線路層於各該佈線區上之該第一絕緣層上。
前述之基板結構及其製法中，該承載件係具有電性連接該線路層之電性連接墊。
前述之基板結構及其製法中，該承載件係具有介電層，以令該第一絕緣層形成於該介電層上。例如，該線路層復延伸於該介電層上。
前述之基板結構及其製法中，該些佈線區中之第一絕緣層係互不相連。
前述之基板結構及其製法中，復包括形成第二絕緣層 於各該佈線區之該線路層上，且該第二絕緣層具有外露部分該線路層之開孔。例如，該第一絕緣層僅形成於該佈線區中對應該開孔下方之位置上；或者，該些佈線區中之第二絕緣層係互不相連。
前述之基板結構及其製法中，復包括形成導電元件於該線路層上。例如，該第一絕緣層僅形成於該佈線區中對應該導電元件下方之位置上。
由上可知，本發明之基板結構及其製法，係藉由該第一與第二絕緣層僅形成於該承載件之部分表面上，故相較於習知技術，本發明於進行熱處理製程期間，該基板結構可有效釋放熱應力，因而該基板結構不易發生翹曲，且可提升該導電元件之應力可靠性。
1,2,2’‧‧‧基板結構
10,20‧‧‧承載件
101,201‧‧‧電性連接墊
11,21,21’‧‧‧第一絕緣層
12,22‧‧‧第二絕緣層
13,23‧‧‧線路層
14,24‧‧‧導電元件
15,25‧‧‧凸塊底下金屬層
200‧‧‧板體
202‧‧‧介電層
203‧‧‧開口
220‧‧‧開孔
230‧‧‧電性接觸墊
A,A’‧‧‧佈線區
a‧‧‧接點處
T‧‧‧階梯狀
第1圖係為習知基板結構之剖面示意圖；第1A至1E圖係為習知基板結構之製法之上視示意圖；第2A至2E圖係為本發明基板結構之製法之剖面示意圖；其中，第2C’及2E’圖係為第2C及2E圖之另一實施例；以及第3A至3E圖係為對應第2A至2E圖之上視示意圖；其中，第3C’圖係為第3C圖之另一實施例。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明基板結構2之製法之剖面示意圖，且第3A至3E圖係為對應第2A至2E圖之上視示意圖。於本實施例中，該基板結構2之製法係可以晶圓級(wafer level)製程進行。
如第2A及3A圖所示，提供一承載件20，該承載件20係具有一板體200、設於該板體200上之複數電性連接墊201、及設於該板體200與該些電性連接墊201上之介電層202，且該介電層202具有複數開口203，以令各該電性連接墊201對應外露於各該開口203。
於本實施例中，該板體200之種類繁多，例如，具矽穿孔(Through-silicon via，簡稱TSV)之中介板、矽中介板(Through Silicon interposer，簡稱TSI)或半導體晶片等半導體板材、或者該板體200之內部可包含另一介電層(圖略)、與內部線路(圖略)，且該內部線路可選擇性地電性連接該電性連接墊201。因此，該板體200之構造並無特別限制。
再者，形成該介電層202之材質係為氮化矽(SiNx)或氧化矽(SiO2)。
如第2B及3B圖所示，形成一第一絕緣層21於該介電層202之部分表面上。
於本實施例中，該介電層202之表面上可定義有複數佈線區A，且該佈線區A之範圍內包含一接點處a，以令該第一絕緣層21僅形成於該接點處a上，其中，該接點處a之範圍不會包含該電性連接墊201。
再者，該佈線區A係指後續線路層之佔用面積之形狀區域，且該接點處a係指該基板結構2用以外接其它電子裝置(如晶片、電路板等)之接點處。
又，該第一絕緣層21係為鈍化層(passivation layer)，且其材質係為光阻介電材(photosensitive dielectric material，簡稱PDM)、聚醯亞胺(polyimide，簡稱PI)、苯並環丁烯(Bis-Benzo-Cyclo-Butene，簡稱BCB)、聚對二唑苯(Polybenzoxazole，簡稱PBO)、環氧樹脂(epoxy)、矽膠等聚合物(polymer)材質。例如，該第一絕緣層21 之製程可先塗佈光阻介電材於該介電層202之全部表面上，再以曝光顯影方式移除多餘之光阻介電材，使剩餘之光阻介電材作為該第一絕緣層21。
如第2C及3C圖所示，形成一線路層23於該介電層202上並延伸至該第一絕緣層21上，使該線路層23部分接觸該第一絕緣層21而部分接觸該介電層202，且該線路層23復形成於該開口203中以電性連接該電性連接墊201。
於本實施例中，該線路層23對應該第一絕緣層21之處係呈現階梯狀T。
再者，該線路層23係為線路重佈層(Redistribution layer，簡稱RDL)。例如，該線路層23之製作方式係先濺鍍(sputtering)晶種層(seed layer)於該電性連接墊201、介電層202與該第一絕緣層21上，再利用黃光製程形成圖案化阻層，之後於圖案化阻層之開口區中電鍍如銅材之金屬層，最後移除該阻層及其下之晶種層，以令該金屬層與剩餘之晶種層作為該線路層23。其中，該黃光製程意指塗佈光阻、曝光該光阻、該光阻顯影、蝕刻移除該阻層等步驟。
於另一實施例中，如第2C’及3C’圖所示，該第一絕緣層21’係沿該佈線區A’形成者，故該線路層23僅接觸形成於該第一絕緣層21’上而未接觸該介電層202。具體地，該佈線區A,A’之範圍依線路層23之佔用面積而改變，故不同實施例之佈線區A,A’之範圍可不相同。
如第2D及3D圖所示，形成一第二絕緣層22於該佈 線區A上，以令該第二絕緣層22覆蓋該線路層23與該第一絕緣層21。
於本實施例中，該第二絕緣層22具有外露部分該線路層23之複數開孔220，且該開孔220中之線路層23係作為電性接觸墊230。
再者，該開孔220之位置係位於該接點處a上。
又，該第二絕緣層22係為鈍化層，且其材質係為光阻介電材(PDM)、聚醯亞胺(polyimide，簡稱PI)、苯並環丁烯(Bis-Benzo-Cyclo-Butene，簡稱BCB)、聚對二唑苯(Polybenzoxazole，簡稱PBO)、環氧樹脂(epoxy)、矽膠等聚合物(polymer)材質。例如，該第二絕緣層22之製程可先塗佈光阻介電材覆蓋該介電層202之全部外露表面、該線路層23之全部外露表面與該第一絕緣層21之全部外露表面上，再以曝光顯影方式移除多餘之光阻介電材，使剩餘之光阻介電材作為該第二絕緣層22。
另外，該第二絕緣層22之材質可相同或不同於該第一絕緣層21之材質。
如第2E及3E圖所示，形成如銲錫材料之導電元件24於該開孔220中之電性接觸墊230上，以令該導電元件24電性連接該線路層23。
於本實施例中，該接點處a亦可表示為該導電元件24之約略形成位置。
再者，可選擇性先形成凸塊底下金屬層(Under bump metallurgy，簡稱UBM)25於該電性接觸墊 230上，再形成該導電元件24於該凸塊底下金屬層上。
又，若接續第2C’圖之製程，將得到如第2E’圖所示之基板結構2，，其中，第2E’圖之上視圖如第3E圖所示。
本發明之製法藉由以極小面積佈設該第一與第二絕緣層21,22，即該第一絕緣層21僅設於該佈線區A，且該第二絕緣層22僅沿該線路層23之形成區域(即該佈線區A)作佈設，以縮小絕緣層之佈設面積，故能大幅減少該承載件20與該絕緣層兩者之接觸面積，且大幅縮小兩者之熱膨脹係數(CTE)之差異，因而能將該基板結構2之翹曲幅度降至最小，並可提升該導電元件24之應力可靠性。
本發明復提供一種基板結構2,2’，係包括：一承載件20、第一絕緣層21,21’、一線路層23以及第二絕緣層22。
所述之承載件20係具有電性連接該線路層23之電性連接墊201，且該承載件20定義有至少一佈線區A,A’，其中，該佈線區A,A’係位於該承載件20之部分表面，且該佈線區A,A’包含接點處a。
所述之第一絕緣層21,21’係僅設於該承載件20之佈線區A,A’上。
所述之線路層23係設於該佈線區A,A’上之第一絕緣層21,21’上。
所述之第二絕緣層22係僅設於該佈線區A上(即沿該線路層23之形成區域作佈設)，以令該第二絕緣層22覆蓋該線路層23與該第一絕緣層21,21’。
於一實施例中，該承載件20係具有一介電層202，以 令該第一絕緣層21、線路層23與第二絕緣層22形成於該介電層202上。
於一實施例中，該第一絕緣層21係僅設於該接點處a上，使該線路層23對應該第一絕緣層21之處係呈現階梯狀T，例如，該電性接觸墊230接觸該第一絕緣層21上，而該線路層23之其它部分則接觸該承載件20上。
於一實施例中，該第二絕緣層22具有外露部分該線路層23之開孔220，且該開孔220之位置係位於該接點處a上，又該基板結構2,2’復包括設於該開孔220中並電性連接該線路層23之導電元件24。
綜上所述，本發明之基板結構及其製法，主要藉由縮小該第一與第二絕緣層之佈設面積，以減少該承載件與該絕緣層兩者之接觸面積及兩者間之熱膨脹係數差異，故該基板結構不易發生翹曲，且能提升該導電元件之應力可靠性。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (14)

  1. 一種基板結構，係包括：一承載件，其定義有複數佈線區；第一絕緣層，係設於各該佈線區之部分表面上；一線路層，係設於各該佈線區上之該第一絕緣層上；第二絕緣層，係設於各該佈線區之該線路層上，該第二絕緣層具有外露部分該線路層之開孔，以令該開孔中之該線路層作為電性接觸墊，其中，該第一絕緣層僅設於該佈線區中對應該開孔下方之位置上，且填滿該開孔的投影面積；以及凸塊底下金屬層，係形成於該電性接觸墊上。
  2. 如申請專利範圍第1項所述之基板結構，其中，該承載件係具有電性連接該線路層之電性連接墊。
  3. 如申請專利範圍第1項所述之基板結構，其中，該承載件係具有介電層，以令該第一絕緣層設於該介電層上。
  4. 如申請專利範圍第3項所述之基板結構，其中，該線路層復延伸於該介電層上。
  5. 如申請專利範圍第1項所述之基板結構，其中，該些佈線區中之第一及/或第二絕緣層係互不相連。
  6. 如申請專利範圍第1項所述之基板結構，復包括設於該凸塊底下金屬層上之導電元件。
  7. 如申請專利範圍第6項所述之基板結構，其中，該第一絕緣層僅設於該佈線區中對應該導電元件下方之位置上。
  8. 一種基板結構之製法，係包括：提供一承載件，其定義有複數佈線區；形成第一絕緣層於各該佈線區之部分表面上；形成一線路層於各該佈線區上之該第一絕緣層上；以及形成第二絕緣層於各該佈線區之該線路層上，該第二絕緣層具有外露部分該線路層之開孔，以令該開孔中之該線路層作為電性接觸墊，其中，該第一絕緣層僅形成於該佈線區中對應該開孔下方之位置上，且填滿該開孔的投影面積；以及形成凸塊底下金屬層於該電性接觸墊上。
  9. 如申請專利範圍第8項所述之基板結構之製法，其中，該承載件係具有電性連接該線路層之電性連接墊。
  10. 如申請專利範圍第8項所述之基板結構之製法，其中，該承載件係具有介電層，以令該第一絕緣層形成於該介電層上。
  11. 如申請專利範圍第10項所述之基板結構之製法，其中，該線路層復延伸於該介電層上。
  12. 如申請專利範圍第8項所述之基板結構之製法，其中，該些佈線區中之第一及/或第二絕緣層係互不相連。
  13. 如申請專利範圍第8項所述之基板結構之製法，復包括形成導電元件於該凸塊底下金屬層上。
  14. 如申請專利範圍第13項所述之基板結構之製法，其中，該第一絕緣層僅形成於該佈線區中對應該導電元件下方之位置上。
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