TW201630130A - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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Publication number
TW201630130A
TW201630130A TW104104027A TW104104027A TW201630130A TW 201630130 A TW201630130 A TW 201630130A TW 104104027 A TW104104027 A TW 104104027A TW 104104027 A TW104104027 A TW 104104027A TW 201630130 A TW201630130 A TW 201630130A
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Taiwan
Prior art keywords
layer
package structure
conductive
dielectric layer
forming
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TW104104027A
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English (en)
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TWI654723B (zh
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程呂義
呂長倫
陳仕卿
馬光華
蕭承旭
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矽品精密工業股份有限公司
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Priority to TW104104027A priority Critical patent/TWI654723B/zh
Priority to CN201510180602.4A priority patent/CN106158673A/zh
Priority to US14/986,149 priority patent/US10242972B2/en
Publication of TW201630130A publication Critical patent/TW201630130A/zh
Application granted granted Critical
Publication of TWI654723B publication Critical patent/TWI654723B/zh

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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
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Abstract

一種封裝結構及其製法，該封裝結構包括一具有相對第一表面及第二表面之介電層；形成於該介電層中之線路層；一設於該介電層第一表面上之電子元件，且令該電子元件電性連接至該線路層；複數設於該介電層第一表面上之導電柱，且令該導電柱電性連接至該線路層；以及一形成於該介電層第一表面上且包覆該電子元件及導電柱之封裝膠體，且令該導電柱上表面外露出該封裝膠體，以供後續得於該封裝膠體上接置其它電子元件，並透過該導電柱電性連接至線路層，解決習知封裝結構僅能朝下接置其他電子元件所導致功能受限問題。

Description

封裝結構及其製法
本發明係關於封裝結構及其製法，特別是關於一種堆疊之半導體封裝結構及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，例如晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)或多晶片模組封裝(Multi-Chip Module,MCM)等覆晶型態的封裝模組。
然而在覆晶封裝製程中，由於晶片與線路基板之熱膨脹係數差異大，因此晶片外圍的凸塊無法與線路基板上對應的接點形成良好的接合，使得凸塊可能自線路基板上剝離。另一方面，隨著積體電路之積集度的增加，由於晶片與線路基板之間的熱膨脹係數不匹配(mismatch)，其所產生的熱應力(thermal stress)與翹曲(warpage)的現象也日漸嚴重，其結果將導致晶片與線路基板之間的電性連接可靠度(reliability)下降，並且造成信賴性測試的失敗。
為了解決上述問題，業界遂發展出採用半導體基材製 作線路基板的半導體堆疊結構，俾透過半導體基材與晶片的材質接近，避免熱膨脹係數不匹配所產生的問題。
請參閱第1圖，該半導體堆疊結構係於一封裝基板18與半導體晶片11之間設置一矽中介板(Through Silicon interposer,TSI)10，該矽中介板10具有矽導通孔(Through-silicon via,TSV)100及設於該矽導通孔100上之線路重佈結構(Redistribution layer,RDL)15，令該線路重佈結構15藉由複數導電元件17電性結合間距較大之封裝基板18之銲墊180，並形成黏著材12包覆該些導電元件17，而間距較小之半導體晶片11之電極墊110係藉由複數銲錫凸塊19電性結合該矽導通孔100。之後，再形成黏著材12包覆該些銲錫凸塊19。
前述該具有矽中介板之3D半導體堆疊結構除了可避免熱膨脹係數不匹配所產生的問題外，該結構亦具有相較習知直接將半導體晶片接置於線路基板之封裝結構面積更加縮小，例如一般線路基板最小之線寬/線距只可做到12/12μm，而當半導體晶片IO數增加時，以現有之線路基板之線寬/線距並無法再縮小，故須加大線路基板面積以提高布線密度，方可接置高IO數之半導體晶片。而如第1圖之結構，由於將半導體晶片接置於一具有矽導通孔(TSV)之矽中介板(TSI)上，經由該TSI當作一轉接板，以將半導體晶片電性連接至線路基板上，此乃因為TSI可以半導體製程做出3/3μm或以下之線寬/線距，故當半導體晶片高IO數時，該矽中介板面積已足夠連接高IO數之半導體晶 片。且由於該矽中介板之細線寬/線距特性(電性傳輸距離短)，因此連接於TSI之半導體晶片其電性傳輸速度，亦較半導體晶片直接接置於線路基板之速度快。
惟該具有矽中介板之3D半導體堆疊結構之製作成本過高，故目前業界積極開發不具有矽中介板，且體積比具矽中介板之3D半導體堆疊結構更小之封裝結構，於此業界開發出無矽基材之線路互連封裝技術(Si Less Interconnect Technology)，其製作流程如下所示。
如第2A圖所示，首先形成一第一介電層21於一承載板20上，且該第一介電層21形成有複數外露該承載板20之開孔。接著，形成一線路層22於該第一介電層21上。 再形成第二介電層23於該第一介電層21與該線路層22上，且該第二介電層23形成有複數外露該線路層22之開孔。之後，形成導電凸塊24於該第二介電層23開口中，令該導電凸塊24電性連接該線路層22。
如第2B圖所示，結合一半導體晶片25於該導電凸塊24上，並形成底膠26於該半導體晶片25與該第二介電層23之間，以及形成封裝膠體27於該第二介電層23上，以包覆該半導體晶片25與底膠26。
如第2C圖所示，移除該承載板20，以露出該線路層22。接著，形成導電元件28於該露出之線路層22上，如此即可實現無矽中介板且封裝體積較習知小之封裝結構，並可藉由該導電元件28使該封裝結構與外部電子元件電性連接。
然而前述封裝結構僅能朝下接置其他之電子元件(如電路板、封裝基板或印刷電路板等)，其元件功能大受限制，故終端應用功能大幅降低，故無法符合現在終端產品需求。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種封裝結構之製法，係包括：形成一第一介電層於一承載板上，且於該第一介電層形成複數第一開孔，以外露該承載板之部分表面；形成一第一金屬層於該第一介電層之全部表面與該第一開孔中；形成第一阻層於該第一金屬層上，且於該第一阻層形成複數開口，以外露該第一金屬層之部分表面與該些第一開孔中之第一金屬層；形成線路層於該些開口中之第一金屬層上；移除該第一阻層及其下方之第一金屬層；形成第二介電層於該第一介電層與該線路層上，且於該第二介電層形成複數第二開孔，以外露該線路層之部分表面；形成第二金屬層於該第二介電層之全部表面與該第二開孔中；形成第二阻層於該第二金屬層上，且於該第二阻層中形成複數開口，以外露該第二開孔及其周圍之第二金屬層之表面；形成導電凸塊於該些開口中之第二金屬層上，令該導電凸塊電性連接該線路層；移除該第二阻層；形成第三阻層於該第二金屬層及該導電凸塊上，且於該第三阻層中形成複數開口，以外露部分該第二金屬層；形成 導電柱於該些開口中之第二金屬層上，並令該導電柱電性連接該線路層；移除該第三阻層及其下方之第二金屬層，以外露出該導電凸塊；結合一電子元件於該導電凸塊上；以及於該第二介電層上形成一包覆該導電柱及電子元件之封裝膠體，且令該導電柱上表面外露出該封裝膠體。
本發明之封裝結構之製法復包括：於該封裝膠體及導電柱上形成一電性連接該導電柱之線路增層結構；移除該承載板，以使部分該線路層上之第一金屬層外露出第一介電層；以及在外露之第一金屬層上形成導電元件。
另外可透過該導電元件接置並電性連接一例如電路板之外部裝置，同時可供另一電子元件透過一導電材料接置並電性連接至該線路增層結構。
透過前述製程，本發明復揭示一種封裝結構，係包括：一具有相對之第一表面及第二表面之介電層；形成於該介電層中之線路層；一設於該介電層第一表面上之電子元件，且令該電子元件電性連接至該線路層；複數設於該介電層第一表面上之導電柱，且令該導電柱電性連接至該線路層；以及一形成於該介電層第一表面上且包覆該電子元件及導電柱之封裝膠體，且令該導電柱上表面外露出該封裝膠體。
本發明之封裝結構復包括：一形成於該封裝膠體上之線路增層結構，且令該線路增層結構電性連接至該導電柱。
該封裝結構復可包括複數形成於該介電層第二表面之導電元件，且令該導電元件電性連接至該線路層。該封 裝結構另可包括至少一接置於該線路增層結構上之電子元件。
因此，本發明之封裝結構及其製法主要藉由形成複數外露出封裝膠體之導電柱，亦或進一步於該封裝膠體上形成電性連接該導電柱之線路增層結構，以令該些導電柱向上電性連接線路增層結構，向下電性連接線路層，而可於該封裝結構上方接置有其他電子元件，如晶片或其他封裝結構，如此即可解決習知結構僅能朝下接置其他之電子元件(如電路板-封裝機板或印刷電路板等)所導致封裝結構功能受限問題，達到符合現今終端產品多功能需求目標。
10‧‧‧矽中介板
100‧‧‧矽導通孔
11‧‧‧半導體晶片
110‧‧‧電極墊
12‧‧‧黏著材
15‧‧‧線路重佈結構
17‧‧‧導電元件
18‧‧‧封裝基板
180‧‧‧銲墊
19‧‧‧銲錫凸塊
20‧‧‧承載板
21‧‧‧第一介電層
22‧‧‧線路層
23‧‧‧第二介電層
24‧‧‧導電凸塊
25‧‧‧半導體晶片
26‧‧‧底膠
27‧‧‧封裝膠體
28‧‧‧導電元件
30‧‧‧承載板
31‧‧‧第一介電層
310‧‧‧第一開孔
32‧‧‧第一金屬層
33a‧‧‧第一阻層
330a‧‧‧開口
34‧‧‧線路層
35‧‧‧第二介電層
350‧‧‧第二開孔
36‧‧‧第二金屬層
33b‧‧‧第二阻層
330b‧‧‧開口
37‧‧‧導電凸塊
33c‧‧‧第三阻層
330c‧‧‧開口
38‧‧‧導電柱
39‧‧‧電子元件
39a‧‧‧作用面
39b‧‧‧非作用面
390‧‧‧電極墊
37’‧‧‧銲接凸塊
391‧‧‧底膠
41‧‧‧封裝膠體
44‧‧‧線路增層結構
440‧‧‧增層介電層
441‧‧‧增層線路層
42‧‧‧絕緣保護層
40‧‧‧導電元件
3,3’‧‧‧封裝結構
43a,43b‧‧‧電子元件
430‧‧‧導電材料
31’‧‧‧介電層
31a’‧‧‧第一表面
31b’‧‧‧第二表面
第1圖係為習知半導體堆疊結構之剖面示意圖；第2A至2C圖係為習知半導體封裝結構之製法剖面示意圖；第3A至3M圖係為本發明之半導體封裝結構之製法第一實施例之剖面示意圖；以及第4A至4C圖係為本發明之半導體封裝結構之製法第二實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝 之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第3A至3M圖，係為本發明之封裝結構之製法第一實施例之剖面示意圖。
如第3A圖所示，以例如塗佈方式形成一第一介電層31於一承載板30上，且進行圖案化製程，於該第一介電層31上形成複數第一開孔310，以外露該承載板30之部分表面。
於本實施例中，該第一介電層31之材質係為聚亞醯胺(Polyimide,PI)、苯並環丁烯(Benezocy-clobutene,BCB)或聚對二唑苯(Polybenzoxazole,PBO)，且該承載板30係為矽晶圓、玻璃板、表面具鋁層之板體或鋁板，較佳為表面具濺鍍鋁層之矽晶圓，但該承載板30之種類僅需為剛性材質即可，並不限於上述。
如第3B圖所示，以濺鍍方式形成一第一金屬層32於該第一介電層31之全部表面與該第一開孔310中。
接著，以塗佈方式形成如光阻之第一阻層33a於該第一金屬層32上，且以曝光、顯影方式進行圖案化製程，於 該第一阻層33a形成複數開口330a，以外露該第一金屬層32之部分表面與該些第一開孔310中之第一金屬層32。
於本實施例中，該第一金屬層32可作為供電鍍用之導電層(seed layer)，且形成該第一金屬層32的材質為Ti、Cu、Ni、V、Al、W、Au或其組成，但不限於此。
如第3C圖所示，利用該第一金屬層32作為電流路徑，電鍍形成線路層34於該些開口330a中之第一金屬層32上。
於本實施例中，形成該線路層34之材質可為銅(Cu)或鋁(Al)等，但不限於此。
如第3D圖所示，剝除該第一阻層33a，且以如蝕刻之方式將該第一阻層33a下方之第一金屬層32移除。
如第3E圖所示，以例如塗佈方式形成第二介電層35於該第一介電層31與該線路層34上，且以曝光、顯影方式進行圖案化製程，於該第二介電層35上形成複數第二開孔350，以外露該線路層34之部分表面。
接著，以濺鍍方式形成第二金屬層36於該第二介電層35之全部表面與該第二開孔350中。
於本實施例中，形成該第二介電層35之材質係為聚亞醯胺(Polyimide,PI)、苯並環丁烯(Benezocy-clobutene,BCB)或聚對二唑苯(Polybenzoxazole,PBO)，且形成該第二金屬層36的材質為Ti、Cu、Ni、V、Al、W、Au或其組成，但該第二金屬層36的材質不限於此。
如第3F圖所示，以塗佈方式形成如光阻之第二阻層 33b於該第二金屬層36上，且以曝光、顯影方式進行圖案化製程，於該第二阻層33b中形成複數開口330b，以外露該第二開孔350及其周圍之第二金屬層36之表面。
接著，利用該第二金屬層36作為電鍍用之電流途徑，以電鍍形成導電凸塊37於該些開口330b中之第二金屬層36上，令該導電凸塊37電性連接該線路層34。
於本實施例中，該導電凸塊37係含有銲錫材料，如錫銀(Sn-Ag)無鉛銲料，且該銲錫材料中亦可含有Cu、Ni或Ge等，但該導電凸塊37之材質無特別限制。又該第二金屬層36可作為凸塊底下金屬(Under Bump Metallurgy,UBM)。
如第3G圖所示，剝除該第二阻層33b，以外露該第二金屬層36。請注意，於本步驟中並未移除該第二阻層33b所覆蓋之第二金屬層36部分。
如第3H圖所示，以塗佈方式形成如光阻之第三阻層33c於該第二金屬層36及該導電凸塊37上，且以曝光、顯影方式進行圖案化製程，於該第三阻層33c中形成複數開口330c，以外露部分該第二金屬層36。
接著利用該第二金屬層36作為電鍍用之電流途徑，以電鍍形成導電柱38於該些開口330c中之第二金屬層36上，並令該導電柱38電性連接該線路層34，其中該導電柱38係設於該導電凸塊37之外圍。
如第3I圖所示，剝除該第三阻層33c，且以如蝕刻之方式將該第三阻層33c下方之第二金屬層36移除，以外露 出該導電凸塊37。
接著結合一電子元件39於該導電凸塊37上，該電子元件39具有作用面39a與相對該作用面39a之非作用面39b。
於本實施例中，該電子元件39之作用面39a上具有電極墊390，且可選擇性地於該電極墊390上形成銲錫材料，以藉由迴銲製程，結合導電凸塊37形成銲接凸塊37’，令該電子元件39固設於該第二介電層35上。另外可選擇性形成包覆該銲接凸塊37’之底膠391於該電子元件39與該第二介電層35之間。該電子元件39可為例如半導體晶片之主動元件亦或其它被動元件。
如第3J圖所示，於該第二介電層35上形成一包覆該導電柱38及電子元件39之封裝膠體41。
如第3K圖所示，利用研磨等方式薄化該封裝膠體41，以外露出該導電柱38上表面，亦可選擇同時外露出該電子元件39之非作用面39b，令該封裝膠體41之頂面與該電子元件39之非作用面39b及導電柱38上表面齊平。
如第3L圖所示，移除該承載板30，以使部分該線路層34上之第一金屬層32外露出第一介電層31。
接著可在外露之第一金屬層32上形成導電元件40，以形成一封裝結構3。
於本實施例中，該導電元件40可為銲球、凸塊或導針等，且可令該第一金屬層32作為凸塊底下金屬(Under Bump Metallurgy,UBM)。
如第3M圖所示，後續即可將該封裝結構3透過該導電元件40接置並電性連接至一例如電路板之電子元件43b，同時可供另一電子元件43a(例如半導體晶片或封裝件)透過一導電材料430接置並電性連接至外露出該封裝膠體41之導電柱38。
請參閱第4A至4C圖，係為本發明之半導體封裝結構之製法第二實施例之剖面示意圖。本實施例之半導體封裝結構之製法與前述第一實施例大致相同，以下僅說明差異處。
如第4A圖所示，係接續第一實施例之第3K圖，接著於該封裝膠體41及導電柱38上形成一線路增層結構44。 於本實施例中，該線路增層結構44具有至少一增層介電層440與形成於該增層介電層440上之增層線路層441，且該增層線路層441電性連接該導電柱38。另外該線路增層結構44亦可省略該增層介電層440，亦即在該封裝膠體41及導電柱38上僅形成增層線路層441。
之後於該線路增層結構44上形成一絕緣保護層42，並使該絕緣保護層42形成有複數外露出該增層線路層441之開孔。該絕緣保護層42例如為防銲層(solder mask)。
如第4B圖所示，移除該承載板30，以使部分該線路層34上之第一金屬層32外露出第一介電層31。
接著可在外露之第一金屬層32上形成導電元件40，以形成一封裝結構3’。
如第4C圖所示，後續即可將該封裝結構3’透過該導 電元件40接置並電性連接至一例如電路板之電子元件43b，同時可供另一電子元件43a(例如半導體晶片或封裝件)透過一導電材料430接置並電性連接至該線路增層結構44之增層線路層441。
透過前述製程，本發明復揭示一種封裝結構，係包括：由第一介電層31及第二介電層35構成之介電層31’，該介電層31’具有相對之第一表面31a’及第二表面31b’；形成於該介電層31’中之線路層34；一設於該介電層31’第一表面上31a’之電子元件39，且令該電子元件39電性連接至該線路層34；複數設於該介電層31’第一表面31a’上之導電柱38，且令該導電柱38電性連接至該線路層34；以及一形成於該介電層31’第一表面31a’上且包覆該電子元件39及導電柱38之封裝膠體41，且令該導電柱38上表面外露出該封裝膠體41。
該封裝結構復包括一形成於該封裝膠體41上之線路增層結構44，且令該線路增層結構44電性連接至該導電柱38。
該封裝結構復包括複數形成於該介電層31’第二表面31b’之導電元件40，且令該導電元件40電性連接至該線路層34。
該封裝結構另包括至少一接置於該線路增層結構44上之電子元件43a。
因此，本發明之封裝結構及其製法主要藉由形成複數外露出封裝膠體之導電柱，亦或進一步於該封裝膠體上形 成電性連接該導電柱之線路增層結構，以令該些導電柱向上電性連接線路增層結構，向下電性連接線路層，而可於該封裝結構上方接置有其他電子元件，如晶片或其他封裝結構，如此即可解決習知結構僅能朝下接置其他之電子元件(如電路板-封裝機板或印刷電路板等)所導致封裝結構功能受限問題，達到符合現今終端產品多功能需求目標。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
3‧‧‧封裝結構
31‧‧‧第一介電層
32‧‧‧第一金屬層
34‧‧‧線路層
35‧‧‧第二介電層
37’‧‧‧銲接凸塊
38‧‧‧導電柱
39‧‧‧電子元件
39a‧‧‧作用面
39b‧‧‧非作用面
40‧‧‧導電元件
41‧‧‧封裝膠體

Claims (29)

  1. 一種封裝結構之製法，係包括：提供一形成有線路層之介電層，且該介電層具有相對之第一表面及第二表面；於該介電層之第一表面上接置一電子元件，並使該電子元件電性連接至該線路層；於該介電層之第一表面上形成複數導電柱，並使該導電柱電性連接至線路層；以及於該介電層之第一表面上形成包覆該電子元件及導電柱之封裝膠體，並使該導電柱上表面外露出該封裝膠體。
  2. 如申請專利範圍第1項所述之封裝結構之製法，復包括於該封裝膠體上形成一線路增層結構，並使該線路增層結構電性連接至該導電柱。
  3. 如申請專利範圍第1或2項所述之封裝結構之製法，復包括：於該介電層第二表面形成複數電性連接該線路層之導電元件。
  4. 如申請專利範圍第3項所述之封裝結構之製法，其中，該些導電元件係供接置另一電子元件。
  5. 如申請專利範圍第1項所述之封裝結構之製法，復包括：於外露出該封裝膠體之該導電柱上接置另一電子元件。
  6. 如申請專利範圍第2項所述之封裝結構之製法，復包括：於該線路增層結構上接置另一電子元件。
  7. 如申請專利範圍第2項所述之封裝結構之製法，其中，該線路增層結構包含有增層線路層。
  8. 如申請專利範圍第7項所述之封裝結構之製法，復包括：於該線路增層結構上形成一絕緣保護層，並使該絕緣保護層形成有複數外露出該增層線路層之開孔。
  9. 如申請專利範圍第1項所述之封裝結構之製法，其中，該線路層在相對於該介電層之第一表面及第二表面上形成有第二金屬層及第一金屬層。
  10. 如申請專利範圍第9項所述之封裝結構之製法，其中，該第一金屬層及第二金屬層係為凸塊底下金屬(Under Bump Metallurgy,UBM)。
  11. 如申請專利範圍第1項所述之封裝結構之製法，其中，於該介電層之第一表面上接置該電子元件後，復包括，於該介電層及該電子元件間形成底膠。
  12. 如申請專利範圍第1項所述之封裝結構之製法，其中，該形成有線路層之介電層之製法係包括：形成一第一介電層於一承載板上，且於該第一介電層形成複數第一開孔，以外露該承載板之部分表面；形成一第一金屬層於該第一介電層之全部表面與該第一開孔中；形成第一阻層於該第一金屬層上，且於該第一阻層形成複數開口，以外露該第一金屬層之部分表面與該些第一開孔中之第一金屬層；形成線路層於該些開口中之第一金屬層上；以及 移除該第一阻層及其下方之第一金屬層。
  13. 如申請專利範圍第12項所述之封裝結構之製法，其中，該線路層上形成有複數導電凸塊，該複數導電凸塊之製法係包括：形成第二介電層於該第一介電層與該線路層上，且於該第二介電層形成複數第二開孔，以外露該線路層之部分表面；形成第二金屬層於該第二介電層之全部表面與該第二開孔中；形成第二阻層於該第二金屬層上，且於該第二阻層中形成複數開口，以外露該第二開孔及其周圍之第二金屬層之表面；形成導電凸塊於該些開口中之第二金屬層上，令該導電凸塊電性連接該線路層；以及移除該第二阻層。
  14. 如申請專利範圍第13項所述之封裝結構之製法，其中，該線路層上形成有複數導電柱，該複數導電柱之製法係包括：形成第三阻層於該第二金屬層及該導電凸塊上，且於該第三阻層中形成複數開口，以外露部分該第二金屬層；以及形成導電柱於該些開口中之第二金屬層上，並令該導電柱電性連接該線路層。
  15. 如申請專利範圍第14項所述之封裝結構之製法，其 中，線路層上形成有複數導電元件，該複數導電元件之製法係包括：移除該承載板，以使部分該線路層上之第一金屬層外露出第一介電層；以及在外露之第一金屬層上形成導電元件。
  16. 如申請專利範圍第1項所述之封裝結構之製法，其中，該介電層之第一表面形成有複數電性連接該線路層之導電凸塊，以供接置該電子元件。
  17. 如申請專利範圍第1項所述之封裝結構之製法，其中，於形成該封裝膠體後，復包括：薄化該封裝膠體，以外露出該導電柱上表面或同時外露出該導電柱上表面與該電子元件之表面。
  18. 一種封裝結構，係包括：一介電層，具有相對之第一表面及第二表面；一線路層，係形成於該介電層中；一電子元件，係設置於該介電層之第一表面上且電性連接至該線路層；複數導電柱，係形成於該介電層第一表面上且電性連接至該線路層；以及一封裝膠體，係形成於該介電層之第一表面上且包覆該電子元件及導電柱，並使該導電柱上表面外露出該封裝膠體。
  19. 如申請專利範圍第18項所述之封裝結構，復包括有一線路增層結構，係形成於該封裝膠體上且電性連接至 該導電柱。
  20. 如申請專利範圍第19項所述之封裝結構，復包括有一絕緣保護層，係形成於該線路增層結構上。
  21. 如申請專利範圍第19項所述之封裝結構，復包括有另一電子元件，係接置於該線路增層結構上。
  22. 如申請專利範圍第18項所述之封裝結構，其中，該介電層之第一表面形成有複數電性連接該線路層之導電凸塊，以供接置該電子元件。
  23. 如申請專利範圍第18項所述之封裝結構，復包括有複數導電元件，係形成於該介電層第二表面且電性連接至該線路層。
  24. 如申請專利範圍第23項所述之封裝結構，復包括有另一電子元件，係接置於該些導電元件上。
  25. 如申請專利範圍第18項所述之封裝結構，復包括有另一電子元件，係接置於外露出該封裝膠體之該導電柱上。
  26. 如申請專利範圍第18項所述之封裝結構，其中，該電子元件之上表面係外露出該封裝膠體。
  27. 如申請專利範圍第18項所述之封裝結構，其中，該線路層在相對於該介電層之第一表面及第二表面上形成有第二金屬層及第一金屬層。
  28. 如申請專利範圍第27項所述之封裝結構，其中，該第一金屬層及第二金屬層係為凸塊底下金屬(Under Bump Metallurgy,UBM)。
  29. 如申請專利範圍第18項所述之封裝結構，復包括有一底膠，係形成於該介電層及該電子元件間。
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