CN106158673A - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

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Publication number
CN106158673A
CN106158673A CN201510180602.4A CN201510180602A CN106158673A CN 106158673 A CN106158673 A CN 106158673A CN 201510180602 A CN201510180602 A CN 201510180602A CN 106158673 A CN106158673 A CN 106158673A
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layer
preparation
dielectric layer
encapsulating
electronic component
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CN201510180602.4A
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程吕义
吕长伦
陈仕卿
马光华
萧承旭
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN106158673A publication Critical patent/CN106158673A/zh
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Abstract

一种封装结构及其制法，该封装结构包括一具有相对第一表面及第二表面的介电层；形成于该介电层中的线路层；一设于该介电层第一表面上的电子元件，且令该电子元件电性连接至该线路层；多个设于该介电层第一表面上的导电柱，且令该导电柱电性连接至该线路层；以及一形成于该介电层第一表面上且包覆该电子元件及导电柱的封装胶体，且令该导电柱上表面外露出该封装胶体，以供后续得于该封装胶体上接置其它电子元件，并透过该导电柱电性连接至线路层，解决现有封装结构仅能朝下接置其他电子元件所导致功能受限问题。

Description

封装结构及其制法
技术领域
本发明涉及一种封装结构及其制法，特别是关于一种堆迭的半导体封装结构及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于晶片封装领域的技术，例如晶片尺寸构装(ChipScale Package,CSP)、晶片直接贴附封装(Direct Chip Attached,DCA)或多晶片模组封装(Multi－Chip Module,MCM)等覆晶型态的封装模组。
然而在覆晶封装制程中，由于晶片与线路基板的热膨胀系数差异大，因此晶片外围的凸块无法与线路基板上对应的接点形成良好的接合，使得凸块可能自线路基板上剥离。另一方面，随着积体电路的积集度的增加，由于晶片与线路基板之间的热膨胀系数不匹配(mismatch)，其所产生的热应力(thermal stress)与翘曲(warpage)的现象也日渐严重，其结果将导致晶片与线路基板之间的电性连接可靠度(reliability)下降，并且造成信赖性测试的失败。
为了解决上述问题，业界遂发展出采用半导体基材制作线路基板的半导体堆迭结构，以透过半导体基材与晶片的材质接近，避免热膨胀系数不匹配所产生的问题。
请参阅图1，该半导体堆迭结构通过于一封装基板18与半导体晶片11之间设置一硅中介板(Through Silicon interposer,TSI)10，该硅中介板10具有硅导通孔(Through-silicon via,TSV)100及设于该硅导通孔100上的线路重布结构(Redistribution layer,RDL)15，令该线路重布结构15藉由多个导电元件17电性结合间距较大的封装基板18的焊垫180，并形成粘着材12包覆该些导电元件17，而间距较小的半导体晶片11的电极垫110藉由多个焊锡凸块19电性结合该硅导通孔100。之后，再形成粘着材12包覆该些焊锡凸块19。
前述该具有硅中介板的3D半导体堆迭结构除了可避免热膨胀系数不匹配所产生的问题外，该结构也具有相较现有直接将半导体晶片接置于线路基板的封装结构面积更加缩小，例如一般线路基板最小的线宽/线距只可做到12/12μm，而当半导体晶片IO数增加时，以现有的线路基板的线宽/线距并无法再缩小，所以须加大线路基板面积以提高布线密度，方可接置高IO数的半导体晶片。而如图1的结构，由于将半导体晶片接置于一具有硅导通孔(TSV)的硅中介板(TSI)上，经由该TSI当作一转接板，以将半导体晶片电性连接至线路基板上，此乃因为TSI可以半导体制程做出3/3μm或以下的线宽/线距，所以当半导体晶片高IO数时，该硅中介板面积已足够连接高IO数的半导体晶片。且由于该硅中介板的细线宽/线距特性(电性传输距离短)，因此连接于TSI的半导体晶片其电性传输速度，也较半导体晶片直接接置于线路基板的速度快。
然而该具有硅中介板的3D半导体堆迭结构的制作成本过高，所以目前业界积极开发不具有硅中介板，且体积比具硅中介板的3D半导体堆迭结构更小的封装结构，于此业界开发出无硅基材的线路互连封装技术(Si Less Interconnect Technology)，其制作流程如下所示。
如图2A所示，首先形成一第一介电层21于一承载板20上，且该第一介电层21形成有多个外露该承载板20的开孔。接着，形成一线路层22于该第一介电层21上。再形成第二介电层23于该第一介电层21与该线路层22上，且该第二介电层23形成有多个外露该线路层22的开孔。之后，形成导电凸块24于该第二介电层23开口中，令该导电凸块24电性连接该线路层22。
如图2B所示，结合一半导体晶片25于该导电凸块24上，并形成底胶26于该半导体晶片25与该第二介电层23之间，以及形成封装胶体27于该第二介电层23上，以包覆该半导体晶片25与底胶26。
如图2C所示，移除该承载板20，以露出该线路层22。接着，形成导电元件28于该露出的线路层22上，如此即可实现无硅中介板且封装体积较现有小的封装结构，并可藉由该导电元件28使该封装结构与外部电子元件电性连接。
然而前述封装结构仅能朝下接置其他的电子元件(如电路板、封装基板或印刷电路板等)，其元件功能大受限制，所以终端应用功能大幅降低，所以无法符合现在终端产品需求。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种封装结构及其制法，以解决现有封装结构仅能朝下接置其他电子元件所导致功能受限问题。
本发明的封装结构的制法，包括：形成一第一介电层于一承载板上，且于该第一介电层形成多个第一开孔，以外露该承载板的部分表面；形成一第一金属层于该第一介电层的全部表面与该第一开孔中；形成第一阻层于该第一金属层上，且于该第一阻层形成多个开口，以外露该第一金属层的部分表面与该些第一开孔中的第一金属层；形成线路层于该些开口中的第一金属层上；移除该第一阻层及其下方的第一金属层；形成第二介电层于该第一介电层与该线路层上，且于该第二介电层形成多个第二开孔，以外露该线路层的部分表面；形成第二金属层于该第二介电层的全部表面与该第二开孔中；形成第二阻层于该第二金属层上，且于该第二阻层中形成多个开口，以外露该第二开孔及其周围的第二金属层的表面；形成导电凸块于该些开口中的第二金属层上，令该导电凸块电性连接该线路层；移除该第二阻层；形成第三阻层于该第二金属层及该导电凸块上，且于该第三阻层中形成多个开口，以外露部分该第二金属层；形成导电柱于该些开口中的第二金属层上，并令该导电柱电性连接该线路层；移除该第三阻层及其下方的第二金属层，以外露出该导电凸块；结合一电子元件于该导电凸块上；以及于该第二介电层上形成一包覆该导电柱及电子元件的封装胶体，且令该导电柱上表面外露出该封装胶体。
本发明的封装结构的制法还包括：于该封装胶体及导电柱上形成一电性连接该导电柱的线路增层结构；移除该承载板，以使部分该线路层上的第一金属层外露出第一介电层；以及在外露的第一金属层上形成导电元件。
另外可透过该导电元件接置并电性连接一例如电路板的外部装置，同时可供另一电子元件透过一导电材料接置并电性连接至该线路增层结构。
透过前述制程，本发明还揭示一种封装结构，包括：一具有相对的第一表面及第二表面的介电层；形成于该介电层中的线路层；一设于该介电层第一表面上的电子元件，且令该电子元件电性连接至该线路层；多个设于该介电层第一表面上的导电柱，且令该导电柱电性连接至该线路层；以及一形成于该介电层第一表面上且包覆该电子元件及导电柱的封装胶体，且令该导电柱上表面外露出该封装胶体。
本发明的封装结构还包括：一形成于该封装胶体上的线路增层结构，且令该线路增层结构电性连接至该导电柱。
该封装结构还可包括多个形成于该介电层第二表面的导电元件，且令该导电元件电性连接至该线路层。该封装结构另可包括至少一接置于该线路增层结构上的电子元件。
因此，本发明的封装结构及其制法主要藉由形成多个外露出封装胶体的导电柱，抑或进一步于该封装胶体上形成电性连接该导电柱的线路增层结构，以令该些导电柱向上电性连接线路增层结构，向下电性连接线路层，而可于该封装结构上方接置有其他电子元件，如晶片或其他封装结构，如此即可解决现有结构仅能朝下接置其他的电子元件(如电路板-封装机板或印刷电路板等)所导致封装结构功能受限问题，达到符合现今终端产品多功能需求目标。
附图说明
图1为现有半导体堆迭结构的剖面示意图；
图2A至图2C为现有半导体封装结构的制法剖面示意图；
图3A至图3M为本发明的半导体封装结构的制法第一实施例的剖面示意图；以及
图4A至图4C为本发明的半导体封装结构的制法第二实施例的剖面示意图。
符号说明
10 硅中介板
100 硅导通孔
11 半导体晶片
110 电极垫
12 粘着材
15 线路重布结构
17 导电元件
18 封装基板
180 焊垫
19 焊锡凸块
20 承载板
21 第一介电层
22 线路层
23 第二介电层
24 导电凸块
25 半导体晶片
26 底胶
27 封装胶体
28 导电元件
30 承载板
31 第一介电层
310 第一开孔
32 第一金属层
33a 第一阻层
330a 开口
34 线路层
35 第二介电层
350 第二开孔
36 第二金属层
33b 第二阻层
330b 开口
37 导电凸块
33c 第三阻层
330c 开口
38 导电柱
39 电子元件
39a 作用面
39b 非作用面
390 电极垫
37’ 焊接凸块
391 底胶
41 封装胶体
44 线路增层结构
440 增层介电层
441 增层线路层
42 绝缘保护层
40 导电元件
3,3’ 封装结构
43a,43b 电子元件
430 导电材料
31’ 介电层
31a’ 第一表面
31b’ 第二表面。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等的用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图3A至图3M，其为本发明的封装结构的制法第一实施例的剖面示意图。
如图3A所示，以例如涂布方式形成一第一介电层31于一承载板30上，且进行图案化制程，于该第一介电层31上形成多个第一开孔310，以外露该承载板30的部分表面。
于本实施例中，该第一介电层31的材质为聚亚酰胺(Polyimide,PI)、苯并环丁烯(Benezocy-clobutene,BCB)或聚对二唑苯(Polybenzoxazole,PBO)，且该承载板30为硅晶圆、玻璃板、表面具铝层的板体或铝板，较佳为表面具溅镀铝层的硅晶圆，但该承载板30的种类仅需为刚性材质即可，并不限于上述。
如图3B所示，以溅镀方式形成一第一金属层32于该第一介电层31的全部表面与该第一开孔310中。
接着，以涂布方式形成如光阻的第一阻层33a于该第一金属层32上，且以曝光、显影方式进行图案化制程，于该第一阻层33a形成多个开口330a，以外露该第一金属层32的部分表面与该些第一开孔310中的第一金属层32。
于本实施例中，该第一金属层32可作为供电镀用的导电层(seedlayer)，且形成该第一金属层32的材质为Ti、Cu、Ni、V、Al、W、Au或其组成，但不限于此。
如图3C所示，利用该第一金属层32作为电流路径，电镀形成线路层34于该些开口330a中的第一金属层32上。
于本实施例中，形成该线路层34的材质可为铜(Cu)或铝(Al)等，但不限于此。
如图3D所示，剥除该第一阻层33a，且以如蚀刻的方式将该第一阻层33a下方的第一金属层32移除。
如图3E所示，以例如涂布方式形成第二介电层35于该第一介电层31与该线路层34上，且以曝光、显影方式进行图案化制程，于该第二介电层35上形成多个第二开孔350，以外露该线路层34的部分表面。
接着，以溅镀方式形成第二金属层36于该第二介电层35的全部表面与该第二开孔350中。
于本实施例中，形成该第二介电层35的材质为聚亚酰胺(Polyimide,PI)、苯并环丁烯(Benezocy-clobutene,BCB)或聚对二唑苯(Polybenzoxazole,PBO)，且形成该第二金属层36的材质为Ti、Cu、Ni、V、Al、W、Au或其组成，但该第二金属层36的材质不限于此。
如图3F所示，以涂布方式形成如光阻的第二阻层33b于该第二金属层36上，且以曝光、显影方式进行图案化制程，于该第二阻层33b中形成多个开口330b，以外露该第二开孔350及其周围的第二金属层36的表面。
接着，利用该第二金属层36作为电镀用的电流途径，以电镀形成导电凸块37于该些开口330b中的第二金属层36上，令该导电凸块37电性连接该线路层34。
于本实施例中，该导电凸块37含有焊锡材料，如锡银(Sn-Ag)无铅焊料，且该焊锡材料中也可含有Cu、Ni或Ge等，但该导电凸块37的材质无特别限制。又该第二金属层36可作为凸块底下金属(UnderBump Metallurgy,UBM)。
如图3G所示，剥除该第二阻层33b，以外露该第二金属层36。请注意，于本步骤中并未移除该第二阻层33b所覆盖的第二金属层36部分。
如图3H所示，以涂布方式形成如光阻的第三阻层33c于该第二金属层36及该导电凸块37上，且以曝光、显影方式进行图案化制程，于该第三阻层33c中形成多个开口330c，以外露部分该第二金属层36。
接着利用该第二金属层36作为电镀用的电流途径，以电镀形成导电柱38于该些开口330c中的第二金属层36上，并令该导电柱38电性连接该线路层34，其中该导电柱38设于该导电凸块37的外围。
如图3I所示，剥除该第三阻层33c，且以如蚀刻的方式将该第三阻层33c下方的第二金属层36移除，以外露出该导电凸块37。
接着结合一电子元件39于该导电凸块37上，该电子元件39具有作用面39a与相对该作用面39a的非作用面39b。
于本实施例中，该电子元件39的作用面39a上具有电极垫390，且可选择性地于该电极垫390上形成焊锡材料，以藉由回焊制程，结合导电凸块37形成焊接凸块37’，令该电子元件39固设于该第二介电层35上。另外可选择性形成包覆该焊接凸块37’的底胶391于该电子元件39与该第二介电层35之间。该电子元件39可为例如半导体晶片的主动元件抑或其它被动元件。
如图3J所示，于该第二介电层35上形成一包覆该导电柱38及电子元件39的封装胶体41。
如图3K所示，利用研磨等方式薄化该封装胶体41，以外露出该导电柱38上表面，也可选择同时外露出该电子元件39的非作用面39b，令该封装胶体41的顶面与该电子元件39的非作用面39b及导电柱38上表面齐平。
如图3L所示，移除该承载板30，以使部分该线路层34上的第一金属层32外露出第一介电层31。
接着可在外露的第一金属层32上形成导电元件40，以形成一封装结构3。
于本实施例中，该导电元件40可为焊球、凸块或导针等,且可令该第一金属层32作为凸块底下金属(Under Bump Metallurgy,UBM)。
如图3M所示，后续即可将该封装结构3透过该导电元件40接置并电性连接至一例如电路板的电子元件43b，同时可供另一电子元件43a(例如半导体晶片或封装件)透过一导电材料430接置并电性连接至外露出该封装胶体41的导电柱38。
请参阅图4A至图4C，其为本发明的半导体封装结构的制法第二实施例的剖面示意图。本实施例的半导体封装结构的制法与前述第一实施例大致相同，以下仅说明差异处。
如图4A所示，其接续第一实施例的图3K，接着于该封装胶体41及导电柱38上形成一线路增层结构44。于本实施例中，该线路增层结构44具有至少一增层介电层440与形成于该增层介电层440上的增层线路层441，且该增层线路层441电性连接该导电柱38。另外该线路增层结构44也可省略该增层介电层440，也就是在该封装胶体41及导电柱38上仅形成增层线路层441。
之后于该线路增层结构44上形成一绝缘保护层42，并使该绝缘保护层42形成有多个外露出该增层线路层441的开孔。该绝缘保护层42例如为防焊层(solder mask)。
如图4B所示，移除该承载板30，以使部分该线路层34上的第一金属层32外露出第一介电层31。
接着可在外露的第一金属层32上形成导电元件40，以形成一封装结构3’。
如图4C所示，后续即可将该封装结构3’透过该导电元件40接置并电性连接至一例如电路板的电子元件43b，同时可供另一电子元件43a(例如半导体晶片或封装件)透过一导电材料430接置并电性连接至该线路增层结构44的增层线路层441。
透过前述制程，本发明还揭示一种封装结构，包括：由第一介电层31及第二介电层35构成的介电层31’，该介电层31’具有相对的第一表面31a’及第二表面31b’；形成于该介电层31’中的线路层34；一设于该介电层31’第一表面上31a’的电子元件39，且令该电子元件39电性连接至该线路层34；多个设于该介电层31’第一表面31a’上的导电柱38，且令该导电柱38电性连接至该线路层34；以及一形成于该介电层31’第一表面31a’上且包覆该电子元件39及导电柱38的封装胶体41，且令该导电柱38上表面外露出该封装胶体41。
该封装结构还包括一形成于该封装胶体41上的线路增层结构44，且令该线路增层结构44电性连接至该导电柱38。
该封装结构还包括多个形成于该介电层31’第二表面31b’的导电元件40，且令该导电元件40电性连接至该线路层34。
该封装结构另包括至少一接置于该线路增层结构44上的电子元件43a。
因此，本发明的封装结构及其制法主要藉由形成多个外露出封装胶体的导电柱，抑或进一步于该封装胶体上形成电性连接该导电柱的线路增层结构，以令该些导电柱向上电性连接线路增层结构，向下电性连接线路层，而可于该封装结构上方接置有其他电子元件，如晶片或其他封装结构，如此即可解决现有结构仅能朝下接置其他的电子元件(如电路板-封装机板或印刷电路板等)所导致封装结构功能受限问题，达到符合现今终端产品多功能需求目标。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (29)

1.一种封装结构的制法，其特征为，该制法包括：
提供一形成有线路层的介电层，且该介电层具有相对的第一表面及第二表面；
于该介电层的第一表面上接置一电子元件，并使该电子元件电性连接至该线路层；
于该介电层的第一表面上形成多个导电柱，并使该导电柱电性连接至线路层；以及
于该介电层的第一表面上形成包覆该电子元件及导电柱的封装胶体，并使该导电柱上表面外露出该封装胶体。
2.根据权利要求1所述的封装结构的制法，其特征为，该制法还包括于该封装胶体上形成一线路增层结构，并使该线路增层结构电性连接至该导电柱。
3.根据权利要求1或2所述的封装结构的制法，其特征为，该制法还包括：于该介电层第二表面形成多个电性连接该线路层的导电元件。
4.根据权利要求3所述的封装结构的制法，其特征为，该些导电元件用于供接置另一电子元件。
5.根据权利要求1所述的封装结构的制法，其特征为，该制法还包括：于外露出该封装胶体的该导电柱上接置另一电子元件。
6.根据权利要求2所述的封装结构的制法，其特征为，该制法还包括：于该线路增层结构上接置另一电子元件。
7.根据权利要求2所述的封装结构的制法，其特征为，该线路增层结构包含有增层线路层。
8.根据权利要求7所述的封装结构的制法，其特征为，该制法还包括：于该线路增层结构上形成一绝缘保护层，并使该绝缘保护层形成有多个外露出该增层线路层的开孔。
9.根据权利要求1所述的封装结构的制法，其特征为，该线路层在相对于该介电层的第一表面及第二表面上形成有第二金属层及第一金属层。
10.根据权利要求9所述的封装结构的制法，其特征为，该第一金属层及第二金属层为凸块底下金属(Under Bump Metallurgy,UBM)。
11.根据权利要求1所述的封装结构的制法，其特征为，于该介电层的第一表面上接置该电子元件后，还包括，于该介电层及该电子元件间形成底胶。
12.根据权利要求1所述的封装结构的制法，其特征为，该形成有线路层的介电层的制法包括：
形成一第一介电层于一承载板上，且于该第一介电层形成多个第一开孔，以外露该承载板的部分表面；
形成一第一金属层于该第一介电层的全部表面与该第一开孔中；
形成第一阻层于该第一金属层上，且于该第一阻层形成多个开口，以外露该第一金属层的部分表面与该些第一开孔中的第一金属层；
形成线路层于该些开口中的第一金属层上；以及
移除该第一阻层及其下方的第一金属层。
13.根据权利要求12所述的封装结构的制法，其特征为，该线路层上形成有多个导电凸块，该多个导电凸块的制法包括：
形成第二介电层于该第一介电层与该线路层上，且于该第二介电层形成多个第二开孔，以外露该线路层的部分表面；
形成第二金属层于该第二介电层的全部表面与该第二开孔中；
形成第二阻层于该第二金属层上，且于该第二阻层中形成多个开口，以外露该第二开孔及其周围的第二金属层的表面；
形成导电凸块于该些开口中的第二金属层上，令该导电凸块电性连接该线路层；以及
移除该第二阻层。
14.根据权利要求13所述的封装结构的制法，其特征为，该线路层上形成有多个导电柱，该多个导电柱的制法包括：
形成第三阻层于该第二金属层及该导电凸块上，且于该第三阻层中形成多个开口，以外露部分该第二金属层；以及
形成导电柱于该些开口中的第二金属层上，并令该导电柱电性连接该线路层。
15.根据权利要求14所述的封装结构的制法，其特征为，线路层上形成有多个导电元件，该多个导电元件的制法包括：
移除该承载板，以使部分该线路层上的第一金属层外露出第一介电层；以及
在外露的第一金属层上形成导电元件。
16.根据权利要求1所述的封装结构的制法，其特征为，该介电层的第一表面形成有多个电性连接该线路层的导电凸块，以供接置该电子元件。
17.根据权利要求1所述的封装结构的制法，其特征为，于形成该封装胶体后，还包括：薄化该封装胶体，以外露出该导电柱上表面或同时外露出该导电柱上表面与该电子元件的表面。
18.一种封装结构，其特征为，该封装结构包括：
一介电层，具有相对的第一表面及第二表面；
一线路层，其形成于该介电层中；
一电子元件，其设置于该介电层的第一表面上且电性连接至该线路层；
多个导电柱，其形成于该介电层第一表面上且电性连接至该线路层；以及
一封装胶体，其形成于该介电层的第一表面上且包覆该电子元件及导电柱，并使该导电柱上表面外露出该封装胶体。
19.根据权利要求18所述的封装结构，其特征为，该封装结构还包括有一线路增层结构，其形成于该封装胶体上且电性连接至该导电柱。
20.根据权利要求19所述的封装结构，其特征为，该封装结构还包括有一绝缘保护层，其形成于该线路增层结构上。
21.根据权利要求19所述的封装结构，其特征为，该封装结构还包括有另一电子元件，其接置于该线路增层结构上。
22.根据权利要求18所述的封装结构，其特征为，该介电层的第一表面形成有多个电性连接该线路层的导电凸块，以供接置该电子元件。
23.根据权利要求18所述的封装结构，其特征为，该封装结构还包括有多个导电元件，其形成于该介电层第二表面且电性连接至该线路层。
24.根据权利要求23所述的封装结构，其特征为，该封装结构还包括有另一电子元件，其接置于该些导电元件上。
25.根据权利要求18所述的封装结构，其特征为，该封装结构还包括有另一电子元件，其接置于外露出该封装胶体的该导电柱上。
26.根据权利要求18所述的封装结构，其特征为，该电子元件的上表面外露出该封装胶体。
27.根据权利要求18所述的封装结构，其特征为，该线路层在相对于该介电层的第一表面及第二表面上形成有第二金属层及第一金属层。
28.根据权利要求27所述的封装结构，其特征为，该第一金属层及第二金属层为凸块底下金属(Under Bump Metallurgy,UBM)。
29.根据权利要求18所述的封装结构，其特征为，该封装结构还包括有一底胶，其形成于该介电层及该电子元件间。
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