CN109841603A - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

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Publication number
CN109841603A
CN109841603A CN201811423713.3A CN201811423713A CN109841603A CN 109841603 A CN109841603 A CN 109841603A CN 201811423713 A CN201811423713 A CN 201811423713A CN 109841603 A CN109841603 A CN 109841603A
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China
Prior art keywords
crystal grain
insulating seal
layer
conductive
line structure
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CN201811423713.3A
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English (en)
Inventor
张简上煜
徐宏欣
林南君
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Powertech Technology Inc
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Powertech Technology Inc
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Publication of CN109841603A publication Critical patent/CN109841603A/zh
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

本发明提供一种封装结构及其制造方法，封装结构包括重布线路结构、晶粒、多个导电结构、第一绝缘密封体、芯片堆叠体以及第二绝缘密封体。晶粒配置在重布线路结构上且电性连接至重布线路结构。导电结构位于重布线路结构上且电性连接至重布线路结构。这些导电结构环绕晶粒。第一绝缘密封体包覆晶粒及导电结构。第一绝缘密封体包括暴露出多个导电结构的顶表面的多个开口。芯片堆叠体配置在第一绝缘密封体与晶粒上。芯片堆叠体电性连接至多个导电结构。第二绝缘密封体包覆芯片堆叠体。

Description

封装结构及其制造方法
技术领域
本发明提供一种封装结构及其制造方法，尤其涉及一种具有电性连接至芯片堆叠体的短导电结构的封装结构及其制造方法。
背景技术
近年来半导体封装技术的发展，着重在提供体积更小、重量更轻、整合度(integration level)更高与制造成本更低的产品。对于多功能的半导体封装，堆叠芯片的技术已被用于提供具有更大储存或处理数据的容量的封装。对于改善所需的多功能的电子元件的需求快速增加，为本领域研究人员的一大挑战。
发明内容
本发明提供一种封装结构及其制造方法，可有效降低封装结构的高度且具有较低的制造成本。
本发明的封装结构包括重布线路结构、晶粒、多个导电结构、第一绝缘密封体、芯片堆叠体以及第二绝缘密封体。晶粒配置在重布线路结构上且电性连接至重布线路结构。导电结构位于重布线路结构上且电性连接至重布线路结构。这些导电结构环绕晶粒。第一绝缘密封体包覆晶粒及导电结构。第一绝缘密封体包括暴露出多个导电结构的顶表面的多个开口。芯片堆叠体配置在第一绝缘密封体与晶粒上。芯片堆叠体电性连接至多个导电结构。第二绝缘密封体包覆芯片堆叠体。
在本发明的一实施例中，封装结构更包括多个导电端子。导电端子位于相对于晶粒及多个导电结构的重布线路结构上。
在本发明的一实施例中，封装结构更包括底胶。底胶位于重布线路结构与晶粒之间。
在本发明的封装结构的制造方法包括以下步骤。提供载板。形成重布线路结构在载板上。配置多个导电结构及多个晶粒在重布线路结构上。这些导电结构环绕这些晶粒。形成第一绝缘密封体以包覆多个晶粒及多个导电结构。形成多个开口在第一绝缘密封体中，以暴露出多个导电结构的顶表面。从重布线路结构移除载板。配置芯片堆叠体在相对于重布线路结构的多个晶粒及第一绝缘密封体上。芯片堆叠体电性连接至多个导电结构。通过第二绝缘密封体包覆芯片堆叠体。
在本发明的一实施例中，制造封装结构的方法更包括以下步骤。形成多个导电端子在相对于多个晶粒及多个导电结构的重布线路结构上。
在本发明的一实施例中，制造封装结构的方法更包括以下步骤。形成嵌入第二绝缘密封体中的多条导线，其中芯片堆叠体藉由多条导线电性连接至多个导电结构，且多条导线延伸至第一绝缘密封体的多个开口内。
在本发明的一实施例中，制造封装结构的方法更包括以下步骤。进行切单制造。
在本发明的一实施例中，制造封装结构的方法更包括以下步骤。形成底胶在重布线路结构及多个晶粒之间。
在本发明的一实施例中，其中多个晶粒藉由覆晶接合连接至重布线路结构。
在本发明的一实施例中，其中第一绝缘密封体的多个开口是藉由雷射钻孔制造形成。
本发明的一实施例中，其中藉由第二绝缘密封体包覆晶片堆叠的步骤包括：将第二绝缘密封体填入第一绝缘密封体的多个开口内。
基于上述，导电结构可作为封装结构内的垂直连接特征。由于导电结构的厚度小，可以有效地减少封装结构的尺寸。此外，通过短的导电结构的匹配，可以省略传统封装结构中的额外的载板或较厚铜柱，进而降低制造成本。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1A至图1L是依据本发明一些实施例的封装结构的制造方法的剖面示意图。
【符号说明】
10：封装结构
100：载板
102：离型层
200：重布线路结构
202：介电层
204：导电图案
206：导通孔
300：导电结构
300a、612a：顶表面
302：第一层
304：第二层
306：第三层
OP1、OP2：开口
400：晶粒
400a：主动面
400b：背面
402：半导体基板
404：导电接垫
406：保护层
408：导电连接件
408a：导电柱体
408b：导电凸块
500：底胶
610：第一绝缘密封体
612：绝缘材料
620：第二绝缘密封体
t300、t400、t610：厚度
710：芯片堆叠体
720：导线
800：导电端子
具体实施方式
图1A至图1L是依据本发明一些实施例的封装结构10的制造方法的剖面示意图。请参照图1A，提供载板100，载板100具有离型层102。载板100可以是玻璃基板或玻璃支撑板。然而，本发明不限于此。可以采用其他适宜的基板材料，只要所述材料能够承载在其之上所形成的封装结构且能够承受后续的制造即可。离型层102可以包括光热转换(light toheat conversion，LTHC)材料、环氧树脂(epoxy resin)、无机材料、有机聚合物材料或其他适宜的粘着材料。然而，本发明不以此为限，在一些替代实施例中可使用其他适宜的离型层。
请参照图1B，形成重布线路结构200在载板100上。重布线路结构200可包括至少一层介电层202、多个导电图案204与多个导通孔206。可以通过适宜的制造技术，如：旋转涂布(spin-on coating)、化学气相沉积(chemical vapor deposition；CVD)、等离子体辅助化学气相沉积(plasma-enhanced chemical vapor deposition；PECVD)或其他类似者，以形成介电层202。介电层202可以由氧化硅、氮化硅、碳化硅、氮氧化硅、聚酰亚胺、苯并环丁烯等的非有机或有机介电材料所制成。另一方面，可以通过溅镀、蒸镀、化学镀(electro-lessplating)或电镀(electroplating)来形成导电图案204以及导通孔206。导电图案204与导通孔206嵌入于介电层202中。介电层202与导电图案204可以交替地堆叠。导通孔206可以穿过介电层202，以使导电图案204彼此电性连接。导电图案204与导通孔206可以由铜、铝、镍、金、银、锡、上述的组合、铜/镍/金的复合结构或是其他适宜的导电材料所组成。
请参照图1B，重布线路结构200包括四层的介电层202。然而，本发明对于介电层202的数量并不加以限制，并且可以基于电路的设计而进行调整。顶部的介电层202具有多个开口OP1，开口OP1暴露出部分顶部的导电图案204，以用于后续制造的电性连接。为了进一步电性连接至其他电路元件，底部的介电层202暴露出部分的底部的导电图案204。
请参照图1C，导电结构300设置在相对于载板100的重布线路结构200上。在一些实施例中，导电结构300可镀析于重布线路结构200的顶部的导电图案204上。镀析制造可以为电镀、化学镀、浸镀(immersion plating)或类似的方法。在一些实施例中，导电结构300可以形成圆柱状。也就是说，导电结构300可以包括导电栓塞(conductive post)、导电柱(conductive pillar)或其他相似物。然而，本发明不限于此。在一些替代实施例中，导电结构300可以采用多边形柱或其他适宜形状。在一些实施例中，每个导电结构300是多层复合结构。每一个导电结构300包括第一层302、堆叠于第一层302上的第二层304以及堆叠于第二层304上的第三层306。第一层302的材料、第二层304的材料与第三层306的材料可以彼此不相同。举例来说，第一层302的材料包括铜、铝、锡、银、上述的合金或其他相似材料。第二层304的材料包括镍、焊料或其他相似材料。第三层的材料包括铜、金或其他具有优异的导电性和良好的打线接合性的金属材料。在一些实施例中，第一层302、第二层304和第三层306可以形成铜/镍/金复合结构。第三层306能增强导电结构300与其他后续形成的元件之间的电性连接。另一方面，第二层304夹在第一层302和第三层306之间，用以作为第一层302和第三层306之间的阻挡层。举例来说，当第一层302、第二层304和第三层306是铜/镍/金复合结构时，由镍形成的第二层304可以防止第一层302的铜原子扩散到第三层306中。若第三层306受到铜污染会使第三层306容易氧化，进而导致不良的打线接合性。然而，通过第二层304作为阻挡层，可以充分防止上述的不利影响。虽然图1C中的导电结构300由三层所构成，但本发明不以此为限。在一些替代实施例中，每个导电结构300可以是单层结构，或由两层、四层或更多层所构成的多层结构。
如图1C所示，导电结构300填入部分的重布线路结构200的顶介电层202的开口OP1。举例而言，导电结构300的第一层302可以部分地位于顶部的介电层202的开口OP1内，以在重布线路结构200和导电结构300之间形成电性连接。第一层302可以与重布线路结构200的顶导电图案204具有物理接触。
请参照图1D，配置多个晶粒400在相对于载板100的重布线路结构200上。晶粒可以通过取放制造(pick and place process)以配置在重布线路结构200上。在一些实施例中，放置晶粒400以使导电结构300环绕晶粒400。导电结构300沿着至少一个晶粒400的周围设置。晶粒400可包括数字晶粒、模拟晶粒或混合信号(mixed signal)晶粒。举例来说，晶粒400可以是特殊应用集成电路(Application-Specific Integrated Circuit；ASIC)晶粒、逻辑晶粒、或其他适宜的晶粒。每一个晶粒400包括半导体基板402、多个导电接垫404、保护层(passivation layer)406与多个导电连接件408。在一些实施例中，半导体基板402可以是具有主动元件(如：晶体管或其他类似者)及选择性地具有被动元件(如：电阻、电容、电感或其他类似者)形成于其上的硅基板。导电接垫404分布在半导体基板402上。导电接垫404可以包括铝接垫、铜接垫或其他适宜的金属接垫。保护层406形成在半导体基板402上，并部分地覆盖每个导电接垫404。换言之，保护层406具有多个接触开口，其露出每个导电接垫404的至少一部分。保护层406可以是氧化硅层、氮化硅层、氮氧化硅层、或由聚合材料或其他适宜的介电材料所形成的介电层。导电连接件408设置在导电接垫404上。举例而言，导电连接件408可以延伸到保护层406的接触开口中，以提供与导电接垫404的电性连接。在一些实施例中，每个导电连接件408可以包括导电柱体408a和设置在导电柱体408a上的导电凸块408b。导电柱体408a可以镀析于导电接垫404上。镀析制造可以为电镀、化学镀、浸镀或类似的方法。导电柱体408a可包括铜、铜合金或其他相似材料等。另一方面，导电凸块408b可以由铜、镍、锡、银或上述的组合所构成。在一些实施例中，可以省略导电柱体408a。导电连接件408可以包括芯片连接(Chip Connection；C2)凸块或控制塌陷高度芯片连接(Controlled Collapse Chip Connection；C4)凸块。
每一个晶粒具有主动面400a及相对于主动面400a的一个背面400b。如图1D所示，晶粒400以面朝下的方式设置，使得晶粒400的主动面400a面向重布线路结构200。晶粒400可以通过覆晶接合以连接重布线路结构200。晶粒400的导电连接件408可以设置在顶介电层202的开口OP1的另一部分中，并可以与重布线路结构200的顶部的导电图案204物理性接触。如此一来，可实现晶粒400与重布线路结构200之间的电性连接。在一些实施例中，重布线路结构200可用于传递电信号到/从晶粒400，且可在较晶粒400更宽的区域中扩展。因此，在一些实施例中，重布线路结构200可以被称为“扇出重布线路结构(fan-outredistribution structure)”。
如图1D所示，导电结构300的厚度t300小于晶粒400的厚度t400。举例而言，晶粒400的背面400b至重布线路结构200的高度高于导电结构300的顶表面300a至重布线路结构200的高度。
在一些实施例中，形成底胶500在重布线路结构200和晶粒400之间，以保护和隔离导电连接件408和顶导电图案204之间的耦合。在一些实施例中，底胶500填充到顶部的介电层202的开口OP1中。底胶500可以由包括聚合物材料、树脂或二氧化硅添加剂的毛细填充胶(capillary underfill filling；CUF)制成，。
尽管图1C及图1D示出了于放置晶粒400之前形成导电结构300，但本发明不以此为限。在一些替代实施例中，可以于形成导电结构300之前，将晶粒400放置在重布线路结构200上。也就是说，图1C及图1D所示的制造步骤是可互换的。
请参照图1E，在重布线路结构200上形成绝缘材料612，以包覆导电结构300、晶粒400和底胶500。绝缘材料612可以包括由模塑制造所形成的模塑化合物或绝缘材料(如：环氧树脂、硅基树脂(silicone)或其他适宜的树脂)。在一些实施例中，可以通过模塑制造形成绝缘材料612，以使导电结构300和晶粒400不会被露出。如图1E所示，绝缘材料612的顶表面612a的水平高度高于导电结构300的顶表面300a和晶粒400的背面400b的水平高度。
请参照图1F，减少绝缘材料612的厚度，以形成第一绝缘密封体610。可以将绝缘材料612的一部分移除，以暴露出晶粒400的背面400b，同时导电结构300仍完全被第一绝缘密封体610完全密封。在一些实施例中，移除绝缘材料612可通过平坦化制造。平坦化制造可以是化学机械研磨(CMP)、机械研磨、蚀刻制造或其他适宜的制造。平坦化制造可以进一步研磨绝缘材料612和晶粒400，以减少随后形成的封装结构10的总厚度。在平坦化制造之后，将第一绝缘密封体610设置在重布线路结构200上，以横向包覆晶粒400。第一绝缘密封体610也包覆导电结构300的侧壁与顶表面300a。第一绝缘密封体610的顶表面610a和晶粒400的背面400b基本上可以彼此共面。另一方面，第一绝缘密封体610的顶表面610a具有高于导电结构300的顶表面300a的水平高度。第一绝缘密封体610的厚度t610可以大于每一个导电结构300的厚度t300。
请参照图1G，在第一密封绝缘体610中形成多个开口OP2。在一些实施例中，开口OP2是通过激光钻孔制造形成。位于导电结构300上方的第一绝缘密封体610可以被部分地去除以形成开口OP2。如图1G所示，开口OP2的位置对应于导电结构300的位置。每个开口OP2可以暴露出每个导电结构300的一部分。开口OP2可以暴露出导电结构300的顶表面300a。在一些实施例中，开口OP2可以部分地暴露出导电结构300的第三层306。
请参照图1H，离型层102及载板100从重布线路结构200移除。当离型层102是光热转换层(Light-To-Heat-Conversion Release Coating；LTHC)时，离型层102及载体100在暴露于激光时可以从重布线路结构200的底部的介电层202及底部的导电图案204剥离并分离。如图1H所示的结构可以切割成条状(Strip Form)，以用于传统的打线接合封装。
请参照图1I，芯片堆叠体710配置在相对于重布线路结构200的第一绝缘密封体610与晶粒400上。芯片堆叠体710可位于晶粒400的背面400b和第一绝缘密封体610的顶表面610a上。芯片堆叠体710可以通过多个芯片彼此顶部堆叠形成。芯片可以是具有非易失性存储器的存储器芯片，例如NAND快取(NAND flash)存储器。然而，本发明不限于此。在一些替代性实施例中，芯片堆叠体710的芯片可以是执行其他功能的芯片，例如逻辑功能、计算功能或其他相似功能。芯片粘着层(未示出)可以设置在芯片堆叠体710中的两个相邻芯片之间，以提升两个芯片之间的粘着。
芯片堆叠体710可以通过多个导线720电性连接至导电结构300。当芯片堆叠体710配置在晶粒400和第一绝缘密封体610上时，多条导线720可通过打线接合制造所形成。导线720的一端耦合到芯片堆叠体710的至少一个芯片，导线720延伸到第一绝缘密封体610的开口OP2中，导线720的另一端耦合到导电结构300的第三层306。导线720的材料可包括金、铝或其他适宜的导电材料。在一些实施例中，导线720的材料与导电结构300的第三层306的材料相同。
请参照图1J，第二绝缘密封体620形成在第一绝缘密封体610和晶粒400上，以包覆芯片堆叠体710和导线720，以使芯片堆叠体710和导线720嵌入于第二绝缘密封体620中。第二绝缘密封体620的材料可以与第一绝缘密封体610的材料相同或不同。第二绝缘密封体620的材料可以是环氧树脂、模塑化合物或其他适宜的绝缘材料。在一些实施例中，第二绝缘密封体620的材料可具有低湿气吸收率。第二绝缘密封体620可以通过压缩模塑(compression molding)、转移模塑(transfer molding)或密封制造的制造所形成。如图1J所示，第二绝缘密封体620可以填充第一绝缘密封体610的开口OP2，以保护位于开口OP2中的导线720的区段。第二绝缘密封体620可以与导电结构300的一部分物理性地接触。第二绝缘密封体620为芯片堆叠体710和导线720提供物理支撑、机械保护以及电与环境隔离。
请参照图1K，多个导电端子800形成在相对于晶粒400及导电结构300的重布线路结构200上。在一些实施例中，导电端子800位于重布线路结构200的底导电图案204上。换言之，重布线路结构200的底部的导电图案204可以作为凸块底金属(under-ballmetallurgy；UBM)图案。导电端子800可以通过植球制造(ball placement process)和/或回焊制造(reflow process)来形成。导电端子800可以是焊球等的导电凸块。然而，本发明不限于此。在一些替代性的实施例中，导电端子800可以依据设计上的需求采用其他可能的形式和形状。举例来说，导电端子800可以是导电柱或导电栓塞(conductive post)。
请参照图1L，在形成导电端子800后，进行切单制造(singulation process)以形成多个封装结构10。切单制造包括例如用旋转刀片或激光光束进行切割。
综上所述，导电结构可作为封装结构内的垂直连接特征。由于导电结构的厚度小，可以有效地减少封装结构的尺寸。此外，通过短的导电结构的匹配，可以省略传统封装结构中的额外的载板或较厚铜柱，进而降低制造成本。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中的技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求所界定的为准。

Claims (10)

1.一种封装结构，包括：
重布线路结构；
晶粒，配置在所述重布线路结构上且电性连接至所述重布线路结构；
多个导电结构，位于所述重布线路结构上且电性连接至所述重布线路结构，其中所述多个导电结构环绕所述晶粒；
第一绝缘密封体，包覆所述晶粒及所述多个导电结构，其中所述第一绝缘密封体包括暴露出所述多个导电结构的顶表面的多个开口；
芯片堆叠体，配置在所述第一绝缘密封体与所述晶粒上，其中所述芯片堆叠体电性连接至所述多个导电结构；以及
第二绝缘密封体，包覆所述芯片堆叠体。
2.根据权利要求1所述的封装结构，还包括：
多条导线，嵌于所述第二绝缘密封体中，其中所述芯片堆叠体通过所述多条导线电性连接至所述多个导电结构，且所述多条导线延伸至所述第一绝缘密封体的所述多个开口内。
3.根据权利要求1所述的封装结构，其中所述第二绝缘密封体填入所述第一绝缘密封体的所述多个开口内。
4.根据权利要求1所述的封装结构，其中每一所述多个导电结构包括第一层、堆叠于所述第一层上的第二层以及堆叠于所述第二层上的第三层，且所述第一绝缘密封体的所述多个开口暴露出所述第三层。
5.根据权利要求4所述的封装结构，其中所述第三层的材料包括金。
6.根据权利要求1所述的封装结构，其中所述第一绝缘密封体的厚度大于每一所述多个导电结构的厚度。
7.根据权利要求1所述的封装结构，其中所述第一绝缘密封体的顶表面高于所述多个导电结构的顶表面。
8.根据权利要求1所述的封装结构，其中所述晶粒具有主动面及相对于所述主动面的背面，所述晶粒包括位于所述主动面上的多个导电连接件，且所述多个导电连接件直接接触所述重布线路结构。
9.一种封装结构的制造方法，包括：
提供载板；
形成重布线路结构在所述载板上；
配置多个导电结构及多个晶粒在所述重布线路结构上，其中所述多个导电结构环绕所述多个晶粒；
形成第一绝缘密封体，以包覆所述多个晶粒及所述多个导电结构；
形成多个开口在所述第一绝缘密封体中，以暴露出所述多个导电结构的顶表面；
从所述重布线路结构移除所述载板；
配置芯片堆叠体在相对于所述重布线路结构的所述多个晶粒及所述第一绝缘密封体上，其中所述芯片堆叠体电性连接至所述多个导电结构；以及
通过第二绝缘密封体包覆所述芯片堆叠体。
10.根据权利要求9所述的封装结构的制造方法，其中每一所述多个晶粒具有主动面及相对于所述主动面的背面，且形成所述第一绝缘密封体的步骤包括：
形成绝缘材料在所述重布线路结构上，以覆盖所述多个晶粒及所述多个导电结构；以及
移除部分的所述绝缘材料，以暴露出所述多个晶粒的所述多个背面，其中所述多个导电结构不被露出。
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