CN103915413A - 层叠封装接合结构 - Google Patents

层叠封装接合结构 Download PDF

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Publication number
CN103915413A
CN103915413A CN201310385077.0A CN201310385077A CN103915413A CN 103915413 A CN103915413 A CN 103915413A CN 201310385077 A CN201310385077 A CN 201310385077A CN 103915413 A CN103915413 A CN 103915413A
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China
Prior art keywords
conductive layer
tpv
layer
semiconductor element
package
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CN201310385077.0A
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CN103915413B (zh
Inventor
林俊成
洪瑞斌
蔡柏豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了用于在管芯封装件中形成具有多个导电层和/或凹槽的封装通孔（TPV）和利用TPV形成具有接合结构的层叠封装（PoP）器件的机制的不同实施例。将多个导电层中的一层用作TPV的主导电层的保护层。当暴露于焊料时，保护层不容易氧化并具有金属间化合物（IMC）的较低的形成速率。用其他管芯封装件的焊料填充管芯封装件的TPV中的凹槽并且形成的IMC层在TPV的表面下方以加强接合结构。本发明提供了叠层封装接合结构。

Description

层叠封装接合结构
相关申请的交叉引用
本申请要求于2012年12月28日提交的标题为“Package on Package（PoP）Bonding Structures″的美国临时专利申请61/746,967号的优先权，其全部内容结合于此作为参考。
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及叠层封装接合结构。
背景技术
半导体器件用于诸如个人电脑、手机、数码相机和其他电子设备的各种电子应用中。通常通过在半导体衬底上方依次沉积绝缘层或介电层、导电层和半导电层的材料并且使用光刻工艺来图案化各种材料层以在其上形成电路部件和元件从而制得半导体器件。
半导体产业通过不断减小最小部件尺寸来不断提高各种电子元件（例如，晶体管、二极管、电阻器、电容器等）的集成度，这使得更多的部件集成在特定的区域上。在一些应用中，这些更小的电子部件也要求与先前的封装相比占用更小面积和/或更低高度的较小封装。
从而，已经开发出诸如层叠封装（PoP）的新的封装技术，其中具有器件管芯的顶部封装件接合至具有另一个器件管芯的底部封装件。通过采用这种新的封装技术，可以提高封装件的集成水平。这些用于半导体的相对新型的封装技术面临着制造挑战。
发明内容
根据本发明的一个方面，提供了一种半导体管芯封装件，包括：半导体管芯；模塑料，至少部分地封装半导体管芯；封装通孔（TPV），形成在模塑料中，TPV设置为邻近半导体管芯，TPV包括第一导电层和第二导电层，并且第一导电层填充TPV的第一部分而第二导电层填充TPV的第二部分；以及重分布结构，重分布结构包括重分布层（RDL），TPV和半导体管芯电连接至RDL，并且RDL能够实现半导体管芯的扇出。
优选地，第一部分的高度介于约0.1μm至约30μm之间。
优选地，第二部分的高度介于约50μm至约300μm之间。
优选地，通过模塑料中的开口来暴露第一导电层的第一表面，并且第一表面基本上与模塑料的表面平齐。
优选地，TPV的与RDL相对的端部相对于模塑料的顶面形成凹槽，凹槽的高度介于约0.1μm至约30μm之间。
优选地，形成与第一导电层邻近并且与第二导电层相对的第三导电层。
优选地，第三导电层由焊料形成。
优选地，第一导电层由与铜相比不太可能氧化并且当结合至焊料时不太可能形成金属间化合物（IMC）的导电金属制成。
优选地，第一导电层由选自由Ni、Pt、Sn和Sn合金组成的组中的金属制成，Sn合金包含Ag、Cu、Bi和它们的组合。
优选地，第二导电层由铜制成。
根据本发明的另一方面，提供了一种半导体管芯封装件，包括：半导体管芯；封装通孔（TPV），形成在半导体管芯封装件中，TPV设置为邻近半导体管芯，TPV包括导电层和凹槽；以及重分布结构，重分布结构包括重分布层（RDL），TPV和半导体管芯电连接至RDL，并且RDL能够实现半导体管芯的扇出，凹槽位于导电层的与RDL相对的一侧。
根据本发明的又一方面，提供了一种层叠封装器件（PoP），包括第一管芯封装件和第二管芯封装件。第一管芯封装件包括：第一半导体管芯；和封装通孔（TPV），TPV设置为邻近半导体管芯，TPV包括第一导电层和第二导电层。第二管芯封装件包括：第二半导体管芯；和包含焊料的外部连接件，其中，第二管芯封装件的外部连接件接合至第一管芯封装件的TPV。
优选地，第二管芯封装件的外部连接件接合至TPV的第一导电层。
优选地，金属间化合物（IMC）形成在外部连接件和第一导电层之间，IMC的厚度介于约0.5μm至约10μm之间。
优选地，焊料填充TPV的一部分并且在模塑料的表面下方形成IMC，模塑料包围TPV和半导体管芯。
优选地，第一管芯封装件还包括：重分布结构，重分布结构包括重分布层（RDL），TPV和半导体管芯电连接至RDL，并且RDL能够实现半导体管芯的扇出。
优选地，在与外部连接件接合之前，将TPV的第一导电层从TPV中去除，第二导电层由铜形成。
优选地，第一导电层由与铜相比不太可能氧化并且当结合至焊料时不太可能形成金属间化合物（IMC）的导电金属制成。
优选地，第一导电层由选自由Ni、Pt、Sn和Sn合金组成的组中的金属制成，Sn合金包含Ag、Cu、Bi和它们的组合。
优选地，第二导电层由铜制成。
附图说明
为了更充分的理解实施例及其优势，现结合附图参考以下描述，其中：
图1A是根据一些实施例的封装结构的立体图；
图1B示出了根据一些实施例的接合至另一个管芯封装件的管芯封装件的截面图；
图2A至图2P示出了根据一些实施例的制备层叠封装（PoP）器件的连续工艺流程的截面图；以及
图3A至图8C是根据一些实施例的管芯封装件和层叠封装（PoP）器件的截面图。
具体实施方式
以下详细论述了本发明实施例的制造和使用。然而，应该理解，本发明的实施例提供了许多可以在各种具体环境中可具体化的发明概念。所论述的具体实施例是说明性的，而不用于限制实施例的范围。
自从发明集成电路以来，由于各种电子元件（例如，晶体管、二极管、电阻器、电容器等）的集成度的不断提高，半导体产业经历了持续快速的发展。多数情况下，这种集成度的提高源于最小部件尺寸的不断减小从而使得更多的元件集成到特定区域中。
由于集成部件占据的体积基本上位于半导体晶圆的表面上，因此这些集成的改进在本质上基本是二维（2D）的。虽然光刻工艺的急剧改进在2D集成电路形成方面产生了相当大的改进，但是可在二维上实现的密度存在着物理限制。这些限制之一是制造这些部件需要的最小尺寸。同样，当将更多的器件放置在一个芯片上时，需要更复杂的设计。
因此，创造三维集成电路（3D IC）来解决上述限制。在一些3D IC的形成工艺中，形成两个或两个以上的晶圆，每一个晶圆都包括集成电路。切割晶圆以形成管芯。封装具有不同器件的管芯，然后将其与对准的器件接合。封装通孔（TPV），也被称为模制通孔（TMV），被越来越多地用作实现3D IC的方式。TPV经常用在3D IC和堆叠的管芯中以提供电连接和/或协助散热。
图1A是根据一些实施例的封装结构100的立体图，其包括接合至另一个封装件120的封装件110，封装件120又接合至另一个衬底130。每一个管芯封装件110和120都包括至少一个半导体管芯（未示出）。半导体管芯包括在半导体集成电路制造中应用的半导体衬底，并且可以在其中和/或其上形成集成电路。半导体衬底是指包括半导体材料的任何构造，半导体材料包括但不限于块状硅、半导体晶圆、绝缘体上硅（SOI）衬底或硅锗衬底。也可以使用包括III、IV和V族元素的其他半导体材料。半导体衬底还可以包括多个隔离部件（未示出），诸如浅沟槽隔离（STI）部件或硅的局部氧化（LOCOS）部件。隔离部件可以限定并且隔离各种微电子元件。可在半导体衬底中形成的各种微电子元件的实例包括晶体管（例如，金属氧化物半导体场效应晶体管（MOSFET）、互补金属氧化物半导体（CMOS）晶体管、双极结型晶体管（BJT）、高压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管（PFET/NFET）等）、电阻器、二极管、电容器、电感器、熔丝和其他合适的元件。实施包括沉积、蚀刻、注入、光刻、退火和/或其它合适的工艺的各种工艺以形成各种微电子元件。互连微电子元件以形成集成电路器件，诸如逻辑器件、存储器件（例如，SRAM）、RF器件、输入/输出（I/O）器件、系统级芯片（SoC）器件、它们的组合和其他适合的器件类型。根据一些实施例，封装件120包括封装通孔（TPV）并用作中介片。
衬底130可由双马来酰亚胺三嗪（BT）树脂、FR-4（由编织玻璃纤维布与环氧树脂粘合剂组成的耐燃复合材料）、陶瓷、玻璃、塑料、胶带、薄膜或可承载用于接纳导电端子的导电焊盘或导电台的其他支撑材料制成。在一些实施例中，衬底130是多层电路板。封装件110通过连接件115接合至封装件120，并且封装件120通过外部连接件145接合至衬底130。在一些实施例中，外部连接件145是接合的凸块结构，诸如接合焊料凸块或具有连接焊料层的接合铜柱。本发明所述的焊料可包括铅或不包括铅。
图1B示出了根据一些实施例的位于管芯封装件120上方的管芯封装件110的截面图。如图1B所述，封装件110包括两个半导体管芯112和113，其中管芯113设置在管芯112上方。然而，封装件110可包括一个半导体管芯或多于两个的半导体管芯。在一些实施例中，在管芯112和113之间存在胶水层（未示出）。半导体管芯112和113可包括如以上所述的用于半导体管芯的各种微电子元件。半导体管芯112接合至衬底115。衬底115可包括上述用于衬底130的各种材料和/或部件。根据一些实施例，半导体管芯112通过接合引线114电连接至衬底115中的导电元件（未示出）。类似地，半导体管芯113通过接合引线116电连接至衬底115中的导电元件。封装件110还包括模塑料111，其覆盖半导体管芯112和113，以及接合引线114和116。封装件110还包括用于外部连接的多个连接件117。连接件117形成在金属焊盘118上，其通过可包括通孔和金属线的互连结构119而电连接至接合引线114和116。
根据一些实施例，如图1B所示，管芯封装件120包括半导体管芯121和围绕管芯121的TPV122。封装件120还包括包含一个或多个重分布层（RDL）123的重分布结构125。重分布层（RDL）123是可包括金属线和通孔的金属互连层，并且被介电材料包围。RDL123能够实现管芯121的扇出。如图1B所示，诸如球栅阵列（BGA）的外部连接件126附接至重分布结构125上的金属焊盘（未示出）。如图1B所示，TPV122连接至封装件110的连接件117。管芯121和外部连接件126位于重分布结构125的相对两侧。管芯121通过连接件127连接至重分布结构125。
在一些实施例中，管芯封装件110的连接件117由焊料制成。在一些实施例中，连接件117包括在焊料柱端部具有焊料的铜柱。连接件117的焊料接合至填充有铜的TPV122的暴露的铜表面。然而，当暴露的铜表面暴露于大气中时，其可以形成氧化铜。从而，如图1B的TPV122D所示，可以在TPV122的表面上形成氧化铜层141。虽然可将助焊剂施加在TPV122的表面以去除形成在TPV122表面上的氧化铜层，但是，在一些实施例中去除工艺是不稳定的。结果，氧化铜层141或至少部分的氧化铜层141仍保留在TPV122（诸如TPV122D）上。连接件117的焊料没有良好接合至氧化铜层141，从而，结合可能被弱化，这将会影响成品率和可靠性。
即使助焊剂确实从TPV（诸如TPV122A、TPV122B和TPV122C）中去除氧化铜层，但是连接件117的焊料和TPV的铜之间的直接接触将导致诸如Cu:Sn的金属间化合物（IMC）的形成。根据一些实施例，图1B示出了在连接件117的焊料和TPV122A、TPV122B以及TPV122C的铜之间形成的IMC层142。由于封装件120上的不同元件的热膨胀系数不同，所以在封装工艺期间和/或之后，封装件120可能会弯曲。这种弯曲（或翘曲）产生了封装件120和封装件110之间的由接合的连接件117和TPV122形成的接合结构的应力。这种应力会造成由连接件117和TPV122形成的接合结构260的破裂从而影响层叠封装（PoP）结构的成品率和可靠性。
在将TPV暴露之后并且结合至连接件之前，保护层（未示出）（诸如焊膏层、有机可焊性膏层（OSP）或其他适用的保护层）可在TPV122上方形成。然而，在形成TPV122之后形成这样的保护层可涉及到将具有封装的管芯（或衬底）的载体转移到加工系统或腔室和/或加工衬底以形成保护层。在形成保护层之前，需要通过诸如助焊剂来处理TPV122的表面以去除形成的氧化物层141。这种附加的加工操作是成本所不允许的。因此，需要一种在管芯封装件之间形成接合结构而不会出现上述问题的机制。
图2A至2P示出了根据一些实施例的制备层叠封装（PoP）器件的连续工艺流程的截面图。图2A示出了位于载体201上方的粘合层（或胶水层）202。根据一些实施例，载体201由玻璃制成。然而，也可将其他材料用于载体201。在一些实施例中，在载体201上方沉积或层压粘合层202。粘合层202可由胶水形成或可为诸如箔的层压材料。在一些实施例中，粘合层202是感光的并且在完成有关的封装工艺之后，通过向载体201照射紫外（UV）光或激光而容易将其从载体201上剥离。例如，粘合层202可以是由美国明尼苏达州圣保罗市的3M公司生产的光热转换（LTHC）涂层。在其他的一些实施例中，粘合层202是热敏感的。在一些实施例中，粘合层202为胶水层（未示出）。例如，胶水层可以是管芯附着膜（DAF）、聚合物（诸如聚酰亚胺、聚苯并恶唑（PBO））或阻焊剂以提高附着力。
根据一些实施例，如图2B所示，然后在粘合层202上形成镀晶种层204。在一些实施例中，镀晶种层204由铜制成并且通过物理汽相沉积（PVD）来形成。然而，也可以使用其他的导电薄膜，例如，镀晶种层204可由Ti、Ti合金、Cu和/或Cu合金制成。Ti合金与Cu合金可包括银、铬、镍、锡、金、钨和它们的组合。在一些实施例中，镀晶种层204的厚度范围在约0.1μm至约1.0μm之间。在一些实施例中，镀晶种层204包括在沉积镀晶种层之前形成的扩散阻挡层。镀晶种层204还可以用作下层的粘附层。在一些实施例中，扩散阻挡层由Ti形成，且厚度范围介于约0.01μm至约0.1μm之间。然而，扩散阻挡层也可由其他材料（诸如TaN或其他的可应用的材料）制成，并且其厚度范围不限制在上述的范围内。在一些实施例中，通过PVD来形成扩散阻挡层。
根据一些实施例，如图2C所示，在沉积镀晶种层204之后，在其上方形成光刻胶层205。可以由诸如旋涂工艺的湿法工艺或诸如干膜的干法工艺来形成光刻胶层205。在形成光刻胶层205之后，图案化光刻胶层205以形成开口206，填充该开口以形成以上所述的图1B中的TPV。涉及的工艺包括光刻和光刻胶显影。在一些实施例中，开口206的宽度W范围介于约40μm至约260μm之间。在一些实施例中，开口206的深度D范围介于约6μm至约300μm之间。
之后，根据一些实施例，在镀晶种层204的表面上镀第一导电层203。第一导电层203不形成含有焊料的IMC或者以远慢于铜的速率形成含有焊料的IMC。此外，当第一导电层203暴露于环境（例如，空气）中，相比于铜，其氧化的可能性很小或不太可能。在一些实施例中，第一导电层203由镍（Ni）形成。然而，也可使用具有上述适于层203的性质的其他导电材料，诸如铂（Pt）、金（Au）、银（Ag）、锡（Sn）、锡合金（包括但不限于SnAg、SnAgCu、SnCu、SnAgCu-Bi）等以及它们的组合。在一些实施例中，层203的厚度D1的范围介于约0.1μm至约30μm之间。
根据一些实施例，如图2D所示，在形成第一导电层203之后，在第一导电层203上方镀第二导电层207以填充开口206。在一些实施例中，层207的厚度D2的范围介于约50μm至约300μm之间。
在通过镀法填充缺口的工艺之后，通过可以为干法工艺或湿法工艺的蚀刻工艺来去除光刻胶层205。图2E示出了根据一些实施例的在去除光刻胶层205并且使开口206中的导电材料暴露以作为（导电）柱122′之后的载体201上的结构的截面图。
之后，根据一些实施例，如图2F所示，半导体管芯121通过胶水层210附接至载体201上方的表面209。根据一些实施例，胶水层210由管芯附着膜（DAF）形成。DAF可由环氧树脂、酚醛树脂、丙烯酸酯橡胶、硅胶填充物或它们的组合形成。图2F示出了管芯121的连接件127远离表面209。然后向位于载体201上方的镀晶种层204的表面应用液体模塑料材料以填充导电柱122′和管芯121之间的空间并且覆盖管芯121和导电柱122′。在一些实施例中，半导体管芯121直接附着于层202的表面。首先去除位于管芯121下方的层204。在这种情况下，将模塑料应用于层202的表面。然后，应用热处理以硬化模塑料材料并且将其转变成模塑料123。在包围导电柱122′的模塑料123形成之后，导电柱122′成为TPV122″。
随后，根据一些实施例，如图2G所示，应用平坦化工艺以去除过量的模塑料123以暴露TPV122″和管芯121的连接件127。在一些实施例中，平坦化工艺是研磨工艺。在其他实施例中，平坦化工艺式是化学机械抛光（CMP）工艺。根据一些实施例，图2H中示出了平坦化后的结构。
根据一些实施例，如图2I所示，在平坦化工艺之后，在图2H中的结构上方的表面211上方形成重分布结构125。图2I示出了第二重分布结构125包括通过一个或多个诸如层212和214的钝化层来隔离的RDL213。RDL213可包括金属线和导电通孔。RDL213由导电材料制成并且直接接触TPV122″和管芯121的连接件127。在一些实施例中，RDL213由铝、铝合金、铜或铜合金制成。然而，RDL213可由其他类型的导电材料制成。钝化层212和214由介电材料制成并且为在外部连接件126与衬底130接合过程中产生的接合应力提供应力消除。在一些实施例中，钝化层212和214由诸如聚酰亚胺、聚苯并恶唑（PBO）或苯并环丁烯（BCB）的聚合物制成。图案化钝化层214以形成用于暴露部分RDL213的开口（未示出）从而形成接合焊盘（未示出）。在一些实施例中，在接合焊盘上方形成凸块下金属化层（UBM）（未示出）。UBM层也可对钝化层214的开口的侧壁加衬。在一些实施例中，RDL213可以是单层。
在2012年3月22日提交的标题为“Bump Structures for Multi-ChipPackaging”的美国专利申请13/427,753号（代理卷号：TSMC2011-1339）以及在2011年12月28日提交的标题为“Packaged Semiconductor Device andMethod of Packaging the Semiconductor Device”的美国专利申请13/338,820号（代理卷号：TSMC2011-1368）中，描述了重分布结构和接合结构的实例和形成它们的方法。上述两申请的全部内容都结合与此作为参考。
根据一些实施例，如图2J所示，在形成重分布结构125之后，将外部连接件126安装（或接合至）在重分布结构125的接合焊盘（未示出）上。载体201上的管芯接受电测试以检查管芯的功能以及形成的TPV122″、重分布结构125和接合的外部连接件126的质量。在一些实施例中，还进行可靠性测试。
根据一些实施例，如图2K所示，在接合焊盘上安装外部连接件126之后，倒转图2J中的结构并将其附着在胶带219。根据一些实施例，胶带219是感光的并且在完成有关的封装工艺之后通过向载体201照射紫外（UV）光容易将其从载体201上剥离。随后，去除载体201和粘合层202。激光可以用来提供热量以去除粘结层。图2L示出了去除载体201和粘合层202之后的结构。根据一些实施例中，如图2M所示，去除粘合层202之后，去除镀晶种层204。通过诸如湿蚀刻的蚀刻来去除镀晶种层204。为了去除铜，可使用含有磷酸（H3PO4）和过氧化氢（H2O2）的水溶液。如果镀种晶层204包括诸如Ti层的扩散阻挡层，则可使用HF的水溶液。在一些实施例中，去除部分第一导电层203以在每一个TPV122″中都形成凹槽（未示出）。
根据一些实施例，如图2N所示，在去除镀晶种层204之后，去除胶水层210。如上所述，胶水层210可由管芯附着膜（DAF）制成，管芯附着膜可通过包含四甲基氢氧化铵（TMAH）和二甲基亚砜（DMSO）的湿剥离工艺来去除。在一些实施例中，没有去除胶水层210而是将其保留以帮助散发管芯121产生的热量。
不管是否去除胶水层210（根据需要），然后使封装的管芯单一化为单个封装管芯。通过管芯切割来完成单一化过程。在完成单一化之后，从封装管芯上去除胶带219。根据一些实施例，图2O示出了在去除胶带219之后的封装管芯120′。在示出的实例中，图2O中的区域X包括两个TPV122。
然后在管芯封装件120′的上方放置管芯封装件110。根据一些实施例，如图2P所示，管芯封装件110的外部连接件117接合至管芯封装件120′的TPV122″。由于第一导电层203的插入，由连接件117和TPV122″形成的接合结构260′具有更薄的IMC层142′，其由连接件117的焊料和诸如Ni的导电材料形成。诸如Ni:Sn的IMC以慢于由焊料和铜（Cu:Sn）形成的IMC的速率形成。图2P中的区域Y示出了接合结构260′和IMC层142′。
图3A示出了根据一些实施例的图2O中的区域X的放大视图。区域X包括被模塑料123包围的TPV122″。TPV122″连接至被钝化层212和214隔离的RDL213。每一个TPV122″都具有高度为D1A的第一导电层203和高度为D2A的第二导电层207。在一些实施例中，D1A的范围介于约0.5μm至约10μm之间。在一些实施例中，D2A的范围介于约50μm至约300μm之间。根据一些实施例，图3B示出了图2Q的区域Y的放大视图。图3B示出了在焊料中的锡和第一导电层203之间形成的IMC层142′。例如，如果第一导电层203由Ni制成，则形成含Ni:Sn的IMC。在一些实施例中，IMC层142′的厚度范围介于约0.5μm至约10μm之间。在一些实施例中，IMC层142′远比图1B所述的IMC层142（含Cu:Sn）薄。因此，第一导电层203用作TPV122″中的第二（或主要）导电层207的保护层。
此外，由于第一导电层203不太可能或不可能氧化，因此大大降低了形成类似于图1B中的氧化物层141的界面氧化物层的风险，在很多情况下，这种风险降低为零。如果在与连接件117接合之前使用了助焊剂预处理，则将会更稳定地去除表面氧化物层（如果有表面氧化物层的话）。从而，在管芯封装件110和120′之间形成的接合结构260比不具有第一导电层203的接合结构更强健。可在用于形成第二导电层207的集成镀系统中形成第一导电层203。形成第一导电层203的附加成本更为合理并且更具制造价值。
可将形成作为TPV的一部分的诸如层203的保护导电层从而降低TPV的表面氧化并且降低上述形成的IMC的量的概念扩展到包括其他类型的实施例。根据一些实施例，图4A示出了TPV122I。图4A示出了在紧邻第一导电层203I处形成第三导电层223I，而第一导电层203I紧邻第二导电层207I处形成。在上述的工艺流程中，第三导电层223I在镀第一导电层203I之前镀在镀晶种层204上方。图4B示出了根据一些实施例的TPV122I接合至连接件117以形成接合结构260I。
第三导电层223I由焊料制成。TPV122I中具有焊料层（层223I）使得接合结构260I的接合焊料的形成延伸至模塑料123的表面下方，这将IMC层142I从TPV122I的表面附近移动到TPV122I的表面下方。将IMC层142I移动至TPV122I的表面下方可加强接合结构260I。根据一些实施例，第一导电层的厚度D1I、第二导电层的厚度D2I和IMC层142I的厚度类似于图3A和图3B所述的厚度。在一些实施例中，第三导电层D3I的厚度介于约0.5μm至约30μm之间。在一些实施例中，图4B中位于模塑料123的表面下方的连接焊料117I的深度范围d3I介于约0.5μm至约30μm之间。d3I约等于D3I。
根据一些实施例，图5A示出了TPV122Ⅱ。图5A示出了在第一导电层203Ⅱ上方形成第三导电层223Ⅱ。如上图2M所述，去除部分第一导电层以在每个TPV中都形成凹槽（未示出）。如果将图3A中的结构用于形成图5A的结构，则使用用于去除第一导电层203Ⅱ（诸如Ni）的蚀刻化学过程来形成凹槽。如果将图4A的结构用于形成图5A的结构，则使用用于去除焊料的蚀刻化学过程来形成凹槽。应用诸如焊膏的第三导电层223Ⅱ来填充凹槽。如图5A所示，第三导电层223Ⅱ中的一部分凸出在TPV122Ⅱ上方。根据一些实施例，图5B示出了TPV122Ⅱ接合至连接件117以形成接合结构260Ⅱ。
第三导电层223Ⅱ由焊料制成。类似于图4A和4B的结构，TPV122Ⅱ中具有焊料层（层223Ⅱ）能够使接合结构260Ⅱ的接合焊料的形成延伸至模塑料123的表面下方，这使IMC层142Ⅱ从TPV122Ⅱ的表面附近移动至TPV122Ⅱ的表面下方。根据一些实施例，第一导电层的厚度D1Ⅱ、第二导电层的厚度D2Ⅱ和IMC层142Ⅱ的厚度类似于图3A和图3B所述的厚度。在一些实施例中，第三导电层D3Ⅱ的厚度范围介于约0.5μm至约30μm之间。在一些实施例中，凹槽部分的高度HII介于约0.5μm至约30μm之间。在一些实施例中，图5B中位于模塑料123的表面下方的连接焊料117Ⅱ的深度d3Ⅱ介于约0.5μm至约30μm之间。
图6A示出了根据一些实施例的TPV122Ⅲ。TPV122Ⅲ类似于图3A中的TPV122″。然而，第二导电层207Ⅲ由焊料而非铜制成，并且第一导电层203Ⅲ由Cu或Ti制成。焊料比铜便宜并且具有良好的导电性。将焊料用作第二导电层可以降低制造成本。如以上图2M所述，在去除镀晶种层204的过程中通过蚀刻去除由Cu或Ti制成的第一导电层203Ⅲ。可使用用于蚀刻镀晶种层204的化学物来移除第一导电层203III。根据一些实施例，图6B示出了去除第一导电层203Ⅲ之后的TPV122Ⅲ′。形成凹槽224Ⅲ。在一些实施例中，凹槽224Ⅲ的高度HⅢ介于约0.5μm至约30μm之间。
根据一些实施例，如图6C所示，TPV122Ⅲ′接合至连接件117以形成接合结构260Ⅲ。连接件117中的焊料填充位于TPV122Ⅲ′表面附近的凹槽。
根据一些实施例，图7A示出了TPV122Ⅳ。TPV122Ⅳ类似于图4A的TPV122I。第一导电层203Ⅳ类似于第一导电层203I。第二导电层207Ⅳ类似于第二导电层207I。然而，第三导电层223IV由Cu或Ti而非焊料制成。如以上图2M所述，在去除镀晶种层204的过程中通过蚀刻去除由Cu或Ti制成的第三导电层223Ⅳ。用于蚀刻镀晶种层的化学物可用于去除第一导电层203Ⅳ。根据一些实施例，图7B示出了去除第三导电层223IV之后的TPV122Ⅳ′。在一些实施例中，第三导电层223Ⅳ的薄层仍然保留在203Ⅳ上方。在完全或部分地去除第三导电层223Ⅳ后形成凹槽224Ⅳ。在一些实施例中，凹槽224Ⅳ的高度HⅣ介于约0.5μm至约30μm之间。
根据一些实施例，如图7C所示，TPV122Ⅳ′接合至连接件117以形成接合结构260Ⅳ。连接件117中的焊料填充TPV122Ⅳ′表面附近的凹槽。如果第三导电层223Ⅳ的薄层仍然在TPV122Ⅳ′中并且已被氧化，则氧化层可通过蚀刻工艺、助焊剂来去除或在接合后溶于焊料中。根据一些实施例，图7C示出了在第一导电层203Ⅳ和连接件117的焊料之间形成的IMC层142Ⅳ。IMC层142Ⅳ的厚度范围类似于图3B中的IMC层142′。
根据一些实施例，图8A示出了TPV122Ⅴ。TPV122Ⅴ类似于图7A中的TPV122Ⅳ。第三导电层223Ⅴ类似于第三导电层223Ⅳ。第一导电层203Ⅴ类似于第一导电层203Ⅳ。第二导电层207Ⅴ类似于第二导电层207Ⅳ。然而，如图8A所示，在第一导电层203Ⅴ和第三导电层223Ⅴ之间形成第四导电层225V。如上所述，第三导电层223Ⅴ由Cu或Ti制成。第四导电层225Ⅴ由焊料形成。在一些实施例中，第四导电层225Ⅴ的厚度D4Ⅴ介于约0.3μm至约2μm之间。
如上所述，在去除镀晶种层204的过程中通过蚀刻来去除由Cu或Ti制成的第三导电层223Ⅴ。根据一些实施例，图8B示出了去除第三导电层223Ⅴ之后的TPV122Ⅴ′。形成凹槽224Ⅴ。在一些实施例中，凹槽224Ⅴ的高度HⅤ介于约0.3μm至约2μm之间。
根据一些实施例，如图8C所示，TPV122Ⅴ′接合至连接件117Ⅴ以形成接合结构260Ⅴ。连接件117中的焊料填充位于TPV122Ⅴ′表面附近的凹槽。根据一些实施例，图8C示出了在第一导电层203Ⅴ和连接件117Ⅴ的焊料之间形成的IMC层142Ⅴ。IMC层142Ⅴ的厚度范围类似于图3B的IMC层142′。
在形成主导电层之前，通过一种或多种镀工艺在TPV中形成上述附加导电层。可在集成系统中实施不同的镀工艺。附加的成本是有限的。在去除镀晶种层的过程中通过附加的蚀刻形成位于TPV端部的凹槽。如果被去除以形成凹槽的导电层由Cu或Ti制成，则蚀刻工艺仅仅是去除镀晶种层工艺的延续。它可能仅仅涉及附加的蚀刻时间。如果去除的导电层不由Cu或Ti制成，则涉及不同的蚀刻工艺。然而，可以在集成系统中进行形成凹槽的蚀刻和去除镀晶种层的蚀刻。有关形成凹槽的制造成本也是有限的。然而，不太可能氧化并且不太可能与焊料形成IMC的附加导电层的保护层提高了成品率并且提高了在管芯封装件之间形成的接合结构的可靠性。凹槽也提高了成品率和在管芯封装件之间形成的接合结构的可靠性。
本发明提供了在管芯封装件中形成具有多个导电层和/或凹槽的封装通孔（TPV）以及利用TPV形成具有接合结构的层叠封装（PoP）器件的机制的实施例。多个导电层中的一层用作TPV的主导电层的保护层。当保护层暴露给焊料时，保护层不太可能氧化并且具有较低的金属间化合物（IMC）形成速率。用其他管芯封装件的焊料来填充管芯封装件的TPV中的凹槽并且形成的IMC层位于TPV的表面下方，这加强了接合结构。
在一些实施例中，提供半导体管芯封装件。半导体管芯封装件包括半导体管芯和形成在半导体管芯封装件中的封装通孔（TPV）。将TPV设置为邻近半导体管芯，并且TPV包括第一导电层和第二导电层。第一导电层填充TPV的第一部分而第二导电层填充TPV的第二部分。半导体管芯封装件还包括重分布结构，并且重分布结构包括重分布层（RDL）。TPV和半导体管芯电连接至RDL，并且RDL能够实现半导体管芯的扇出（fan-out）。
在一些实施例中，提供了半导体管芯封装件。半导体管芯封装件包括半导体管芯和形成在半导体管芯封装件中的封装通孔（TPV）。将TPV设置为邻近半导体管芯，其中TPV包括导电层和凹槽。半导体管芯还包括重分布结构，并且重分布结构包括重分布层（RDL）。TPV和半导体管芯电连接至RDL，并且RDL能够实现半导体管芯的扇出。凹槽导电层的与RDL相对的一侧。
在其他实施例中，提供了层叠封装（PoP）器件。PoP器件包括第一管芯封装件。第一管芯封装件包括第一半导体管芯和封装通孔（TPV）。将TPV设置为邻近半导体管芯，并且TPV包括第一导电层和第二导电层。PoP器件还包括第二管芯封装件。第二管芯封装件包括第二半导体管芯和包含焊料的外部连接件。第二管芯封装件的外部连接件接合至第一管芯封装件的TPV。
尽管具体描述了本发明的实施例及其优点，但应当理解，在不背离所附权利要求限定的本发明的精神和范围的情况下，可作出各种改变、替代和变化。此外，本申请的范围不旨在受限于本说明书所述的工艺、机器装置、制造、物质组成、工具、方法和步骤的特定的实施例中。本领域的技术人员从本发明的公开中很容易理解，根据本发明，可使用与本发明所述的相应实施例执行基本上相同的功能或取得实质上相同结果的目前现有的或今后将被开发的工艺、机器装置、制造、物质组成、工具、方法或步骤。因此，所附权利要求旨在将这些工艺、机器装置、制造、物质组成、工具、方法或步骤包括在它们的范围内。

Claims (10)

1.一种半导体管芯封装件，包括：
半导体管芯；
模塑料，至少部分地封装所述半导体管芯；
封装通孔（TPV），形成在所述模塑料中，所述TPV设置为邻近所述半导体管芯，所述TPV包括第一导电层和第二导电层，并且所述第一导电层填充所述TPV的第一部分而所述第二导电层填充所述TPV的第二部分；以及
重分布结构，所述重分布结构包括重分布层（RDL），所述TPV和所述半导体管芯电连接至所述RDL，并且所述RDL能够实现所述半导体管芯的扇出。
2.根据权利要求1所述的半导体管芯封装件，其中，所述第一部分的高度介于约0.1μm至约30μm之间。
3.根据权利要求1所述的半导体管芯封装件，其中，所述第二部分的高度介于约50μm至约300μm之间。
4.根据权利要求1所述的半导体管芯封装件，其中，通过所述模塑料中的开口来暴露所述第一导电层的第一表面，并且所述第一表面基本上与所述模塑料的表面平齐。
5.根据权利要求1所述的半导体管芯封装件，其中，所述TPV的与所述RDL相对的端部相对于所述模塑料的顶面形成凹槽，所述凹槽的高度介于约0.1μm至约30μm之间。
6.根据权利要求1所述的半导体管芯封装件，其中，形成与所述第一导电层邻近并且与所述第二导电层相对的第三导电层。
7.根据权利要求6所述的半导体管芯封装件，其中，所述第三导电层由焊料形成。
8.根据权利要求1所述的半导体管芯封装件，其中，所述第一导电层由与铜相比不太可能氧化并且当结合至焊料时不太可能形成金属间化合物（IMC）的导电金属制成。
9.一种半导体管芯封装件，包括：
半导体管芯；
封装通孔（TPV），形成在所述半导体管芯封装件中，所述TPV设置为邻近所述半导体管芯，所述TPV包括导电层和凹槽；以及
重分布结构，所述重分布结构包括重分布层（RDL），所述TPV和所述半导体管芯电连接至所述RDL，并且所述RDL能够实现所述半导体管芯的扇出，所述凹槽位于所述导电层的与所述RDL相对的一侧。
10.一种层叠封装器件（PoP），包括：
第一管芯封装件，所述第一管芯封装件包括：
第一半导体管芯；和
封装通孔（TPV），所述TPV设置为邻近所述半导体管芯，所述TPV包括第一导电层和第二导电层；以及
第二管芯封装件，所述第二管芯封装件包括：
第二半导体管芯；和
包含焊料的外部连接件，
其中，所述第二管芯封装件的外部连接件接合至所述第一管芯封装件的TPV。
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