CN101083244A - 半导体封装及制造方法和衬底和半导体器件及制造方法 - Google Patents

半导体封装及制造方法和衬底和半导体器件及制造方法 Download PDF

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Publication number
CN101083244A
CN101083244A CNA2007101288247A CN200710128824A CN101083244A CN 101083244 A CN101083244 A CN 101083244A CN A2007101288247 A CNA2007101288247 A CN A2007101288247A CN 200710128824 A CN200710128824 A CN 200710128824A CN 101083244 A CN101083244 A CN 101083244A
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conductive pole
semiconductor packages
face
electrode
stacked
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CN100466244C (zh
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山口昌浩
中村博文
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Nec Toppan Electric Substrate Co Ltd
Micron Memory Japan Ltd
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Nec Toppan Electric Substrate Co Ltd
Elpida Memory Inc
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Abstract

一种半导体封装包括：衬底，含有连接到多个外部电极的布线图案；一或多个半导体芯片，连接到布线图案并安装在衬底上；导电柱，连接到预定外部电极并在纵向方向上起着中继电极作用；和树脂密封层，用来整体密封半导体芯片和导电柱处于一种其中导电柱上部终端面被暴露的状态。

Description

半导体封装及制造方法和衬底和半导体器件及制造方法
技术领域
本发明涉及路由系统及其管理规则条目的方法。
本发明涉及一种通过堆叠多个半导体封装形成的叠层型半导体存储器件，包含在叠层型半导体器件中的半导体封装及其制造方法。
背景技术
近些年，堆叠多个半导体封装从而整体形成叠层型半导体器件的POP(Package on Package)技术引起关注(比如，参见JP2005-45251)。叠层型半导体器件使用POP技术允许高密度封装并可通过确保对每一半导体封装独立执行测试而减化制造工艺。当执行这样的叠层型半导体器件时，需要形成可以将每一半导体封装与外部电连接的电极结构。比如，当使用BGA(球栅阵列，Ball Grid Array)封装时，为了电连接上层半导体封装，多个焊料球被形成在下层半导体封装的衬底下表面上，且部分焊料球通过通孔被连接到衬底上分离提供的焊料球连接盘。之后，通过在焊料球连接盘上形成焊料球实现了连接到布置在上层的半导体封装的结构。因此，能够形成一种可以经由下层半导体封装达到从外部连接到上层半导体封装的电极结构。
一般，在制作半导体封装中，必需将整个半导体封装用树脂密封，半导体芯片处于被安装在半导体衬底上的状态。然而，在具有上述传统电极结构的叠层型半导体器件中，由于上层半导体封装通过焊料球连接，所以不可避免地采用一种结构，其中用于密封的树脂被置于除下层半导体封装衬底上焊料球连接盘邻近区域和半导体芯片周围的狭窄区域之外被树脂密封。因此，由于下层半导体封装依据有否布置树脂区域之间的热膨胀系数差，存在衬底发生卷曲和/或变形的危险，这导致了叠层型半导体器件的缺陷。
发明内容
本发明的一个目的是提供一种可以电连接到上部半导体封装而不引起衬底的卷曲和/或变形的叠层型半导体器件以至于，在实现堆叠了具有多个半导体封装的叠层型半导体器件结构时，确保高可靠性和高密度封装。
本发明的一个方面是半导体封装包含：衬底，含有连接到多个外部电极的布线图案；一个或多个半导体芯片，连接到所述布线图案并安装在所述衬底上；导电柱，连接到前面所述外部电极并在纵向方向上起着中继电极的功能；和树脂密封层，用来整体密封所述半导体芯片和所述导电柱在其中所述导电柱的上部终端面被暴露的状态。
根据本发明的半导体封装，多个外部电极中的部分被连接到导电柱并起着到达上部终端面的中继电极的作用，以便实现下层与上层半导体封装间的电连接的结构。相比于例如用来连接的焊料球被直接置于衬底上的情况，通过采用这样一种使用导电柱作为中继电极的相对简单的结构，可以在衬底上宽面积地整体密封导电柱和半导体芯片。相应地，可以实现阻止由于树脂密封层的影响引起的衬底的卷曲和变形，并且因此可以实现高可靠性和高密度封装的半导体封装。
本发明的半导体封装中，所述导电柱可由铜制成。
本发明的半导体封装中，所述多个外部电极和被连接到所述导电柱的上部终端面的连接电极可为焊料球。
本发明的半导体封装中，所述导电柱暴露的终端面可形成在比所述树脂密封层的表面低的位置。
本发明的半导体封装中，在所述树脂密封层的一个表面上，包括所述导电柱位置的周缘区域的高度可比中央区域的高度低。
本发明的一个方面是具有导电柱的衬底包含：衬底，包含连接到多个外部电极的布线图案；一个或多个连接盘，形成在所述导电柱上并连接到一或多个半导体芯片；和导电柱，连接到预定的所述外部电极并在纵向方向起着中继电极的功能。
本发明的导电柱的衬底中，所述导电柱可由铜制成。
本发明的一个方面是一种叠层型半导体器件，通过叠置多个包括所述半导体封装的半导体封装而形成，并允许从所述预定外部电极到所需半导体封装通过所述导电柱连接。
本发明的叠层型半导体器件中，所述多个外部电极和用来在邻近的上和下半导体封装之间连接的连接电极可为焊料球。
本发明的一个方面是半导体封装的制造方法包含步骤：形成具有布线图案和在导电板一侧上的多个外部电极的衬底结构如此以至于预定的所述外部电极被连接到所述导电板部分地起着中继电极功能的位置；在所述导电板的另一侧通过在该处使用起着中继电极功能的一部分同时移除其它部分而形成导电柱；在所述衬底结构的所述导电板被移除一侧的表面安装一或多个半导体芯片；用树脂整体地密封所述一或多个半导体芯片和所述导电柱；和处理所述树脂表面以至于所述导电柱的一终端面被露出。
本发明的半导体封装制造方法中，所述导电柱可由铜制成。
本发明的半导体封装制造方法中，所述多个外部电极和被连接到所述导电柱上部终端面的连接电极可为焊料球。
本发明的半导体封装制造方法可进一步包含通过移除所述导电柱的上终端面使暴露的所述导电柱的上终端面的高度比所述树脂表面的高度稍低的步骤。
本发明半导体封装的制造方法可进一步包含形成的包括所述树脂表面上的导电柱位置的周缘区域的高度比中央区域的高度稍低的步骤。
本发明的一个方面是包括上面描述的半导体封装的叠层型半导体器件的制造方法，其中连接电极被连接到所述导电柱的上部暴露的终端面，用来依次连接到一或多个其它半导体封装如此以至于提供一种通过所述导电柱从所述预定外部电极到所需半导体封装的电连接。
如上所述，根据本发明，由于导电柱作为纵向方向上的中继电极形成在其中半导体芯片被安装在衬底上的半导体封装中，可以使用树脂整体密封半导体芯片和导电柱。于是，可以可靠地抑制衬底卷曲和变形的发生，并且纵向方向的电连接允许在堆叠半导体封装中不增加整体的尺寸。进一步，通过提供的导电柱终端面凹陷结构和树脂密封层表面的阶梯结构，可以中间空隙足够小的堆叠多个半导体封装来减薄半导体器件。
附图说明
本发明的上述和其它目的以及特征将在下文通过考虑后面的描述结合附图全面揭露，其中借助实例示例了一个实例，其中：
图1图示了第一实施例中叠层型半导体器件的横截面结构；
图2A至2C图示了第一实施例中叠层型半导体器件的制造方法步骤，到在铜板50上形成电解电镀层52的步骤；
图3A和3B图示了第一实施例中叠层型半导体器件的制造方法步骤，到绝缘层12形成后开口形成通孔17的步骤；
图4A至4C图示了第一实施例中叠层型半导体器件的制造方法步骤，到形成焊料球连接盘14与布线图案15的步骤；
图5A和5B图示了第一实施例中叠层型半导体器件的制造方法步骤，到在阻焊剂13形成后形成防蚀涂层55的步骤；
图6A和6B图示了第一实施例中叠层型半导体器件的制造方法步骤，到形成了铜柱18的步骤；
图7A和7B图示了第一实施例中叠层型半导体器件的制造方法步骤，到安装半导体芯片10和11的步骤；
图8A和8B图示了第一实施例中叠层型半导体器件的制造方法步骤，到铜柱18的终端面暴露后焊料球23固定的步骤；
图9图示了第二实施例中叠层型半导体器件的横截面结构；
图10图示了第二实施例中叠层型半导体器件的制造方法；
图11图示了第二实施例变形的叠层型半导体器件的横截面结构；和
图12图示了第二实施例变形的叠层型半导体器件的制造方法。
具体实施方式
下面将参考附图描述本发明的实施例。在这里，两个实施例分别描述为应用本发明的叠层型半导体器件。
首先将描述第一实施例的叠层型半导体器件的结构及其制造方法。图1示出了第一实施例的叠层型半导体器件的横截面结构。第一实施例的叠层型半导体器件具有应用本发明的第一半导体封装(在下文中，称为第一封装)1，和电连接到第一封装1并放置于第一封装1上的第二半导体封装(在下文中，称为第二封装)2。第一封装1与第二封装2是BGA封装并具有一种结构，其中用于电连接到外部并在封装间电连接的多个电极(焊料球)以矩阵形式彼此连接。
两个形成有如半导体存储器的电路的半导体芯片10和11被堆叠并被置于第一封装1中。下面的半导体芯片10通过粘着层安装在绝缘层12的中央上，并且上面的半导体芯片11通过粘着层安装在半导体芯片10上。布线层形成在绝缘层12下面并被阻焊剂13覆盖保护。焊料球连接盘14与布线图案15形成在布线层中被阻焊剂13覆盖。因此，包括布线图案15的衬底结构借助于绝缘层12和阻焊剂13形成。
多个焊料球16形成在第一封装1的下面，并且分别连接到焊料球连接盘14。多个焊料球16在第一封装1外周缘侧被安排成两行。外部焊料球16通过焊料球连接盘14与绝缘层12中的通孔17电连接到上部铜柱18。铜柱18是形成在与靠近外周缘的焊料球16相对的位置的圆柱形导电柱，在叠层型半导体器件的纵向方向起着中继电极的作用。
同时，靠近中央的焊料球16通过焊料球连接盘14和绝缘膜12中的通孔17电连接到形成在绝缘层12上表面的键合连接盘20。连接到半导体芯片10焊盘的键合线21或者连接到半导体芯片11焊盘的键合线22被电连接到每一个键合连接盘20。
另外，半导体芯片10和11、键合线21和22、以及铜柱18整体被堆叠在绝缘层12上的树脂密封层19密封。
如此，在图1中的第一封装1中，可以形成一种用来在纵向方向从焊料球16到铜柱18上部终端面连接的电极结构。然后，焊料球23作为用来连接到上层第二封装2的电极被连接到铜柱18的上部终端面。半导体芯片30被安装在第二封装2上。焊料球23以这种顺序连接到焊料球连接盘33、绝缘层31中的通孔、键合连接盘36以及键合线37，并如此电连接到半导体芯片30的焊盘。尽管第二封装2具有绝缘层31，但阻焊剂32和树脂密封层35如同在第一封装1中，其中并未设置相当于铜柱18的组件。
第一实施例中叠层型半导体器件的结构特征在于第一封装1中的电极结构包括铜柱18。关于下层第一封装1，半导体芯片10与11可以通过焊料球16电连接到外部。与此相反，关于上层第二封装2，第一封装1存在于半导体芯片30和外部之间。换句话说，形成了电极结构，允许从焊料球16到上部焊料球23通过铜柱18的电连接并从而形成了在外部与半导体芯片30之间电连接的路径。
如果未提供铜柱18，必需采取一种结构，其中另一焊料球形成在第一封装1的绝缘层12上并且第二封装2安装在该焊料球上。这种情况下，无法避免的得到一种结构，其中第一封装1的树脂密封层19布置于除被配置的用来连接到第二封装2的焊料球位置及其周围之外，这导致了衬底结构的卷曲和变形的发生。与此相反，在本实施例的结构中，可以将包括半导体芯片10、11和铜柱18的整个区域通过树脂密封层19整体密封，所以第一封装1保持了不卷曲和不变形。
能够使用焊料球23可以被连接到具有普通结构的封装像第二封装2。尽管图1中示出了包括两个半导体芯片10和11的第一封装1的结构，但安装在第一封装1上的半导体芯片的数量可以适当地改变，比如，1个，3个或更多，等等。相似的，2个或更多半导体芯片可以被安装在第二封装2上。
接下来将利用附图2至8描述第一实施例中的叠层型半导体器件的制作方法。首先，如图2A所示，具有预定厚度的铜板50(比如，150至200μm)被准备用来形成铜柱18。接下来，如图2B所示，镀层光刻胶51形成在铜板50的表面上。镀层光刻胶51通过涂覆或粘结光刻胶而形成，比如，使用光刻法，并通过曝光和显影与如图1所示的键合连接盘20一致的图案。之后，如图2C所示，电解电镀层52形成在未形成镀层光刻胶51的区域中，比如，使用电解电镀镍/金或者镍/铜方法。
接下来，如图3A所示，镀层光刻胶51被从其上形成有电解电镀层52的铜板50上移除，并且形成了绝缘层12。比如，通过粘结含有玻璃织布的环氧树脂材料使用层压法按压到移除了镀层光刻胶51的铜板50的上部，形成了绝缘层12。随后，如图3B所示，激光束被应用到绝缘层12与焊料球16相对应的位置以开口形成通孔17。比如，二氧化碳气体激光器可以用来开口形成通孔17。
接下来，如图4A所示，镀层光刻胶53形成在具有通孔17的绝缘膜12上。比如，使用与图2B中镀层光刻胶51相类似的光刻法，形成该镀层光刻胶53。此时，镀层光刻胶53的图案与图1所示的焊料球连接盘14的位置及布线图案15相一致。之后，如图4B所示，铜镀层54通过电解电镀铜方法在未形成镀层光刻胶53的区域形成。随后，如图4C所示，镀层光刻胶53被从镀层光刻胶53及铜镀层54表面的预定区域移除，所以焊料球连接盘14与布线图案15出现了。
接下来，如图5A所示，比如，使用光刻法形成了用来保护布线图案15表面的阻焊剂13，用于保护。焊料球连接盘14的表面通过进行电解电镀金工艺被保护。之后，如图5B所示，防蚀涂层55形成在铜板50的背面(与绝缘层12相反的表面)，其具有与图1中铜柱18的位置相一致的图案。在这种情况下，在铜板50的背表面上形成镀层光刻胶之后，比如，使用光刻法，镍层可以作为防蚀涂层55而形成。
之后，如图6A所示，在形成防蚀涂层55的铜板50背面表面进行刻蚀，并形成圆柱形的铜柱18。比如，通过碱溶液刻蚀，铜板50中未形成防蚀涂层55的区域被移除至到达绝缘层12的深度，剩余的区域成为铜柱18。此时，被镍掩蔽的键合连接盘20出现在绝缘层12背面表面上。之后，如图6B所示，防蚀涂层55被从铜柱18的底面移除。图6b中，相比于图6A顶面与底面翻转。
接下来，如图7A所示，半导体芯片10被安装在绝缘层12的中央上，之后半导体芯片11被安装在半导体芯片10上。粘着剂用来分别固定绝缘层12与半导体芯片10和11。进一步，键合线21和22分别连接到半导体芯片10、11及键合连接盘20之间。其后，如图7B所示，包括半导体芯片10和11、铜柱18以及类似物的整个区域通过覆盖树脂密封层19被整体密封。
接下来，如果8A所示，图7B中的密封树脂层19被研磨至暴露铜柱18的终端面。之后，如图8B所示，焊料球16作为外部电极被布置在焊料球连接盘14上并被固定在那。在铜柱18暴露的终端面进行表面处理之后，焊料球23作为连接电极被布置并附着在那。随后，上部焊料球23被预先集成附着到第二封装2的连接盘以便第二封装2被安装在第一封装1上，从而完成了具有如图1所示结构的叠层型半导体器件。
接下来，将描述第二实施例中的叠层型半导体器件的结构及其制作方法。图9示出了第二实施例中叠层型半导体器件的横截面结构。第二实施例的叠层型半导体器件具有第一封装1a和第二封装2。第二实施例的基本结构与第一实施例的相似，但第一封装1a的上部结构与第一实施例中的不同。在图9中，通过与图1中的相同的附图标记表征的组件与第一实施例具有相同的结构，所以其相关描述将被省略。
第二实施例的叠层型半导体器件特征在于第一封装1a的上部表面不是水平的并且铜柱18的终端面18a形成在较低的位置。更确切的说，如图9所示，每个铜柱18的上部在第一封装1a的上部面被移除，并且暴露的终端面18a比树脂密封层19的表面稍低。焊料球23被置于铜柱18的终端面18a上，并且第二封装2被安装在焊料球23上。
当采用图9所示的结构时，每个焊料球23被置于一种状态，其中其较低部分被嵌入到铜柱18的终端面18a的凹陷部分。在这种情况下，树脂密封层19在布置有树脂密封层19的每个焊料球23的周围起着焊料坝的作用，因此可以在制造过程中稳定地形成焊料球23并可提高成品率。进一步，由于铜柱18的终端面18a处于稍低的位置，所以这可以减小第一封装1a与第二封装2之间相对于相同尺寸的焊料球23产生的空隙，并且因此可以减小叠层型半导体器件的尺寸。
图9中的叠层型半导体器件的制造方法将在下面利用图10描述。这里，前面描述的第一实施例中图2至7的步骤一般适用于第二实施例，所以其相关的描述将被省略。同时，第二实施例与第一实施例的区别参照图10与第一实施例的图8，在下面描述。
首先，从图7B的状态，如图10A所示，激光束被应用于树脂密封层19每一铜柱18所在位置区域以移除其上部，因此铜柱18的终端面18被暴露。在这种情况下，有必要在先调整图7B状态中的铜柱18与树脂密封层19的高度以便得到理想的高度之间的差值。随后，如图10B所示，焊料球23被置于并附着在铜柱18的终端面18a。之后，预先装配的第二封装2被安装在焊料球23上，因此完成了具有图9所示结构的叠层型半导体器件。
接下来，将描述第二实施例的变形叠层型半导体器件。在下面描述的第二实施例的变形中，如图9所示的暴露的铜柱18的终端面18a形成在第一封装1a的上部较低位置的特征，它是另一个特征树脂密封层19本身的表面不是水平的，相反的具有阶梯结构。除了这一特征其基本结构与上面描述的第二实施例一样。
图11显示了第二实施例变形的叠层型半导体器件的横截面结构。在图11所示的变形中，第一封装1b的树脂密封层19具有凸起表面如此以至树脂密封层19的中央部分比周缘部分高。换句话说，在树脂密封层19的表面上，形成阶梯结构如此以至于中央区域19a比周缘区域19b高出预定高度，并且倾斜部分19c形成在区域19a与19b之间。另外，铜柱18的终端面18a的结构与图9中终端面18a的相同。
在这里，中央区域19a的高度受键合线22从半导体芯片11表面凸起的高度和树脂密封层19覆盖键合线22上部的厚度的限制。同时，周缘区域19b的高度并不受限于这样的因素并可以通过移除树脂密封层19的上部调整。相应地，通过采用图11所示的结构，可以相对地降低周缘区域19b的位置，同时确保中央区域19a的高度，并因此上层第二封装2可以被安装在较低位置。另外，也得到了降低铜柱18的终端面18a高度的效果，如此以至可以进一步减薄整个叠层型半导体器件。
图11的叠层型半导体器件的制造方法将利用图12描述。在这里，前面描述的第一实施例中图2至7A的步骤一般适用于第二实施例变形的每一步，因此相关描述将被省略。同时，第二实施例变形与第一实施例区别在于相应于图7B和8的步骤，示于图12。
首先，从图7A的状态，如图12A所示，第一封装1b通过树脂密封层19被覆盖，其表面被处理以至于形成了上面描述的包括中央区域19a、周缘区域19b和倾斜部分19c的阶梯结构。在这种情况下，通过使用具有凸起形状的树脂铸模，可以模铸图12A所示形状的阶梯结构。
接下来，如图12B所示，焊料球23通过如图10B相同的方法被置于并粘着在铜柱18的终端面18a。之后，预先装配的第二封装2被安装在焊料球23上，因此完成了具有如图12所示结构的叠层型半导体器件。
在上面描述的第二实施例变形中，实例中树脂密封层19表面的阶梯结构表面形成了，铜柱18的终端面18a结构也形成了。然而，也可实现仅具有阶梯结构表面的树脂密封层19的叠层型半导体器件。更确切的说，通过应用如图11所示的阶梯结构的树脂密封层19加至图1所示结构的叠层型半导体器件，也可以整体上降低第一封装1和第二封装2的高度。
尽管上述本发明是基于第一和第二实施例特定的描述，但本发明并不受限于上面描述的每一实施例，并可以在不脱离其主题范围被用于实践。例如，实施例中的叠层型半导体器件具有包括下层第一封装1(1a，1b)和上层第二封装2的双层结构，但本发明广泛应用于具有更大数量的叠层型半导体封装的叠层型半导体器件。在这种情况下，实施例中第一封装1的电极结构形成在除最高层外每一半导体封装中，并且典型封装可以堆叠在最高层。进一步，因为实施例中电极结构使用铜柱18，本发明广泛应用于形成通过使用另一导电材料导电柱的电极结构的情况。
在第一和第二实施例中，在制造叠层型半导体器件过程中采用刻蚀铜板50的方法形成铜柱18，并通过以这样方式使用铜板50，可以高精度的确定铜柱18的高度。当高精度的保证铜柱18的高度时，通过树脂密封层19密封第一半导体封装1之后，可以容易地暴露铜柱18终端面的电极部分，并在堆叠若干半导体封装中提高组装效率。
本发明并不局限于上面描述的实施例，并且可以进行各种各样的变化和变形而不脱离本发明范围。
本申请基于2006年1月19日申请的日本专利申请号No.2006-011674，其全部内容在此作为参考引入。

Claims (15)

1、一种半导体封装，包括：
衬底，包含有连接到多个外部电极的布线图案；
一或多个连接到所述布线图案并安装在所述衬底上的半导体芯片；
导电柱，连接到预定的所述外部电极并在纵向方向上起着中继电极作用；和
树脂密封层，用来整体密封所述半导体芯片和所述导电柱，所述导电柱的上部终端面被暴露。
2、根据权利要求1所述的半导体封装，其中所述导电柱由铜制成。
3、根据权利要求1所述的半导体封装，其中所述多个外部电极和要被连接到所述导电柱的上部终端面的连接电极是焊料球。
4、根据权利要求3所述的半导体封装，其中所述导电柱的暴露的终端面被形成在比所述树脂密封层的表面低的位置。
5、根据权利要求3或4所述的半导体封装，其中在所述树脂密封层的表面上，包括所述导电柱位置的周缘区域的高度比中央区域的高度低。
6、一种具有导电柱的衬底，包括：
衬底，包含有连接到多个外部电极的布线图案；
一或多个连接盘形成在所述导电柱上并连接到一或多个半导体芯片；和
导电柱，连接到预定的所述外部电极并在纵向方向上起着中继电极的作用。
7、根据权利要求6所述的具有导电柱的衬底，其中所述导电柱由铜制成。
8、一种叠层型半导体器件，通过堆叠包括根据权利要求1所述的半导体封装的多个半导体封装而形成，并允许通过所述导电柱从所述预定外部电极到期望的半导体封装的连接。
9、根据权利要求8所述的叠层型半导体器件，其中所述的多个外部电极和用来连接邻近的上和下半导体封装之间的连接电极是焊料球。
10、一种半导体封装的制造方法，包括如下步骤：
形成衬底结构，具有布线图案和在导电板一侧面上的多个外部电极，使得预定的所述外部电极被连接到所述导电板部分地起着中继电极作用的位置；
使用在预定位置起着中继电极作用的一部分，同时移除其它部分，从而在所述导电板的另一侧面形成导电柱；
在所述导电板被移除的一侧，在所述衬底结构的表面安装一或多个半导体芯片；
用树脂整体地密封所述一或多个半导体芯片和所述导电柱；和
处理所述树脂表面从而暴露所述导电柱的一终端面。
11、根据权利要求10所述的半导体封装的制造方法，其中所述导电柱由铜制成。
12、根据权利要求10所述的半导体封装的制造方法，其中所述多个外部电极和被连接到所述导电柱上部终端面的连接电极是焊料球。
13、根据权利要求12所述的半导体封装的制造方法，进一步包含步骤：通过移除所述导电柱的上终端面，暴露高度稍低于所述树脂表面的高度的所述导电柱的上终端面。
14、根据权利要求12或13所述的半导体封装的制造方法，进一步包含步骤：形成周缘区域，所述周缘区域包括所述树脂表面上、高度稍低于中央区域的高度的导电柱位置的。
15、一种包含根据权利要求1中所述的半导体封装的叠层型半导体器件的制造方法，其中连接电极连接到所述导电柱的上部暴露终端面，用来依次连接到一或多个其它半导体封装，从而提供通过所述导电柱从所述预定外部电极到期望的半导体封装的电连接。
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