CN102117798A - 堆叠封装 - Google Patents

堆叠封装 Download PDF

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Publication number
CN102117798A
CN102117798A CN2010101896672A CN201010189667A CN102117798A CN 102117798 A CN102117798 A CN 102117798A CN 2010101896672 A CN2010101896672 A CN 2010101896672A CN 201010189667 A CN201010189667 A CN 201010189667A CN 102117798 A CN102117798 A CN 102117798A
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Prior art keywords
semiconductor chip
electrode
piles
size
stacked package
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Granted
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CN2010101896672A
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CN102117798B (zh
Inventor
金钟薰
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

本发明涉及一种堆叠封装，包括具有第一尺寸的第一半导体芯片和具有大于第一尺寸的第二尺寸的一个或更多个第二半导体芯片。第一半导体芯片具有其上设置有接合衬垫的第一表面、与第一表面相反的第二表面、以及穿透第一表面和第二表面的第一穿透电极。一个或更多个第二半导体芯片堆叠在第一半导体芯片的第二表面上，且具有电连接到第一穿透电极的第二穿透电极。成型部分邻接第一半导体芯片的一个或更多个侧表面，使得包括第一尺寸和成型部分的尺寸的总体尺寸等于或大于第二尺寸。

Description

堆叠封装
技术领域
本发明总体上涉及半导体技术，更具体地涉及堆叠封装。
背景技术
为了满足微型化和高性能的需求，需要提供高容量的半导体模块的新技术。一种设置高容量的半导体模块的方法是制造高度集成的存储芯片。存储芯片的高度集成度是通过在半导体芯片的现有有限的空间中集成更多数目的单元来实现。
然而，存储芯片的高集成度既要求高精度技术，诸如用于获得精细的线宽的技术，又要求一个漫长的开发期。认识到这些限制，堆叠技术已被提议为设置高容量半导体模块的另一种方法。
两种这样的堆叠技术包括在单个封装体中埋入两个堆叠芯片的第一种方法以及堆叠独立封装的两个分离封装的第二种方法。最近，已发现另一种技术，其中由诸如铜的导电材料制成的穿透电极以这样的方式形成在半导体芯片中：当堆叠半导体芯片时，半导体芯片可通过穿透电极电连接。
通过使用穿透电极，I/O衬垫可以精细节距被接合，使得I/O衬垫的数目增加。此外，由于形成了更多数目的I/O衬垫，可改善半导体芯片之间的信号传输速度。而且，由于可实现半导体芯片的三维设计，因此可提高半导体芯片的性能。
当制造堆叠封装使得可通过穿透电极形成上和下半导体芯片之间的电连接时，若向下放置的芯片(以下称为“下芯片”)与向上放置的芯片(以下称为“上芯片”)的尺寸不同，则很可能产生缺陷。例如，在下芯片具有小于上芯片的尺寸的情况下，可以实施堆叠而上芯片处于结构上的不稳定状态，堆叠本身可能是不可行的。
发明内容
本发明的实施例包括堆叠封装，其即使在上方堆叠的芯片具有大于下方设置的芯片的尺寸时，也可确保结构稳定性。
在本发明的一个实施例中，堆叠封装包括第一半导体芯片，该第一半导体芯片具有第一尺寸，并具有其上设置有接合衬垫的第一表面和与第一表面相反的第二表面、以及穿透第一表面和第二表面的第一穿透电极；一个或更多个第二半导体芯片，具有大于第一尺寸的第二尺寸，堆叠在第一半导体芯片的第二表面上，且具有彼此电连接并且电连接到第一穿透电极的第二穿透电极；以及成型部分(molding part)，邻接第一半导体芯片的一个或更多个侧表面使得包括第一尺寸和成型部分的尺寸的总尺寸等于或大于第二尺寸。
堆叠封还可包括第三半导体芯片，设置在一个或更多个堆叠的第二半导体芯片之中最上的第二半导体芯片上，以电连接到最上的第二半导体芯片的第二穿透电极。
堆叠封装可进一步包括形成在成型部分上和一个或更多个堆叠的第二半导体芯片上的密封构件；形成在第一半导体芯片的第一表面上以连接到接合衬垫的再布线(redistribution lines)；形成在第一半导体芯片的第一表面上以及再布线上的绝缘层，该绝缘层具有暴露部分再布线的开口；以及结合到再布线的暴露部分的外部连接端子。
堆叠封装还可包含底部填充物(underfill)，形成在第一半导体芯片与一个或更多个堆叠的第二半导体芯片之中最下的半导体芯片之间，以及在堆叠的第二半导体芯片之间。
当第一半导体芯片具有四边形形状时，成型部分可形成为覆盖第一半导体芯片的两个相对的侧表面或四个侧表面。
堆叠封装还可包括基板，该基板具有面对第一半导体芯片的第一表面的第三表面，且在第三表面上设置有电连接到第一半导体芯片的接合衬垫的第一连接衬垫，以及与第三表面相反的第四表面，且在第四表面上设置有第二连接衬垫；连接构件，电连接第一半导体芯片的接合衬垫和基板的第一连接衬垫；密封构件，形成在基板的第三表面上以及第二半导体芯片和成型部分上；以及结合到基板的第二连接衬垫的外部连接端子。
堆叠封装可进一步包括底部填充物，形成在第一半导体芯片和成型部分与基板之间。
堆叠封装可进一步包括基板，该基板具有窗口、面对第一半导体芯片的第一表面的第三表面，以及与第三表面相反的第四表面，第四表面上设置有电连接到第一半导体芯片的接合衬垫的第一连接衬垫、以及设置在第一连接衬垫以外的第二连接衬垫；连接构件，穿过窗口并连接第一半导体芯片的接合衬垫和基板的第一连接衬垫；密封(encapsulation)构件，形成为密封包括第二半导体芯片和成型部分的基板的第三表面以及包含连接构件的基板的窗口；以及外部连接端子，结合到基板的第二连接衬垫。
堆叠封装可进一步包括插入成型部分和基板之间的粘附构件。
在本发明的另一个实施例中，堆叠封装包括第一半导体芯片，具有第一尺寸并具有其上设置有接合衬垫的第一表面、与第一表面相反的第二表面、以及穿透第一表面和第二表面的第一穿透电极；一个或更多个第二半导体芯片，具有大于第一尺寸的第二尺寸，堆叠在第一半导体芯片的第二表面上，且具有彼此电连接且电连接到第一穿透电极的第二穿透电极，以及彼此电连接的第三穿透电极；虚设芯片，设置在一个或更多个堆叠的第二半导体芯片之中最下的第二半导体芯片下面且与第一半导体芯片分离，并且具有电连接到第三穿透电极的第四穿透电极；以及成型部分，邻接第一半导体芯片和虚设芯片的一个或更多个侧表面，从而获得等于或大于第二尺寸的尺寸。
第三穿透电极可形成为穿过第二半导体芯片的与第二穿透电极分离的部分。
虚设芯片可以形成为在其中没有电路部分而仅具有第四穿透电极。
当第一半导体芯片具有四边形形状时，成型部分可形成为覆盖第一半导体芯片和虚设芯片的两个相对的侧表面或四个侧表面。
堆叠封装可进一步包括第三半导体芯片，设置在一个或更多个堆叠的第二半导体芯片之中最上的第二半导体芯片上，以电连接到最上的第二半导体芯片的第二穿透电极。
堆叠封装可进一步包括密封构件，形成在成型部分上和一个或更多个堆叠的第二半导体芯片上；再布线，形成在第一半导体芯片的第一表面上以电连接到接合衬垫和第四穿透电极；绝缘层，形成在第一半导体芯片的第一表面上以及再布线上，并具有暴露出部分再布线的开口；以及外部链接端子，结合到再布线的暴露部分。
堆叠封装可进一步包括底部填充物，形成在第一半导体芯片和虚设芯片与一个或更多个堆叠的第二半导体芯片之中的最下的第二半导体芯片之间，以及形成在堆叠的第二半导体芯片之间。
在本发明的另一个实施例中，堆叠封装包括第一半导体芯片，该第一半导体芯片具有第一尺寸，且具有其上设置有接合衬垫的第一表面、与第一表面相反的第二表面、以及穿透第一表面和第二表面的第一穿透电极；一个或更多个第二半导体芯片，具有大于第一尺寸的第二尺寸，堆叠在第一半导体芯片的第二表面上，且具有彼此电连接并电连接到第一穿透电极的第二穿透电极；成型部分，邻接第一半导体芯片的一个或更多个侧表面使得包括第一尺寸和成型部分的尺寸的总尺寸等于或大于第二尺寸；散热器，设置在第一半导体芯片、成型部分与一个或更多个堆叠的第二半导体芯片之中最下的第二半导体芯片之间，以及沿着一个或更多个第二半导体芯片的侧表面延伸；底部填充物，形成在堆叠的第二半导体芯片之间的间隔中；再布线，形成在第一半导体芯片的第一表面上以连接到接合衬垫；绝缘层，形成在第一半导体芯片的第一表面上以及再布线上，且具有暴露出部分再布线的开口；外部连接端子，结合到再布线的暴露部分。
散热器可形成为散热器的沿着堆叠的第二半导体芯片的侧表面设置的部分接触堆叠的第二半导体芯片的侧表面。
散热器可形成为散热器的沿着堆叠的第二半导体芯片的侧表面设置的部分与堆叠的第二半导体芯片的侧表面分离。
堆叠封装可进一步包括底部填充物，形成在堆叠的第二半导体芯片的侧表面与散热器之间的间隔中。
堆叠封装可进一步包括第三半导体芯片，设置在堆叠的第二半导体芯片之中最上的第二半导体芯片上，以电连接到最上的第二半导体芯片的第二穿透电极。
在本发明的另一个实施例中，用于制造堆叠封装的方法包含将第一半导体芯片结合到临时晶片上使得第一半导体芯片的第一表面面对临时晶片的步骤，每个第一半导体芯片具有其上设置有接合衬垫的第一表面、与第一表面相反的第二表面，以及当从第一表面测量时，形成为未到达第二表面的深度的穿透电极；在临时晶片上形成成型部分以覆盖第一半导体芯片；处理成型部分和每个第一半导体芯片的第二表面以暴露第一穿透电极；在处理过的成型部分和第一半导体芯片的第二表面上堆叠一个或更多个第二半导体芯片，一个或更多个第二半导体芯片具有大于第一尺寸的第二尺寸且具有彼此电连接且电连接到第一穿透电极的第二穿透电极；在处理过的成型部分上和堆叠的第二半导体芯片上形成密封构件；移除临时晶片以暴露包括接合衬垫的第一半导体芯片的第一表面以及第一穿透电极；在第一半导体芯片的第一表面和成型部分上形成再布线以分别连接接合衬垫；在第一半导体芯片的第一表面和再布线上以及成型部分上形成绝缘层，以暴露部分再布线；以及结合外部连接端子到再布线的暴露部分。
在结合外部连接端子的步骤后，此方法可进一步包括将得到的结构切割成为单元级的步骤。
附图说明
图1示出根据本发明的实施例的堆叠封装的截面视图。
图2A至2H示出用于说明根据本发明的实施例的堆叠封装的制造方法的截面视图。
图3示出根据本发明实施例的堆叠封装的截面视图。
图4示出根据本发明实施例的堆叠封装的截面视图。
图5示出根据本发明实施例的堆叠封装的截面视图。
图6示出根据本发明实施例的堆叠封装的截面视图。
具体实施方式
以下，将参考附图详细描述本发明的具体实施例。
应理解这里的图不必按比例，并且在一些情况下可以夸大比例以更清晰地描述本发明的某些特征。
图1示出根据本发明第一实施例的堆叠封装的截面视图。
参看图1，根据本发明实施例的堆叠封装100包括第一半导体芯片110、围绕第一半导体芯片110的侧表面的成型部分130、以及堆叠在第一半导体芯片110和成型部分120上的一个或更多个第二半导体芯片120。
在实施例中，第一半导体芯片110具有第一表面A以及第二表面B，在第一表面A上设置有接合衬垫112，第二表面B与第一表面A相反。多个第一穿透电极114形成在第一半导体芯片110中，且从第一表面A穿透第一半导体芯片的本体到第二表面B。例如，可形成第一穿透电极114以穿透第一半导体芯片110的中心部分。例如当从上面看时，第一半导体芯片110具有第一尺寸且为四边形形状。例如，当观察第一半导体芯片的第二表面B时，第二表面B的面积具有第一尺寸，由此第一半导体芯片110与第二半导体芯片120之间形成台阶(step)。
同时，尽管未示出，应理解第一半导体芯片110具有形成在其中的电路部分，且用于将接合衬垫112电连接到它们对应的第一穿透电极114的连接线形成在第一半导体芯片110的第一表面A上。
在实施例中，第二半导体芯片120从上面看时具有四边形形状且具有大于第一半导体芯片110的第一尺寸的第二尺寸。也就是说，当从上面看时，第二半导体芯片120的面积是大于第一尺寸的第二尺寸。一个或更多个第二半导体芯片120(与1中显示为四个)垂直堆叠在第一半导体芯片110的第二表面B上。一个或更多个堆叠的第二半导体芯片120具有多个第二穿透电极124。第二穿透电极124形成在对应于穿透第一半导体芯片110形成的第一穿透电极114的位置处，使得它们可彼此电连接并电连接到第一穿透电极114。在实施例中，各第二半导体芯片的第二穿透电极114形成在第二半导体芯片120的中心部分处，且与第一穿透电极114对准，以彼此电连接且电连接到第一半导体芯片110的第一穿透电极114。
同时，尽管未示出，应理解与第一半导体芯片110的情况相似，一个或更多个第二半导体芯片120具有形成在其中的电路部分，且接合衬垫和用于将接合衬垫电连接到它们对应的第二穿透电极124的连接线形成在第二半导体芯片120的面对第一半导体芯片110的第二表面B的表面。
在图1所示的实施例中，形成成型部分130以围绕具有第一尺寸的第一半导体芯片110的侧表面，由此，成型部分130与第一半导体芯片110的结合体具有等于或大于第二半导体芯片120的第二尺寸的尺寸。尽管优选形成成型部分130以围绕具有四边形形状的第一半导体芯片110的所有的四个侧表面，但情况可能是，通过形成成型部分130使其仅与第一半导体芯片的一个以上但不是所有的四个侧表面接界(邻接)，也可以充分地增加总尺寸。例如，在实施例中，成型部分可仅仅形成在第一半导体芯片110的两个相对的侧表面上。因此，成型部分130可被理解为在具有第一尺寸的第一半导体芯片110上堆叠具有大于第一尺寸的第二尺寸的第二半导体芯片120时确保结构稳定性。
根据本发明的实施例的堆叠封装100还包括密封构件140，形成在成型部分130上和一个或更多个堆叠的第二半导体芯片120上。密封构件140用以保护第一和第二半导体芯片110和120不受外部影响，且例如可由诸如EMC(环氧树脂塑封料，epoxy molding compound)的材料制成。
根据本发明的实施例的堆叠封装100可进一步包括底部填充物(未示出)，其形成在设置在一个或更多个堆叠的第二半导体芯片120之中的最下的第二半导体芯片120(以下称作“最下的第二半导体芯片120a”)与第一半导体芯片110之间，以及在最下的第二半导体芯片120a与成型部分130之间。填充物也可形成在堆叠的第二半导体芯片120之间。当然，在根据本发明的实施例的堆叠封装100中，可省略底部填充物，且替代地，最下的第二半导体芯片120a与第一半导体芯片110之间，最下的第二半导体芯片120a与成型部分130之间，以及堆叠的第二半导体芯片120之间的间隔可被密封构件140填充。
根据本发明的实施例的堆叠封装100进一步包括：再布线150，其形成在第一半导体芯片110的第一表面A上，且其电连接到对应的接合衬垫112；绝缘层160，其形成在第一半导体芯片110的第一表面A上以及再布线150上，且其形成为暴露部分再布线150；以及外部连接端子170，其分别结合到再布线150的暴露部分。绝缘层160例如包含阻焊剂；而外部连接端子170例如包含焊料球。
尽管未示出，根据本发明实施例的堆叠封装100可进一步包括第三半导体芯片，其设置在一个或更多个堆叠的第二半导体芯片120之中设置于最上的第二半导体芯片120(以下称为“最上的第二半导体芯片120b”)上，并且电连接到最上的第二半导体芯片120b的第二穿透电极124。可这样理解，第三半导体芯片形成为具有在其中的电路部分，而没有分离的穿透电极。第三半导体芯片具有多个接合衬垫，该多个接合衬垫设置在第三半导体芯片的面对最上的第二半导体芯片120b的表面上，且接合衬垫电连接到最上的第二半导体芯片120b的第二穿透电极124。
从以上描述中清楚的是，在根据本发明的实施例的封装中，由于第一半导体芯片的第一尺寸和成型部分的尺寸的结合尺寸等于或大于第二半导体芯片的第二尺寸，所以即使在第一半导体芯片和成型部分上堆叠一个或更多个第二半导体芯片时也可确保结构的稳定性。
这样，由于保证了结构稳定性，根据本发明的第一实施例的封装提供了增加制造产量和改善产品可靠性的优势。
如2A至2H示出根据本发明实施例的堆叠封装的制造方法的截面视图。下面将描述此方法。
参看如2A，多个第一半导体芯片110以规则的间隔被结合到临时晶片200上。临时晶片200包含裸晶片或晶片形状的薄膜。每个第一半导体芯片110具有其上设置有接合衬垫112的第一表面A和与第一表面A相反的第二表面B。当从第一表面A测量时，第一穿透电极114形成到没有到达第二表面B的深度。每个第一半导体芯片110具有第一尺寸。这些第一半导体芯片110以这种方式被结合：它们的第一表面A面对临时晶片200。
参考图2B，成型材料132形成在临时晶片200上以覆盖第一半导体芯片110。成型部分132例如包含环氧树脂、聚合物、EMC等等。
参考图2C，移除成型材料132和第一半导体芯片110的部分厚度，由此，形成暴露出第一半导体芯片110的第一穿透电极114并且围绕第一半导体芯片110的侧表面的成型部分130。
尽管当第一半导体芯片具有四边形形状时，优选成型部分130形成为围绕第一半导体芯片110的所有的四个侧表面，但是成型部分130形成为仅与第一半导体芯片的一个以上但不是所有的四个侧表面接界也可以充分地增加总尺寸。例如，在实施例中，成型部分可仅仅形成在每个第一半导体芯片110的两个相对的侧表面上。在这样的情况下，先前步骤中的成型材料132可被理解为在形成成型材料132之后，被图案化以仅仅覆盖每个第一半导体芯片110的两个相对的侧表面和上表面。
参考图2D，一个或更多个第二半导体芯片120被堆叠在每个第一半导体芯片110和邻接或围绕形成部分130上。第二半导体芯片120具有大于第一半导体芯片110的第一尺寸的第二尺寸。因此，当一个或更多个第二半导体芯片120被堆叠在第一半导体芯片110上时，一个或更多个第二半导体芯片也被堆叠在围绕/邻接第一半导体芯片110的成型部分130上。一个或更多个堆叠的第二半导体芯片120具有形成在其中的第二穿透电极124。第二穿透电极124彼此电连接并电连接到第一半导体芯片110的第一穿透电极114，该第一半导体芯片110上堆叠有一个或更多个第二半导体芯片120。在实施例中，如图2D所示第一半导体芯片110的第一穿透电极114和第二半导体芯片120的第二穿透电极124通过沿垂直线对准彼此电连接。
这里，由于第二半导体芯片120被堆叠在每个第一半导体芯片110和成型部分130上，所以即使第二半导体芯片120具有大于第一半导体芯片110的尺寸，它们也可以结构稳定的方式堆叠。
参考图2E，密封构件140形成在成型部分130上和一个或更多个堆叠的第二半导体芯片120上。密封构件140例如包含EMC。
在形成密封构件140之前，第三半导体芯片(未示出)可被附加地结合到最上的第二半导体芯片120b，第三半导体芯片中没有形成穿透电极且接合衬垫设置在面对最上的第二半导体芯片120b的表面上。
在密封构件140形成之前，不论第三半导体芯片是否被结合，底部填充物(未示出)可被附加地形成在最下的半导体芯片120a与第一半导体芯片110和邻接的成型部分130之间。底部填充物也可形成在堆叠的第二半导体芯片120之间。当然，底部填充物可以被省略，且在这样的情况下，最下的第二半导体芯片120a和第一半导体芯片110和邻接的成型部分130之间的间隔，以及在堆叠的第二半导体芯片120之间的间隔被密封构件140填充。
参考图2F，已经过先前处理步骤且形成有密封构件140的生成的结构被颠倒使得临时晶片200面向上。在这样的状态下，临时晶片200被移除使得第一半导体芯片110的第一表面A、设置在第一表面A上的接合衬垫112、以及第一穿透电极114暴露。
参考图2G，再布线150形成在第一半导体芯片110的暴露的第一表面A以及邻接的成型部分130上以分别连接到暴露的接合衬垫112。再布线150通过例如电镀或无电镀形成。然后，在第一半导体芯片110的第一表面A以及成型部分130上形成绝缘层160以覆盖再布线150后，通过蚀刻绝缘层160，暴露部分再布线150。此后，诸如焊料球的外部连接端子170被结合到再布线150的暴露部分。
参考图2H，已通过先前的处理步骤且被结合到外部连接端子170所生成的结构被沿线I-I’切断。由于这样的事实，在条级(strip level)制造的多个堆叠的封装体被彼此分离成单元级(unit level)，且通过这样，完成了根据本发明的实施例的堆叠封装100的制造。
在根据本发明的实施例的上述方法中，具有尺寸大于第一半导体芯片的第二半导体芯片以这样的状态堆叠在第一半导体芯片上：通过采用重新构造晶片的制造技术，第一半导体芯片的侧表面被成型部分包围，由此，可容易且稳定地进行第二半导体芯片的堆叠工艺。
因此，在本发明中，由于当堆叠第二半导体芯片时可确保结构稳定性，所以可增加制造产量且并可改善产品的可靠性。
图3示出根据本发明的另一个实施例的堆叠封装的截面视图。图3所示的堆叠封装可与根据本发明以上描述的实施例的堆叠封装基本相同，除了基板和在基板与第一半导体芯片之间的电连接结构之外。因此，这里将省略相同部件的描述，且相同的技术术语和相同的附图标记将被用以指示相同或相似的部件。
参考图3，根据本发明实施例的堆叠封装300包括设置在第一半导体芯片110之下的基板350和电连接第一半导体芯片110与基板350的连接构件360。
在图3所示的实施例中，基板350具有面对第一半导体芯片110的第一表面A的第三表面C以及与第三表面相反的第四表面D，在第三表面C上设置有电连接到第一半导体芯片110的接合衬垫112的第一连接衬垫352，在第四表面D上设置有第二连接衬垫354。基板350例如包含印刷电路板。
连接构件360电连接彼此面对的第一半导体芯片110的接合衬垫112与第一基板350的第一连接衬垫352，且可包含例如焊料凸起或螺柱凸起。
根据本发明实施例的堆叠封装300进一步包括底部填充物380，形成在第一半导体芯片110与基板350之间以及邻接的成型部分130与基板350之间界定的间隔中。底部填充物380可理解为形成为通过连接构件360改善或维持第一半导体芯片110与基板350之间的电的或物理的耦合力。
在根据本发明的实施例的堆叠封装300中，形成密封构件140以覆盖包括基板350的第三表面C以及成型部分130和一个或更多个堆叠的第二半导体芯片120。诸如焊料球的外部连接端子170例如被结合到设置在基板350的第四表面D上的第二连接衬垫354。
尽管未示出，根据本发明实施例的堆叠封装300可进一步包括形成在第一半导体芯片110和邻接的成型部分130与最下的第二半导体芯片120a之间的底部填充物。底部填充物也可形成在堆叠的第二半导体芯片120之间。
而且，尽管未示出，根据本发明的实施例的堆叠封装300可进一步包含第三半导体芯片，其设置在最上的第二半导体芯片120b上。与前述实施例类似，第三半导体芯片可被理解为形成为其中具有电路部分且没有分离的穿透电极。第三半导体芯片具有接合衬垫，其设置在第三半导体芯片的面对最上的第二半导体芯片120b的表面上，并且电连接到最上的第二半导体芯片120b的第二穿透电极124。
图4示出根据本发明另一个实施例的堆叠封装的截面视图。图4所示的根据本发明的实施例的堆叠封装与图1中所示的堆叠封装基本相同，除了基板和在基板与第一半导体芯片之间的电连接结构之外。因此，这里将省略对于相同部件的描述，相同的技术术语和相同的附图标记将被用以指示相同或相似的部件。
参考图4，根据本发明的实施例的堆叠封装400包括基板450，其具有窗口W和电连接第一半导体芯片110与基板450的连接构件460。
在图4所示的实施例中，基板450的窗口W是基板450中的开口且被定义为暴露第一半导体芯片110的包括接合衬垫112和第一穿透电极114的第一表面A。基板450具有面对第一半导体芯片110的第一表面A的第三表面C和与第三表面C相反的第四表面D。第一连接衬垫452设置在第四表面D上以电连接到第一半导体芯片110的接合衬垫112。第二连接衬垫454设置在第一连接衬垫452以外的第四表面D上。优选地，第一连接衬垫452设置在基板450邻近窗口W的第四表面D上，且多个第二连接衬垫454设置在基板450在第一连接衬垫452以外的第四表面D上，以与窗口W分离。具有窗口W的基板450例如包含印刷电路板。
在实施例中，为了电连接第一半导体芯片110的接合衬垫112与基板的第一连接衬垫452，连接构件460穿过基板450的窗口W。连接构件460例如可包括金属线。
根据本发明的实施例的堆叠封装400进一步包括粘附构件480，其被插入成型部分130与基板450之间。
在根据本发明的实施例的堆叠封装400中，形成密封构件140以覆盖基板450的第三表面C以及成型部分130和一个或更多个堆叠的第二半导体芯片120。密封构件填充包含连接构件460的基板450的窗口W。诸如焊料球的外部连接端子170例如被结合到设置在基板350的第四表面D上的第二连接衬垫454。
类似地，尽管未示出，根据本发明的实施例的堆叠封装400可进一步包括底部填充物，其形成在第一半导体芯片110和邻接的成型部分130与最下的第二半导体芯片120a之间。底部填充物也可形成在堆叠的第二半导体芯片120之间。
而且，尽管未示出，根据本发明的实施例的堆叠封装400可进一步包括设置在最上的第二半导体芯片120b上的第三半导体芯片。第三半导体芯片可被理解为形成为其中具有电路部分且没有分离的穿透电极。第三半导体芯片具有接合衬垫，其设置在第三半导体芯片的面对最上的第二半导体芯片120b的表面上，并且电连接到最上的第二半导体芯片120b的第二穿透电极124。
图5示出根据本发明另一个实施例的堆叠封装的截面视图。根据图5所示的实施例的堆叠封装与图1所示的堆叠封装基本相同，除了虚设芯片(dummy chip)和电连接结构之外。因此，这里将省略对于相同部件的描述，且相同的技术术语和相同的附图标记将被用以指示相同或相似的部件。
参考图5，根据本发明的实施例的堆叠封装500包括虚设芯片550，其设置在最下的第二半导体芯片120a下面。如图5所示，虚设芯片550与第一半导体芯片110分离。
在实施例中，虚设芯片550中不包括电路部分，但是形成有多个穿过虚设芯片的第四穿透电极552。
一个或更多个第二半导体芯片120不仅具有电连接到第一半导体芯片110的第一穿透电极114的第二穿透电极124，而且具有第三穿透电极126，第三穿透电极126形成为穿过第二半导体芯片120的部分且与第二穿透电极124分离。在实施例中，第三穿透电极形成为穿过第二半导体芯片120的位于虚设芯片550上的边缘部分。各个第二半导体芯片120的第三穿透电极126彼此电连接。形成为穿过最下的第二半导体芯片120a的第三穿透电极126电连接到穿过虚设芯片550形成的第四穿透电极552。此外，穿过虚设芯片550形成的第四穿透电极552电连接到再布线150。
在实施例中，形成成型部分130以围绕第一半导体芯片110和虚设芯片550的侧表面。成型部分130也可形成为使其仅邻接第一半导体芯片的一个以上但不是所有的侧表面。在这样的情况下，成型部分130可形成为邻接虚设芯片550的侧表面，该虚设芯片550的侧表面对应于第一半导体芯片的形成有成型部分130的侧表面。
在根据本发明的实施例的堆叠封装500中，密封构件140形成以覆盖成型部分130以及一个或更多个堆叠的第二半导体芯片120。再布线150形成在第一半导体芯片110的第一表面A上，且电连接到接合衬垫112。绝缘层160形成在第一半导体芯片110的第一表面A上以及再布线150上，并包含暴露部分再布线150的开口。外部连接端子170被结合到再布线150的暴露部分。
尽管未示出，根据本发明的实施例的堆叠封装500可进一步包括底部填充物，其形成在第一半导体芯片110、虚设芯片550、成型部分130与最下的第二半导体芯片120a之间。底部填充物也可形成在堆叠的第二半导体芯片120之间。此外，第三半导体芯片可设置在最上的第二半导体芯片120b上。第三半导体芯片可被理解为具有与前述实施例中相同的构造。
图6示出根据本发明另一个实施例的堆叠封装的截面视图。图6所示的堆叠封装与图1所示堆叠封装基本相同，除了散热器(heat spreader)和密封结构之外。因此，这里将省略对于相同的部件的描述，且相同的技术术语和相同的附图标记将被用以指示相同或相似的部件。
参考图6，根据本发明实施例的堆叠封装600包括散热器680，其一部分被设置在第一半导体芯片110、成型部分130与最下的第二半导体芯片120a之间，且其一部分沿着一个或更多个堆叠的第二半导体芯片120的侧表面向上延伸。
在实施例中，散热器680用以将第一半导体芯片110以及一个或更多个第二半导体芯片120中产生的热快速消散到外界。优选地，散热器680由具有优良的散热特性的材料制成，例如金属。
在实施例中，散热器680具有设置在第一半导体芯片110、成型部分130与最下的第二半导体芯片120a之间的水平部分680a，以及从水平部分680a的端部沿一个或更多个第二半导体芯片120的侧表面延伸的垂直部分680b。例如，垂直部分680b形成为梳状形状，使得可实现优良的散热特性。
如图6所示，垂直部分680b不与堆叠的第二半导体芯片120的侧表面接触且与其分离。然而，垂直部分680b设置为接触堆叠的第二半导体芯片120的侧表面是可以的。在垂直部分680b设置为与堆叠的第二半导体芯片120的侧表面分离的情况下，垂直部分680b与堆叠的第二半导体芯片120之间的间隔可被底部填充物填充。
在实施例中，堆叠的第二半导体芯片120之间的间隔可被底部填充物690填充。底部填充物用以维持一个或更多个堆叠的第二半导体芯片120的第二穿透电极124之间的耦合力，并且也用以保护堆叠的第二半导体芯片120的有源表面(有源表面为其上形成有接合衬垫的表面)不受外部影响。
在根据本发明的实施例的堆叠封装600中，再布线150形成在第一半导体芯片110的第一表面A上，且电连接到接合衬垫112。绝缘层160形成在第一半导体芯片110的第一表面A上以及再布线150上，并包括暴露部分再布线150的开口。外部连接端子170被结合到再布线150的暴露部分。
尽管未示出，根据本发明的实施例的堆叠封装600可进一步包括设置在最上的第二半导体芯片120b上的第三半导体芯片。第三半导体芯片可被理解为具有与前述实施例中相同的结构。类似地，应了解底部填充物690可形成在最上的第二半导体芯片120b与第三半导体芯片之间。
尽管为了说明的目的描述了本发明的具体实施例，但是本领域技术人员应理解，可以进行各种变更、添加和替代而不偏离权利要求公开的本发明的范围和精神。
交叉引用
本申请要求2009年12月31日提交的韩国专利申请第10-2009-0135201号的优先权，其全部内容通过引用结合于此。

Claims (20)

1.一种堆叠封装，包括：
第一半导体芯片，具有第一尺寸并具有第一表面和与所述第一表面相反的第二表面，所述第一半导体芯片包括设置在所述第一表面上的接合衬垫以及穿透所述第一表面和所述第二表面的一个或更多个第一穿透电极；
一个或更多个第二半导体芯片，具有大于所述第一尺寸的第二尺寸，堆叠在所述第一半导体芯片的所述第二表面上，所述一个或更多个第二半导体芯片包括一个或更多个第二穿透电极，所述一个或更多个第二穿透电极彼此电连接且电连接到所述一个或更多个第一穿透电极；以及
成型部分，邻接所述第一半导体芯片的一个或更多个侧表面，使得包括所述第一尺寸和所述成型部分的尺寸的总尺寸等于或大于所述第二尺寸。
2.根据权利要求1所述的堆叠封装，进一步包括：
第三半导体芯片，设置在所述一个或更多个堆叠的第二半导体芯片之中最上的第二半导体芯片上，所述第三半导体芯片电连接到所述最上的第二半导体芯片的所述第二穿透电极。
3.根据权利要求1所述的堆叠封装，进一步包括：
密封构件，形成在所述成型部分上以及所述一个或更多个堆叠的第二半导体芯片上；
再布线，形成在所述第一半导体芯片的所述第一表面上，且电连接到所述接合衬垫；
绝缘层，形成在所述第一半导体芯片的所述第一表面上以及所述再布线上，所述绝缘层具有暴露部分所述再布线的开口；以及
外部连接端子，结合到所述再布线的暴露部分。
4.根据权利要求3所述的堆叠封装，进一步包括：
底部填充物，形成在所述第一半导体芯片和所述一个或更多个堆叠的第二半导体芯片之中最下的半导体芯片之间，以及在所述堆叠的第二半导体芯片之间。
5.根据权利要求1所述的堆叠封装，其中所述第一半导体芯片具有四边形形状，且所述成型部分形成为覆盖所述第一半导体芯片的两个相对的侧表面或围绕所述第一半导体芯片的所有的四个侧表面。
6.根据权利要求1所述的堆叠封装，进一步包括：
基板，具有面对所述第一半导体芯片的所述第一表面的第三表面以及与所述第三表面相反的第四表面，所述基板包括设置在所述第三表面上且电连接到所述第一半导体芯片的所述接合衬垫的连接衬垫，以及设置在所述第四表面上的第二连接衬垫；
连接构件，电连接所述第一半导体芯片的所述接合衬垫和所述基板的所述第一连接衬垫；
密封构件，形成在所述基板的所述第三表面上以及所述第二半导体芯片和所述成型部分上；以及
外部连接端子，结合到所述基板的所述第二连接衬垫。
7.根据权利要求6所述的堆叠封装，进一步包括：
底部填充物，形成在所述第一半导体芯片与所述基板之间以及所述成型部分与所述基板之间的间隔中。
8.根据权利要求1所述的堆叠封装，进一步包括：
基板，具有窗口、面对所述第一半导体芯片的所述第一表面的第三表面、以及与所述第三表面相反的第四表面，所述基板包括设置在所述第四表面上且电连接到所述第一半导体芯片的所述接合衬垫的第一连接衬垫，以及设置在第一连接衬垫以外的所述第四表面上的第二连接衬垫；
连接构件，穿过所述窗口并电连接所述第一半导体芯片的所述接合衬垫和所述基板的所述第一连接衬垫；
密封构件，形成为密封所述基板的所述第三表面和所述第二半导体芯片和所述成型部分、以及包括所述连接构件的所述基板的窗口；以及
外部连接端子，结合到所述基板的所述第二连接衬垫。
9.根据权利要求8所述的堆叠封装，进一步包括：
插入所述成型部分和所述基板之间的粘附构件。
10.一种堆叠封装，包括：
第一半导体芯片，具有第一尺寸并具有第一表面和与所述第一表面相反的第二表面，所述第一半导体芯片包括设置在所述第一表面上的接合衬垫以及穿透所述第一表面和所述第二表面的一个或更多个第一穿透电极；
一个或更多个第二半导体芯片，具有大于所述第一尺寸的第二尺寸，且堆叠在所述第一半导体芯片的所述第二表面上，所述一个或更多个第二半导体芯片包括一个或更多个第二穿透电极以及一个或更多个第三穿透电极，所述一个或更多个第二穿透电极彼此电连接且电连接到所述一个或更多个第一穿透电极；
虚设芯片，设置在所述一个或更多个堆叠的第二半导体芯片之中最下的第二半导体下面，所述虚设芯片与所述第一半导体芯片分离，并且包括电连接到所述第三穿透电极的第四穿透电极；以及
成型部分，邻接所述第一半导体芯片的一个或更多个侧表面以及所述虚设芯片的一个或更多个侧表面，从而获得等于或大于所述第二尺寸的尺寸。
11.根据权利要求10所述的堆叠封装，其中所述第三穿透电极形成为穿过所述第二半导体芯片的与所述第二穿透电极分离的部分。
12.根据权利要求10所述的堆叠封装，其中所述虚设芯片在其中不包括电路部分而仅形成所述第四穿透电极。
13.根据权利要求10所述的堆叠封装，其中所述第一半导体芯片具有四边形形状，且所述成型部分形成为覆盖所述第一半导体芯片的两个相对的侧表面或围绕所述第一半导体芯片的所有四个侧表面，且围绕所述虚设芯片。
14.根据权利要求10所述的堆叠封装，进一步包括：
第三半导体芯片，设置在所述一个或更多个堆叠的第二半导体芯片之中最上的第二半导体芯片上，所述第三半导体芯片电连接到所述最上的第二半导体芯片的所述第二穿透电极。
15.根据权利要求10所述的堆叠封装，进一步包括：
密封构件，形成在所述成型部分上和所述一个或更多个堆叠的第二半导体芯片上；
再布线，形成在所述第一半导体芯片的所述第一表面上以电连接到所述接合衬垫和所述第四穿透电极；
绝缘层，形成在所述第一半导体芯片的所述第一表面上以及所述再布线上，所述绝缘层具有暴露部分所述再布线的开口；以及
外部连接端子，结合到所述再布线的暴露部分。
16.根据权利要求15所述的堆叠封装，进一步包括：
底部填充物，形成在所述第一半导体芯片与所述一个或更多个堆叠的第二半导体芯片之中最下的半导体芯片之间，以及在所述虚设芯片与所述最下的半导体芯片之间，以及形成在所述堆叠的第二半导体芯片之间。
17.一种堆叠封装，包括：
第一半导体芯片，具有第一尺寸，并具有第一表面和与所述第一表面相反的第二表面，所述第一半导体芯片包括设置在所述第一表面上的接合衬垫，以及穿透所述第一表面和所述第二表面的一个或更多个第一穿透电极；
一个或更多个第二半导体芯片，具有大于所述第一尺寸的第二尺寸，且堆叠在所述第一半导体芯片的所述第二表面上，所述一个或更多个第二半导体芯片包括一个或更多个第二穿透电极，所述一个或更多个第二穿透电极彼此电连接并电连接到所述一个或更多个第一穿透电极；
成型部分，邻接所述第一半导体芯片的一个或更多个侧表面，使得包括所述第一尺寸和所述成型部分的尺寸的总尺寸等于或大于所述第二尺寸；
散热器，包括设置在所述第一半导体芯片与所述一个或更多个堆叠的第二半导体芯片之中最下的第二半导体芯片之间以及在所述成型部分与所述一个或更多个堆叠的第二半导体芯片之中最下的第二半导体芯片之间的部分、以及沿着所述一个或更多个堆叠的第二半导体芯片的侧表面延伸的部分；
底部填充物，形成在所述堆叠的第二半导体芯片之间的间隔中；
再布线，形成在所述第一半导体芯片的所述第一表面上，且电连接到所述接合衬垫；
绝缘层，形成在所述第一半导体芯片的所述第一表面上以及所述再布线上，所述绝缘层具有暴露部分所述再布线的开口；以及
外部连接端子，结合到所述再布线的暴露部分。
18.根据权利要求17所述的堆叠封装，其中形成所述散热器使得所述散热器的沿着所述一个或更多个堆叠的第二半导体芯片的侧表面延伸的所述部分接触所述一个或更多个堆叠的第二半导体芯片的所述侧表面。
19.根据权利要求17所述的堆叠封装，其中形成所述散热器使得所述散热器的沿着所述一个或更多个堆叠的第二半导体芯片的侧表面延伸的所述部分与所述一个或更多个堆叠的第二半导体芯片的所述侧表面分离。
20.根据权利要求19所述的堆叠封装，进一步包括：
底部填充物，形成在所述一个或更多个堆叠的第二半导体芯片的所述侧表面与所述散热器之间的间隔中。
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