CN103165586A - 半导体堆叠封装体及其制造方法 - Google Patents

半导体堆叠封装体及其制造方法 Download PDF

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Publication number
CN103165586A
CN103165586A CN2012105441938A CN201210544193A CN103165586A CN 103165586 A CN103165586 A CN 103165586A CN 2012105441938 A CN2012105441938 A CN 2012105441938A CN 201210544193 A CN201210544193 A CN 201210544193A CN 103165586 A CN103165586 A CN 103165586A
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semiconductor chip
chip
stacking
semiconductor
penetrating electrode
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CN2012105441938A
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吴卓根
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SK Hynix Inc
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Hynix Semiconductor Inc
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Publication of CN103165586A publication Critical patent/CN103165586A/zh
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Abstract

本发明提供一种半导体芯片堆叠及其制造方法，还提供包括半导体芯片堆叠的电子系统及相关方法。该半导体芯片堆叠包括：半导体芯片堆叠包括：垂直堆叠在插入体的顶表面上的多个第一半导体芯片；第二半导体芯片，堆叠在插入体的与半导体芯片堆叠相反的底表面上；以及外部电极，附着至第二半导体芯片的与插入体相反的顶表面。

Description

半导体堆叠封装体及其制造方法
技术领域
本公开的示范实施例涉及半导体封装体，更具体涉及半导体堆叠封装体及其制造方法。
背景技术
随着对于更小及性能更高的电子产品的需求，已持续开发了用以制造大容量半导体模块和/或大容量半导体封装体的各种技术。响应于上述需求，已提出垂直堆叠多个半导体芯片（例如，存储器芯片和/或逻辑芯片）的技术。
发明内容
示范实施例涉及半导体堆叠封装体及其制造方法。
此外，实施例涉及包括半导体堆叠封装体的电子系统。
根据一些实施例，一种半导体堆叠封装体包括：插入体；半导体芯片堆叠，包括垂直堆叠在插入体的顶表面上的多个第一半导体芯片；第二半导体芯片，堆叠在插入体的与半导体芯片堆叠相反的底表面上；以及外部电极，附着至第二半导体芯片的与插入体相反的顶表面。
根据另一实施例，一种半导体堆叠封装体包括：第一贯穿电极插入其中的插入体；半导体芯片堆叠，包括垂直堆叠在插入体的顶表面上的多个第一半导体芯片；第二贯穿电极，穿透半导体芯片堆叠以电连接至第一贯穿电极；第二半导体芯片，在插入体的底表面上；以及第三贯穿电极，穿透第二半导体芯片以电连接至第一贯穿电极。
半导体堆叠封装体还可包括覆盖半导体芯片堆叠的保护层。
多个第一半导体芯片的每一个可包括存储器芯片。
第二半导体芯片可包括逻辑芯片。
半导体堆叠封装体还可包括覆盖第二半导体芯片的保护层。
根据又一实施例，一种制造半导体堆叠封装体的方法包括：在插入体的顶表面上垂直堆叠多个第一半导体芯片，以形成半导体芯片堆叠；以及在插入体的与半导体芯片堆叠相反的底表面上堆叠第二半导体芯片。
该方法还可包括形成穿透插入体的本体的第一贯穿电极。第一贯穿电极的一端可暴露于插入体的顶表面，以构成第一接触部分，并且第一贯穿电极的另一端可以暴露于插入体的底表面，以构成第二接触部分。
附图说明
从结合附图的以下详细描述可更清楚地理解以上和其他方面、特征和其他优点，其中
图1是示出半导体堆叠封装体的示例的截面图；
图2至12是示出根据一些示范实施例的制造半导体堆叠封装体的方法及由此制造的半导体堆叠封装体的截面图；
图13是示出对比示例的半导体堆叠封装体的截面图，以描述根据一些实施例的半导体堆叠封装体及其制造方法的优点；
图14是示出根据本发明构思的变型实施例的半导体堆叠封装体并且示出其制造方法的截面图；以及
图15是示出包括根据一些实施例的半导体堆叠封装体的电子系统的示例的示意方块图。
具体实施方式
下面参考附图来描述示范实施例。在没有偏离本公开的精神和教导的情况下，多种不同形式及实施例是可能的，因此，本公开不应该被理解为局限于本文所述的实施例。相反，提供这些实施例以使得本公开透彻以及向本领域技术人员传达本公开的范围。在图中，为了清楚起见，可能夸大层及区域的尺寸和相对尺寸。在通篇说明书中，相同的参考标号或相同的参考指示符表示相同的元件。
本文参考为实施例（及中间结构）的示意图示的截面图示来描述示范实施例。这样，例如由于制造技术和/或公差所造成的图示的形状的变化是可预期的。因此，公开的实施例不可理解为对本文示出的区域的特定形状的限制，而是要理解为包含例如因制造所造成的形状的偏差。
本文所使用的术语仅为了描述特定实施例而不旨在成为实施例的限制。如本文所使用的，单数形式“一”、“所述”及“该”旨在包括复数形式，除非上下文有明确另外指示。应进一步理解的是，当本文使用术语“具有”、“包括”、“包含”时，说明存在所述的特征、步骤、操作、元件和/或构件，但是不排除存在或附加一个或多个其它特征、步骤、操作、元件、构件和/或其组。
应理解，当元件被描述为“耦接至”、“连接至”或“相应于”另一元件或“在另一元件上”时，它可直接“耦接”、“连接”或“响应于”该另一元件或“直接在该另一元件上”，或者也可存在插入元件。相反，当提及元件被描述为“直接耦接至”、“直接连接至”、“直接响应于”另一元件或“直接在另一元件上”时，则不存在插入元件。如本文所使用的，术语“和/或”包括相关列出项目中的一者或多者的任何或所有组合。
应理解，虽然本文可使用术语第一、第二等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语只是用以使得元件彼此区分。因此，在不脱离本实施例的教导的情况下，第一元件可被称为第二元件。
除非另有限定，本文所使用的所有术语（包括技术及科学术语）具有相同于这些实施例所属领域的普通技术人员所通常了解的意思。应进一步理解的是，术语（例如在一般使用字典中所界定的术语）应该理解为具有与它们在相关技术的上下文中的含义一致的含义而不理解为理想化的或过度正式的理解，除非本文明确界定如此。
图1是示出半导体堆叠封装体的示例的截面图。
参考图1，可以通过在封装基板100（例如，印刷电路板（PCB））上垂直堆叠多个半导体芯片而实现半导体堆叠封装体。多个半导体芯片可以包括顺次堆叠的第一半导体芯片111、第二半导体芯片113及第三半导体芯片115。可以在堆叠的半导体芯片111、113及115之间以及在第一半导体芯片111与封装基板100之间设置底填材料120（或粘接剂）。多个堆叠的半导体芯片111、113及115可以构成半导体芯片堆叠110。多个堆叠的半导体芯片111、113及115的内部电路可以经由贯通电极130（例如，经由穿透堆叠的半导体芯片111、113及115的贯通硅通路（TSVs））彼此电连接。在封装基板100上安装半导体芯片堆叠110之后，可以形成诸如环氧树脂模制化合物（EMC）的模制构件140，以覆盖半导体芯片堆叠110。随后，可以在封装基板100的与半导体芯片堆叠110相反的底表面上形成外部电极150（例如，焊料球），由此实现半导体堆叠封装体。
根据图1示出的半导体堆叠封装体，半导体芯片堆叠110安装在封装基板100上。因此，在半导体芯片堆叠110与封装基板100之间再插入附加的半导体芯片可能存在限制。在半导体芯片堆叠110与封装基板100之间设置附加的半导体芯片的情况下，半导体芯片堆叠110应在附加的半导体芯片安装到封装基板100上之后再堆叠在附加的半导体芯片上。然而，在此情况下，可能需要复杂的工艺并且可能需要准确的控制工艺。
图2至12是示出根据一些实施例的制造半导体堆叠封装体的方法及由此制造的半导体堆叠封装体的截面图。为了说明的容易及方便，将结合包括三个半导体芯片的半导体芯片堆叠的示例来描述本实施例。然而，构成半导体芯片堆叠的半导体芯片的数目并不局限于三个。例如，构成半导体芯片堆叠的半导体芯片的数目可以是四个、八个或更多。
参考图2，在封装工艺期间插入体200可以用作一个或多个半导体芯片堆叠的处理构件（handling member）。在本实施例中，插入体200将描述为其上安装有半导体芯片堆叠的非柔性基板。然而，在一些实施例中，插入体200可以是膜状基板、带状基板或片状基板。
插入体200可以是半导体基板（例如，硅基板或锗基板）或绝缘体基板（例如，碳聚合物基板、玻璃纤维基板或树脂基板）。在一些另外的实施例中，插入体200可以是金属基板。在一些另外的实施例中，插入体200可以包括绝缘体基板及设置在绝缘体基板中或上的导电电路内连。这些导电电路内连可以由铁、铜、镍或金形成。当插入体200是半导体基板时，可以在半导体基板的表面上涂布诸如氧化物材料的绝缘层，以使半导体基板与其它元件电绝缘。当插入体200是金属基板时，也可以在金属基板的表面上涂布绝缘层，以使金属基板与其它元件电绝缘。
当插入体200及堆叠在插入体200上的半导体芯片包含相同材料（例如，硅材料）时，插入体200的热膨胀系数（CTE）可能等于或相似于在插入体200上的半导体芯片的热膨胀系数。因此，插入体200与插入体200上的半导体芯片之间产生的机械应力和/或物理应力可被减轻或防止。于是，即使插入体200与堆叠在插入体200上的半导体芯片的温度不同，裂缝（cracks）可能也不会形成于插入体200和/或半导体芯片中。此外，硅材料展现出优良的热传导性。因此，在一些实施例中，插入体200可包括硅材料。
插入体200可被蚀刻以形成从插入体200的顶表面203延伸至插入体200的主体区域（bulk region）中的沟槽201。沟槽201可以使用湿蚀刻工艺、干蚀刻工艺、激光钻孔工艺或微钻孔工艺来形成。沟槽201的深度可以根据形成半导体堆叠封装体之后所剩余的插入体201的最终厚度而变化。在一些实施例中，沟槽201可形成为到达插入体200的底表面205。也就是，沟槽201可以对应于完全穿透插入体200的通孔。然而，虽然相对厚的插入体200有助于在封装工艺期间处理安装在插入体200上的半导体芯片，但是相对薄的插入体200可有利于半导体堆叠封装体。因此，在一些实施例中，如图2所示，沟槽201的深度可以小于插入体200的初始厚度。
导电层可以填充沟槽201，由此在各个沟槽201中形成第一贯穿电极210。第一贯穿电极210（例如，贯穿硅通路（TSV））可以作为电接触结构。
填充沟槽201的导电层可包括金属材料、掺杂多晶硅材料或碳纳米管（CNT）材料。金属材料可以包括铝（Al）、铁（Fe）、铜（Cu）、镍（Ni）、金（Au）或其金属合金。此外，可以在第一贯穿电极210与插入体200之间设置诸如氧化硅材料的绝缘层（未示出）。绝缘层可形成以防止第一贯穿电极210电连接至插入体200。如果插入体200是绝缘体基板，则可以省略在第一贯穿电极210与插入体200之间形成绝缘层。
第一贯穿电极210的每一个的顶部可以对应于第一接触部分211并且可以相邻于插入体200的顶表面203。也就是，第一贯穿电极210的第一接触部分211可暴露于插入体200的顶表面203。在一些实施例中，第一贯穿电极210的第一接触部分211可以从插入体200的顶表面203向上突出。使第一接触部分211从顶表面203突出，可以改善第一接触部分211与其它元件之间的电连接及物理连接的可靠性。
第一贯穿电极210的下部分可以对应于第二接触部分213并且可以在后续工艺中电连接至外部装置。在本实施例中，如图2所示，可以在沟槽201的下区域中埋置第一贯穿电极210的第二接触部分213。然而，如果沟槽201形成为具有穿透插入体200的贯穿孔形状，则第二接触部分213可暴露于插入体200的底表面205。考虑到要电连接至后续工艺中形成的多个半导体芯片堆叠，第一贯穿电极210可形成为包括多个组。
参考图3，可以制备多个第一半导体芯片300。在后续工艺中，第一半导体芯片300可堆叠在参考图2描述的插入体200上。为了图示的简单化，在图3中仅示出多个第一半导体芯片300之一。
第一半导体芯片300可以是易失性存储器芯片，例如，动态随机存取存储器（DRAM）芯片。然而，第一半导体芯片300并不限于易失性存储器芯片。例如，第一半导体芯片300可以是非易失性存储器芯片（例如，闪存芯片）、包括各种逻辑电路的逻辑芯片或用于网络通信的通信芯片。将结合DRAM芯片作为第一半导体芯片300的示例来描述本实施例。
第二贯穿电极310可形成为穿透第一半导体芯片300的每一个。第二贯穿电极310可用作将第一半导体芯片300电连接至其它芯片或其它基板的电接触结构。有源区域（未示出）可形成在第一半导体芯片300的顶表面中并且集成电路可形成在有源区域中和有源区域上。第二贯穿电极310可电连接至第一半导体芯片300的集成电路。第二贯穿电极310可以通过重分布内连（redistributed interconnections）（未示出）电连接至第一半导体芯片300的集成电路。第二贯穿电极310可以形成于穿透穿透第一半导体芯片300的各个第一通孔301中。也就是，可以通过以导电材料填充第一通孔301来形成第二贯穿电极310。这些第二贯穿电极310可以使用形成贯穿硅通路（TSV）的技术来制造。第二贯穿电极310可由导电材料（例如，金属材料、掺杂多晶硅材料或碳纳米管（CNT）材料）形成。金属材料可以包括铝（Al）、铁（Fe）、铜（Cu）、镍（Ni）、金（Au）或其金属合金。
第二贯穿电极310的每一个在其两端上可分别包括第三接触部分312及第四接触部分313。第三接触部分312及第四接触部分313可电连接至其它元件。第三接触部分312及第四接触部分313可暴露于第一半导体芯片300的顶表面及底表面。在一些实施例中，第三接触部分312及第四接触部分313可从第一半导体芯片300的顶表面及底表面突出。使第三接触部分312及第四接触部分313从顶表面及底表面突出，可以改善第三接触部分312及第四接触部分313与其它元件之间的电连接及物理连接的可靠性。此外，可以以金桩凸块（GSB）、铜柱凸块（CPB）或焊料凸块覆盖第三接触部分312及第四接触部分313的每一个。
参考图4，可以在图2所示的插入体200的顶表面203上堆叠参考图3所述的第一半导体芯片300当中的一对第一芯片410。可在第一贯穿电极210当中的第一组贯穿电极210上堆叠此对第一芯片410中之一，以及可以在第一贯穿电极210当中的第二组贯穿电极210上堆叠此对第一芯片410当中的另一个。虽然下面的实施例是结合其中在插入体200上垂直堆叠相同于第一半导体芯片300的芯片的示例来描述，但是本发明构思亦可以应用于其中在插入体200上垂直堆叠不同功能和/或尺寸的芯片的其它示例。
此外，即使以下使用术语“第一半导体芯片300的第一芯片410”、“第一半导体芯片300的第二芯片450”、“第一半导体芯片300的第三芯片470”等以使第一芯片410、第二芯片450及第三芯片470彼此区分，但是第一芯片410、第二芯片450及第三芯片470可以具有相同于参考图3所述的第一半导体芯片300的构型。即使以下使用术语“第二贯穿电极的第一部分411”、“第二贯穿电极的第二部分451”、“第二贯穿电极的第三部分471”等来区分第一部分411、第二部分451及第三部分471，但是第一部分411、第二部分451及第三部分471可具有相同于参考图3所述的第二贯穿电极310的构型。也就是，第一部分411、第二部分451及第三部分471的每一个可包括第三接触部分412及第四接触部分413，第三接触部分412对应于图3所示的第二贯穿电极310的第三接触部分312，第四接触部分413对应于图3所示的第二贯穿电极310的第四接触部分313。
再次参考图4，可以在插入体200的顶表面203上堆叠一对第一芯片410，使得穿透第一芯片410的第二贯穿电极的第一部分411电连接至设置在插入体200中的各个第一贯穿电极210。当从平面图看时，第一芯片410可以配置成彼此间隔开。第一部分411的第三接触部分412可暴露于第一芯片410的顶表面，以及第一部分411的第四接触部分413可电连接至第一贯穿电极210的各个第一接触部分211。在插入体200与第一芯片410之间可设置第一中间绝缘层430。第一中间绝缘层430可以用作粘合剂并且也可使第一芯片410与插入体200电绝缘。
第一中间绝缘层430可包括底填层（例如，树脂层）、非导电膜（NCF）、非导电膏（NCP）、各向异性导电膜（ACF）或各向异性导电膏（ACP）。
参考图5，可以在各个第一芯片410上堆叠第二芯片450，并且可以在各个第二芯片450上堆叠第三芯片470。也可以在第一芯片410与第二芯片450之间及在第二芯片450与第三芯片470之间设置另外的第一中间绝缘层430。当在第一芯片410上堆叠第二芯片450及第三芯片470时，穿透第二芯片450的第二部分451可与各个第一部分411及穿透第三芯片470的第三部分471垂直对准，并且第三部分471也可与各个第二部分451垂直对准。于是，第二部分451可与各个第一部分411的电连接，以及第三部分471可以与各个第二部分451电连接。
顺次及垂直堆叠的一组第一芯片410、第二芯片450及第三芯片470可构成半导体芯片堆叠400。因此，在本实施例中，如图5所示，可以在插入体200上设置一对半导体芯片堆叠400，使得该对半导体芯片堆叠400彼此横向地间隔开。虽然描述的实施例显示了在插入体200上的一对半导体芯片堆叠400，但是在另外的实施例中，可以在插入体200上设置一对以上的半导体芯片堆叠400。另外，一组垂直堆叠的第一部分411、第二部分451及第三部分471可构成完全穿透半导体芯片堆叠400的单个第二贯穿电极401。在每个第二贯穿电极401中，诸如凸块的连接构件（未示出）可设置在第一部分411与第二部分451之间及第二部分451与第三部分471之间。类似地，另一连接构件也可设置在第一贯穿电极210与第一部分411之间。连接构件可以改善第一部分411与第二部分451之间、第二部分451与第三部分471之间以及第一贯穿电极210与第一部分411之间的电连接的可靠性。在一些实施例中，当使用诸如各向异性导电膜（ACF）或各向异性导电膏（ACP）的各向异性导电层作为第一中间绝缘层430时，可以不需要诸如凸块的连接构件。
参考图6，第一保护层510可形成为覆盖半导体芯片堆叠400。第一保护层510可形成以保护半导体芯片堆叠400不受外部环境影响。第一保护层510可填充半导体芯片堆叠400之间的空间，由此覆盖半导体芯片堆叠400的所有侧壁。第一保护层510可以使用第一模制工艺（first molding process）由环氧树脂模制化合物（EMC）材料形成。在一些实施例中，第一保护层510可形成为包括热固性树脂材料、二氧化硅（silica）材料或非导电填充材料。在另外的实施例中，第一保护层510可形成为包括绝缘树脂材料、非导电膜（NCF）、非导电膏（NCP）、各向异性导电膜（ACF）或各向异性导电膏（ACP）。
在一些实施例中，第一保护层510可形成为离开半导体芯片堆叠400的暴露顶表面并且覆盖半导体芯片堆叠400的侧壁。甚至当执行后续工艺时，第一保护层510可以保护半导体芯片堆叠400。因此，第一保护层510也可形成为完全覆盖半导体芯片堆叠400的所有表面。
当以第一保护层510完全覆盖半导体芯片堆叠400时，插入体200、半导体芯片堆叠400及第一保护层510可用作具有半成品形状的芯片堆叠基板501。因此，可以在芯片堆叠基板501上安装至少一个附加的半导体芯片。
芯片堆叠基板501可比插入体200和/或每一半导体芯片堆叠400厚，这是因为除了插入体200及半导体芯片堆叠400之外，芯片堆叠基板501还包括第一保护层510。此外，由于第一保护层510的存在，芯片堆叠基板501可以具有相对高的强度。因此，即使使用芯片堆叠基板501来执行后续工艺，第一保护层510也可抑制或防止工艺缺陷（例如，芯片堆叠基板501的翘曲和/或在芯片堆叠基板501中的裂缝）的发生或产生。此外，如图6所示，可以以第一保护层510来覆盖半导体芯片堆叠400的所有表面，且插入体200的与半导体芯片堆叠400相反的底表面205可保持暴露。因此，可对插入体200的暴露底表面205附加地施加各种工艺而不会对半导体芯片堆叠400有任何损坏。例如，可在插入体200的暴露底表面205上堆叠附加的半导体芯片而不会对半导体芯片堆叠400有任何损坏。也就是，当执行附加工艺时，可改善工艺裕度（process margin）。
参考图7，可以使插入体200的底表面205（例如，参见图4的未凹陷的底表面的视图）凹陷，以移除插入体200的下部分。在使插入体200的底表面（也就是，下部分）凹陷之前，可以形成第一保护层510以覆盖半导体芯片堆叠400。结果，与第一接触部分211（见图2）相反的凹陷的底表面206可以暴露第一贯穿电极210的第二接触部分213。在移除插入体200的下部分之后，第一贯穿电极210的第二接触部分213可以从插入体200的凹陷的底表面206向下突出。即使因移除插入体200的下部分而减少了插入体200的厚度，芯片堆叠基板501仍然可以因第一保护层510的存在而具有相对高的强度。因此，当在插入体200的凹陷的底表面206上堆叠附加的半导体芯片时，第一半导体芯片410、450及470不会被损坏。在一些实施例中，底表面205和/或凹陷的底表面206没有被第一保护层510所覆盖。
在一些实施例中，可使用研磨工艺、化学机械抛光（CMP）工艺或回蚀刻工艺，使插入体200的底表面205凹陷。可使用干蚀刻工艺或湿蚀刻工艺来执行回蚀刻工艺。
参考图8，可在插入体200的与半导体芯片堆叠400相反的凹陷的底表面206上堆叠第二半导体芯片600，其中与半导体芯片堆叠400相反是指每一行第二半导体芯片600布置在每个半导体芯片堆叠400的下方（或上方，取决于观看位置）。当构成半导体芯片堆叠400的第一半导体芯片410、450及470为诸如DRAM芯片的存储器芯片时，第二半导体芯片600可以是控制存储器芯片的操作的控制芯片或逻辑芯片。在一些实施例中，第一半导体芯片410、450、470及第二半导体芯片600可以是相同类型但是彼此尺寸不同的芯片。
第二半导体芯片600的每一个可包括邻接其顶表面605的第五接触部分611及邻接其底表面的第六接触部分613，底表面与顶表面605相反。第五接触部分611可电连接至外部装置，且第六接触部分613可电连接至第一半导体芯片410、450及470。第五接触部分611及第六接触部分613可以具有连接垫形状。可替换地，第五接触部分611可以对应于穿透第二半导体芯片600的第三贯穿电极610的第一端，而第六接触部分613可对应于穿透第二半导体芯片600的第三贯穿电极610的第二端。图8示出其中第五接触部分611及第六接触部分613对应于穿透第二半导体芯片600的第三贯穿电极610的第一端及第二端的示例。然而，在一些实施例中，可以在第二半导体芯片600的顶表面和底表面上设置连接垫，并且连接垫可直接连接至第三贯穿电极610的第五接触部分611及第六接触部分613或可经由重分布内连（未示出）间接连接至第五接触部分611及第六接触部分613。
如上所述，第二半导体芯片600可堆叠在插入体200的凹陷的底表面206上。具体地，第二半导体芯片600可设置在插入体200的凹陷的底表面206上，并且通过对第二接触部分213及第六接触部分613施加热和压力，第六接触部分613可连接至第一贯穿电极210的第二接触部分213且与第一贯穿电极210的第二接触部分213结合。第二半导体芯片600可直接安装在包括插入体200的芯片堆叠基板501上。因此，可以使用相同或相似于晶片上芯片（chip on wafer，COW）接合工艺的技术，在芯片堆叠基板501上安装第二半导体芯片600。根据本实施例，即使在插入体200的凹陷的底表面206上安装第二半导体芯片600，第二半导体芯片600可也电连接至安装在插入体200的与凹陷的底表面206相反的顶表面上的半导体芯片堆叠400，其中第二半导体芯片600可通过穿透插入体200的第一贯穿电极210而与半导体芯片堆叠400电连接。
参考图9，可在插入体200的凹陷的底表面206上形成第二保护层530，以覆盖第二半导体芯片600。第二保护层530可使用第二模制工艺形成。第二模制工艺可以实质相同或相似于在形成第一保护层510中使用的第一模制工艺。当形成第二保护层530时，芯片堆叠基板501可用作支撑第二半导体芯片600的基板。在第二模制工艺期间，因为以第一保护层510覆盖半导体芯片堆叠400，因此不会损坏半导体芯片堆叠400。
如图9所示，第二保护层530可形成为覆盖第五接触部分611，第五接触部分611将第二半导体芯片600电连接至外部装置。然而，在一些实施例中，第二保护层530可形成为覆盖第二半导体芯片600的侧壁并且暴露第五接触部分611及第二半导体芯片600的顶表面605。也就是，图9中示出的第二保护层530可被附加地平坦化，以暴露第五接触部分611及第二半导体芯片600的顶表面605。
参考图10，可以图案化图9中示出的第二保护层530，以形成选择性地暴露第五接触部分611的开口531。开口531可通过使用选择蚀刻工艺或钻孔工艺选择性地移除第二保护层530的一些部分而形成。钻孔工艺可以包括激光钻孔工艺或微钻孔工艺。
参考图11，外部电极650可形成在开口531暴露的各个第五接触部分611上。第五接触部分611可对应于第三贯穿电极610的端部。然而，在采用电连接至第五接触部分611的重分布内连（未示出）的情况下，开口531可形成为暴露重分布内连的一些部分，并且可以在重分布内连的暴露部分（对应于连接垫）上形成外部电极650。外部电极650可形成为具有焊料球形状、焊料凸块形状、导电板形状或内连线形状。
参考图12，在形成第二保护层530与外部电极650之后，可以选择性地移除半导体芯片堆叠400之间的第一保护层510、一部分的插入体200以及第二半导体芯片600之间的第二保护层530，以使半导体芯片堆叠400和第二半导体芯片600分离成多个离散的半导体堆叠封装体690。分离工艺可通过使用金刚石刀或激光的切割工艺来执行。
如图12所示，参考图2至12描述的实施例的半导体堆叠封装体690的每一个可配置为包括半导体芯片堆叠400中之一、第二半导体芯片600中之一以及其间的插入体200。在每一半导体堆叠封装体690中，穿透插入体200的第一贯穿电极210可电连接至穿透半导体芯片堆叠400的各个第二贯穿电极401，并且第一贯穿电极210可电连接至第二半导体芯片600的各个第六接触部分613。第二半导体芯片600的第五接触部分611可电连接至外部电极650。半导体芯片堆叠400可包括具有高集成密度及大数据容量的多个堆叠的半导体芯片（例如，多个堆叠的存储器芯片），且作为单个芯片安装在插入体200上的第二半导体芯片600可以是具有相对高的信号处理速度的逻辑芯片（例如，控制芯片）。
如果半导体芯片堆叠400包括多个堆叠的存储器芯片且第二半导体芯片600是逻辑芯片，逻辑芯片可设置为比半导体芯片堆叠400与外部电极650之间的距离更靠近外部电极650。这样定位逻辑芯片在半导体堆叠封装体690的操作速度及可靠性方面可以是有帮助的。因此，当半导体芯片111、113及115是存储器芯片且如图1所示仅堆叠在基板100的一个表面上时，逻辑芯片可用作半导体芯片堆叠110的最下面的芯片，以改善半导体堆叠封装体690的操作速度及可靠性。在此情况下，如图13所示，可以顺次堆叠逻辑芯片20及多个存储器芯片31。
参考图13，具有第一贯穿电极21的逻辑芯片20可堆叠在基板10上，以便与外部电极（未示出）（例如，附着至基板10的与逻辑芯片20相反的底表面的焊料球）有相对快的数据通信。在此情况下，多个存储器芯片31可堆叠在逻辑芯片20上，与基板10相反。因此，可以根据堆叠的存储器芯片31的数目来确定穿透堆叠的存储器芯片31的第二贯穿电极33的每一个的实质长度。也就是，如果堆叠的存储器芯片31的数目增加，则第二贯穿电极33的每一个的垂直长度也可增加。因此，当对包括堆叠的存储器芯片31的半导体芯片堆叠30的顶部施加热及压力以将第二贯穿电极33的下部分连接和/或接合至第一贯穿电极21（见图13的结合部分）时，热及压力通过第二贯穿电极33传导，第二贯穿电极33的垂直长度可能变长。于是，当堆叠的存储器芯片31的数目增加时，可靠地实现第一贯穿电极21与第二贯穿电极23之间的电性及机械结合/连接可能变得更加困难。
为了甚至在堆叠的存储器芯片31的数目增加的情况下可获得第一贯穿电极21与第二贯穿电极33之间的可靠的结合/连接，应增加施加至半导体芯片堆叠30的热能及压力。在此情况下，邻近半导体芯片堆叠30的顶表面设置的存储器芯片31可能由于增加的热能和增加的压力而被损坏。结果，半导体芯片堆叠30可能失灵。
可替换地，为了甚至在堆叠的存储器芯片31的数目增加的情况下可获得第一贯穿电极21与第二贯穿电极33之间的可靠的结合/连接，应考虑的是，每当以堆叠的存储器芯片31之间的粘接剂32堆叠每一堆叠的存储器芯片31时，在可靠的结合/连接之后执行电功能测试。然而，在此情况下，可能花相对长的时间来制造半导体堆叠封装体。因此，半导体堆叠封装体的制造成本可能随着生产量的下降而增加。
与以上参考图13示出的对比示例成对比，根据图8中所示的实施例的半导体堆叠封装体可通过在插入体200的一个表面上顺次安装第一至第三芯片410、450及470（对应于存储器芯片）并且通过在插入体200的另一表面上安装第二半导体芯片600（对应于不同于第一至第三芯片410、450及470的逻辑芯片）来制造。因此，当在插入体200上安装第二半导体芯片600时，可能不需要过大的热能及过大的压力。
此外，如上所述，第二半导体芯片600可以实质安装在包括插入体200及第一保护层510的芯片堆叠基板501上。因此，甚至当第二半导体芯片600安装在芯片堆叠基板501上时，第一至第三芯片410、450及470也可通过插入体200及第一保护层510被保护。相较之下，当使逻辑芯片20与半导体芯片堆叠30结合时，图13示出的对比示例的半导体芯片堆叠30可在没有任何其它基板或任何其它支撑物（例如，保护层）的情况下被处理和/或转移。因此，当逻辑芯片20与半导体芯片堆叠30结合时或当在半导体芯片堆叠30与逻辑芯片20之间的结合之后执行后续功能测试时，可能更易损坏半导体芯片堆叠30。然而，根据图2至12示出的示范实施例，半导体芯片堆叠400可以通过插入体200及第一保护层510被完全包围。因此，半导体芯片堆叠400可以使用穿透插入体200的第一贯穿电极210而被电测试，并且甚至在半导体芯片堆叠400被转移或处理时，半导体芯片堆叠400也可被插入体200及第一保护层510包封。因此，当转移或处理芯片堆叠基板501时，不会损坏半导体芯片堆叠400。
根据图4及5的描述，可以在插入体200上顺次堆叠第一至第三芯片410、450及470。然而，本发明构思并不局限于此。例如，半导体芯片堆叠400可以主要通过以相同或相似于图13示出的对比示例的方式顺次堆叠第一至第三芯片410、450及470而形成，并且随后半导体芯片堆叠400可直接安装在插入体200上。
图14是示出根据本发明构思的变型实施例的半导体堆叠封装体并且示出制造半导体堆叠封装体的方法的截面图。这些变型实施例类似于图2至12示出的先前的实施例。因此，为了避免重复说明，下面将主要详细描述本变型实施例与图2至12示出的先前的实施例之间的差异。
参考图14，第二保护层535可形成为覆盖第二半导体芯片600的整个侧壁607并且暴露第二半导体芯片600的顶表面605。例如，可将第二保护层535模制或变形为具有暴露第二半导体芯片600的顶表面605的平坦表面。
根据图2至12示出的实施例，半导体芯片堆叠400的每一个都可包括顺次堆叠的三个芯片410、450及470。然而，本发明构思并不局限于此。例如，根据图14示出的变型实施例，半导体芯片堆叠400的每一个可进一步包括堆叠在第三芯片470上的第四芯片490，第三芯片470与第四芯片490之间具有第一中间绝缘层430。第四芯片490可配置为不包括任何穿透其本体的贯穿电极。
图15是示出包括根据一些实施例的半导体堆叠封装体的电子系统的示例的示意方块图。在电子系统700（例如，电脑、移动电话之类）中可以使用根据前述实施例的半导体堆叠封装体。电子系统700可配置为包括主板701及安装在主板701上的各种电子装置和/或封装体。主板701可以是印刷电路板（PCB）。电子封装体中的至少一者可以使用参考图2至12、14及15描述的实施例中之一来实现。
电子系统700可以包括安装在主板701上通过数据总线（未示出）彼此通信的运算处理器703、存储/控制单元705、储存单元707、视频处理器709及网络适配器711。运算处理器703可以是微处理器，以及存储/控制单元705可以是半导体堆叠封装体，其包括像DRAM芯片的存储器芯片及控制存储器芯片的操作的逻辑芯片。此外，储存单元707可以包括非易失性存储器装置和/或硬盘，且视频处理器709可以是半导体堆叠封装体，其包括诸如用以暂时储存视频数据的视频DRAM芯片的存储器芯片及用以处理/控制储存在视频DRAM芯片中的视频数据的视频控制器。此外，网络适配器711可以对应于接口单元。也就是，网络适配器711可以传送电性数据至外部通信网络或可以从外部通信网络接收电性数据。
储存在储存单元707中的程序数据通过数据总线可加载到存储/控制单元705中并且可以由运算处理器703来执行。在一些实施例中，储存单元707可配置为包括具有多个闪存装置的固态硬盘（SSD，亦称为固态驱动器）。此外，电子系统700可进一步包括用以接收数据的输入装置713及用以显示其中处理的数据的输出装置715。输入装置713可以包括键盘或触敏显示屏，而输出装置715可以包括显示监视器、打印机或显示屏。电子系统700可以对应于个人电脑、伺服器或移动系统。移动系统可以包括膝上型电脑、手持式电脑或智能手机。
根据上述实施例，可以在基板（例如，插入体）的第一表面上顺次堆叠多个第一半导体芯片并且可以在基板的与第一表面相反的第二表面上堆叠至少一个第二半导体芯片。第二半导体芯片在功能和/或尺寸上可以不同于第一半导体芯片。因此，上述实施例可以处理第二半导体芯片及第一半导体芯片仅顺次堆叠在基板的一个表面上时所发生的问题。
为了说明，上面已披露本发明构思的实施例。本领域技术人员应理解，在不偏离所附权利要求披露的本发明构思的范围及精神的情况下，各种变型、添加及替换是可能的。
本申请要求2011年12月14日提交韩国知识产权局的韩国申请第10-2011-0134708号的优先权，其全部内容引用结合于此。

Claims (15)

1.一种半导体堆叠封装体，包括：
插入体；
半导体芯片堆叠，包括垂直堆叠在该插入体的顶表面上的多个第一半导体芯片；
第二半导体芯片，堆叠在该插入体的与该半导体芯片堆叠相反的底表面上；以及
外部电极，附着至该第二半导体芯片的与该插入体相反的顶表面。
2.如权利要求1所述的半导体堆叠封装体，还包括：
第一贯穿电极，穿透该插入体；
第二贯穿电极，穿透该第一半导体芯片以将该第一半导体芯片电连接至该第一贯穿电极；以及
第三贯穿电极，穿透该第二半导体芯片以将该第一贯穿电极电连接至该外部电极。
3.一种半导体堆叠封装体，包括：
第一贯穿电极插入其中的插入体；
半导体芯片堆叠，包括垂直堆叠在该插入体的顶表面上的多个第一半导体芯片；
第二贯穿电极，穿透该半导体芯片堆叠以电连接至该第一贯穿电极；
第二半导体芯片，在该插入体的底表面上；以及
第三贯穿电极，穿透该第二半导体芯片以电连接至该第一贯穿电极。
4.如权利要求3所述的半导体堆叠封装体，还包括覆盖该半导体芯片堆叠的保护层。
5.如权利要求3所述的半导体堆叠封装体，其中该多个第一半导体芯片中的每一个包括存储器芯片。
6.如权利要求3所述的半导体堆叠封装体，其中该第二半导体芯片包括逻辑芯片。
7.如权利要求3所述的半导体堆叠封装体，还包括覆盖该第二半导体芯片的保护层。
8.如权利要求7所述的半导体堆叠封装体，其中该保护层覆盖该第二半导体芯片的侧壁并且暴露该第二半导体芯片的与该插入体相反的顶表面。
9.如权利要求3所述的半导体堆叠封装体，还包括电连接至该第三贯穿电极的外部电极。
10.一种制造半导体堆叠封装体的方法，该方法包括：
在插入体的顶表面上垂直堆叠多个第一半导体芯片，以形成半导体芯片堆叠；以及
在该插入体的与该半导体芯片堆叠相反的底表面上堆叠第二半导体芯片。
11.如权利要求10所述的方法，还包括：
形成穿透该插入体的本体的第一贯穿电极，
其中该第一贯穿电极的一端暴露于该插入体的顶表面以构成第一接触部分，以及该第一贯穿电极的另一端暴露于该插入体的底表面以构成第二接触部分。
12.如权利要求11所述的方法，其中该半导体芯片堆叠形成为包括穿透该多个第一半导体芯片以使该第一半导体芯片彼此电连接的第二贯穿电极，并且该第二贯穿电极电连接至该第一贯穿电极。
13.如权利要求11所述的方法，其中该第二半导体芯片形成为包括穿透该第二半导体芯片的本体的第二贯穿电极，并且该第二贯穿电极电连接至该第一贯穿电极。
14.如权利要求13所述的方法，还包括将外部电极附着至该第二贯穿电极。
15.如权利要求10所述的方法，其中该插入体是包括硅材料的基板。
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