CN100438022C - 半导体装置及其制造方法、电路基板及电子机器 - Google Patents

半导体装置及其制造方法、电路基板及电子机器 Download PDF

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CN100438022C
CN100438022C CNB2004100559290A CN200410055929A CN100438022C CN 100438022 C CN100438022 C CN 100438022C CN B2004100559290 A CNB2004100559290 A CN B2004100559290A CN 200410055929 A CN200410055929 A CN 200410055929A CN 100438022 C CN100438022 C CN 100438022C
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semiconductor device
chip
substrate
manufacture method
semiconductor
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CN1581483A (zh
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山口浩司
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

提供一种半导体装置及其制造方法，电路基板和电子机器。半导体装置的制造方法包括：在第一面(20)具有多个芯片搭载区域(38)的半导体基板(10)的、起于第一面(20)的凹部(22)内形成导电部(20)的步骤；在各个芯片搭载区域(38)上至少各一个堆叠半导体芯片(40)的步骤；在半导体基板(10)的第一面(20)上设置密封材料(46)的步骤；和从第二面(20)除去半导体基板(10)的一部分让其减薄，让导电部(30)从第一面(20)与第二面(21)贯通的步骤。这样，可以提高生成效率以及可靠性。

Description

半导体装置及其制造方法、电路基板及电子机器
技术区域
本发明涉及一种半导体装置及其制造方法、电路基板及电子机器。
背景技术
三维安装方式的半导体装置正在开发中。此时，为谋求整体的薄型化，可对各个半导体基板进行磨削使其变薄。在过去的方法中，是把多个半导体芯片之间堆叠而成的，整个工序必须以半导体芯片为单位进行处理，因此生产效率差。或者，另一种想法是把多个半导体晶片之间进行堆叠，然后切断成单片，但这不仅使半导体装置的合格率变差，薄型加工后的半导体晶片的处理也变得困难。
专利文献1：特开2002-50738号公报。
发明内容
本发明的目的在于，对于半导体装置及其制造方法、电路基板及电子机器，谋求生产效率和可靠性的提高。
(1)有关本发明的半导体装置的制造方法，包括：
(a)在第一面具有多个芯片搭载区域的基板的、起于所述第一面的凹部内形成导电部的步骤；
(b)在所述芯片搭载区域上堆叠半导体芯片的步骤；
(c)在所述基板的所述第一面上设置对至少一个半导体芯片进行密封的密封材料的步骤；和
(d)从第二面除去所述基板的一部分让其减薄，让所述导电部从所述第一面与所述第二面贯通的步骤。
根据本发明，可以用密封材料加固基板，可以稳定进行基板的薄型化工序，以提高可靠性。另外，基板具有多个芯片搭载区域，可以成批制造多个堆叠结构的半导体装置，以提高生产效率。
(2)在该半导体装置的制造方法中，在所述步骤(a)～(d)结束之后，进一步包括切断相邻所述芯片搭载区域之间，获得多个单片的步骤。
(3)在该半导体装置的制造方法中，采用第一切刀切削所述密封材料，采用第二切刀切削所述基板。这样，可以对多个对象物的每一个适用最佳切削方式。另外，即使在第1切刀上附着密封材料的切削粉末的情况，由于采用与第1切刀不同的第2切刀切削基板，可以防止切削不良。
(4)在该半导体装置的制造方法中，所述步骤(a)包括：
在所述基板上形成所述凹部的步骤；
在所述凹部的内面上形成绝缘层的步骤；和
通过介入所述绝缘层在所述凹部内形成所述导电部的步骤。
(5)在该半导体装置的制造方法中，在所述步骤(b)中，在各个所述芯片搭载区域上至少搭载各一个芯片。
(6)在该半导体装置的制造方法中，所述步骤(b)中，在任选一个所述芯片搭载区域上堆叠虚设芯片。由此，可以实现密封材料的流动均匀化。即可以防止密封材料产生流动偏移导致的气泡卷入。因而可提高密封工序的可靠性。
(7)在该半导体装置的制造方法中，所述步骤(b)中，通过在所述芯片搭载区域上堆叠所述半导体芯片或者所述虚设芯片，在各个所述芯片搭载区域上至少搭载各一个芯片。
(8)在该半导体装置的制造方法中，所述半导体芯片，具有贯通两面的贯通电极；
所述步骤(b)中，通过所述贯通电极，将所述半导体芯片与所述基板的所述导电部电连接。
这样，由贯通电极获得两面的电导通，对于2段以上的堆叠的情况特别有效。
(9)在该半导体装置的制造方法中，所述步骤(b)中，通过导线，将所述半导体芯片与所述基板的所述导电部电连接。
(10)在该半导体装置的制造方法中，所述步骤(c)中，在所述基板的所述第一面侧形成具有开口部的掩模，将所述密封材料填充到所述开口部。
(11)在该半导体装置的制造方法中，所述步骤(c)在比大气压减压的处理室内进行。由此可以防止气泡残留在密封材料。
(12)在该半导体装置的制造方法中，在所述步骤(d)结束之后，进一步包括形成具有将所述导电部电连接的多个连接盘部的布线层的步骤。因此，虽然对基板实施薄型加工，由于在第1面上设置有半导体芯片及密封材料，加固了基板，可以稳定形成布线层。
(13)在该半导体装置的制造方法中，进一步包括在所述基板的所述第二面侧上形成树脂层的步骤；
所述连接盘部在所述树脂层上形成。
因此，施加在连接盘部的应力可通过树脂层得到有效缓解。
(14)在该半导体装置的制造方法中，进一步包括在所述连接盘部上设置外部端子的步骤。
(15)在该半导体装置的制造方法中，所述基板是半导体基板。因此，能够抑制信号的延迟，以实现信号处理的高速化。
(16)在该半导体装置的制造方法中，在所述半导体基板上形成多个集成电路；
所述集成电路在各个所述芯片搭载区域上形成，与所述导电部电连接。
(17)在该半导体装置的制造方法中，所述基板是插接板。
(18)有关本发明的半导体装置，包括：
基板，其在第一面上具有多个芯片搭载区域，具有从所述第一面与第二面贯通的贯通电极；
半导体芯片，其被堆叠在所述基板的各个所述芯片搭载区域上；和
密封材料，其被设置在所述基板的所述第一面上，对至少一个半导体芯片进行密封。
(19)在该半导体装置中，所述基板是半导体基板。
(20)在该半导体装置中，在所述半导体基板上形成多个集成电路；
所述集成电路在各个所述芯片搭载区域上形成，与所述贯通电极电连接。
(21)在该半导体装置中，将相邻的所述芯片搭载区域之间切断后构成。
(22)有关本发明的电路基板，安装有上述半导体装置而构成。
(23)有关本发明的电子机器，具有上述半导体装置。
附图说明
图1A～图1D表示有关本发明第1实施方式的半导体装置的制造方法的图。
图2A～图2D表示有关本发明第1实施方式的半导体装置的制造方法的图。
图3A～图3B表示有关本发明第1实施方式的半导体装置及其制造方法的图。
图4A～图4B表示有关本发明第1实施方式的半导体装置及其制造方法的图。
图5A～图5D表示有关本发明第1实施方式的半导体装置的制造方法的图。
图6A～图6B表示有关本发明第1实施方式的半导体装置的制造方法的图。
图7A～图7B表示有关本发明第1实施方式的半导体装置及其制造方法的图。
图8表示有关本发明第1实施方式的半导体装置及其电路基板的图。
图9表示有关本发明实施方式的电子机器的图。
图9表示有关本发明实施方式的电子机器的图。
图11A～图11C表示有关本发明第1实施方式的半导体装置的制造方法的图。
图中：10-半导体基板，12-集成电路，14-电极，22-凹部，28-绝缘层，30-导电部，38-芯片搭载区域，40-半导体芯片，42-贯通电极，46-密封材料，48-开口部，50-掩模，56-树脂层，60-布线层，64-连接盘部，66-绝缘层，70-外部端子，74-第1切刀，78-第2切刀，90-半导体芯片，92-电线。
具体实施方式
下面，关于本发明的实施方式参照附图进行说明。
(第1实施方式)
图1A～图8表示有关适用本发明的第1实施方式的半导体装置及其制造方法的图。首先，准备基板(半导体基板10)。在本实施方式中，作为基板，使用半导体基板(例如硅基板)10。半导体基板10也可以是半导体晶片。在本实施方式中，半导体基板10上形成有多个集成电路12(参照图3A)。半导体基板10上可以形成与集成电路12电连接的电极(例如焊盘)14。一个集成电路12上可以形成1组多个电极14。1组多个电极14，可以沿集成电路12区域的端部(例如矩形区域相对面的2边，或者4边)排列。电极14多种情况采用铝或者铜等金属形成。
半导体基板10上形成1层或1层以上的钝化膜16、18。钝化膜16、18，可用例如SiO2、SiN、聚酰亚胺树脂等形成。在图1A所示例中，钝化膜16上形成有电极14、连接集成电路12和电极14的的布线(图上未画出)。另外，另一钝化膜18避开电极14的表面至少一部而形成。钝化膜18，也可以在覆盖电极14的表面形成后，蚀刻其一部分使电极14的一部分露出来。蚀刻可采用干式蚀刻及湿式蚀刻中任意一种。钝化膜18的蚀刻时，电极14的表面也可以被蚀刻。
在本实施方式中，在半导体基板10，由第1面20形成凹部22(参照图1C)。第1面20是形成电极14一侧(形成集成电路12一侧)的面。凹部22避开集成电路12的元件以及布线形成。如图1B所示，电极14上也可形成贯通孔24。贯通孔24的形成上可适用蚀刻(干式蚀刻或湿式蚀刻)。蚀刻也可在采用平板印刷工序形成图案化后的保护层(图中未画出)之后进行。电极14的下面形成钝化膜16时，这里也形成贯通孔26(参照图1C)。电极14的蚀刻在钝化膜16上终止时，为形成贯通孔26，也可将电极14的蚀刻中使用的蚀刻剂换成其他蚀刻剂。此时，也可以再一次采用平板印刷工序形成图案化后的保护层。
如图1C所示，为了与贯通孔24(及贯通孔26)连通，在半导体基板10上形成凹部22。贯通孔24(及贯通孔26)和凹部22也可合起来称之为凹部。凹部22的形成可采用蚀刻(干式蚀刻和湿式蚀刻)。蚀刻也可在采用平板印刷工艺形成图案化后的保护层(图中未画出)之后进行。或者凹部22的形成可使用激光(例如CO2激光、YAG激光等)。激光也可适用于贯通孔24、26的形成。也可以采用一种蚀刻剂或者激光，连续进行凹部22及贯通孔24，26的形成。凹部22的形成也可采用喷砂加工。
如图1D所示，凹部22的内侧可形成绝缘层28。绝缘层28可以是氧化膜或氮化膜。例如，半导体基板10由Si形成时，绝缘层28可以是SiO2也可以是SiN。绝缘层28形成在凹部22的底面。绝缘层28形成在凹部22的内壁面。但是，绝缘层28形成为不埋没凹部22。即，由绝缘层28形成凹部。绝缘层28也可形成在钝化膜16的贯通孔26的内壁面。绝缘层28也可形成在钝化膜18上。
绝缘层28也可形成在电极14的贯通孔24内壁面。绝缘层28避开电极14的一部分(例如其上面)而形成。也可覆盖电极14的整个表面形成绝缘层28，再将其一部分蚀刻(干式蚀刻或湿式蚀刻)，露出电极14的一部分。蚀刻可在采用平板印刷工艺形成图案化后的保护层(图中未画出)之后进行。
然后，在凹部22(例如绝缘层28的内侧)设置导电部30(参照图2B)。导电部30也可用Cu或W等形成。如图2A所示，也可在形成导电部30的外层部32后形成其中心部34。中心部34可用Cu、W、掺杂多晶硅(例如低温多晶硅)的任意一个来形成。外层部32至少包含阻挡层。关于阻挡层，中心部34或者下面说明的晶种层的材料是在半导体基板10(例如Si)上防止扩散的材料。阻挡层可用与中心部34不同的材料(例如TiW、TiN)形成。中心部34采用电解电镀形成时外层部32也可包含晶种层。晶种层在形成阻挡层之后形成。晶种层由和中心部34同样的材料(例如Cu)等形成。另外，导电部30(至少其中心部34)也可以采用无电解电镀或喷墨方式形成。
如图2B所示，外层部32也在钝化膜18上形成时，如图2C所示，对外层部32的钝化膜18(及绝缘层28)上的部分进行蚀刻。外层部32形成后，通过形成中心部34，可设置导电部30。导电部30的一部分位于半导体基板10的凹部22内。凹部22的内壁面和导电部30之间由于存在绝缘层28，因此两者的电连接被切断。导电部30，与电极14(集成电路12)电连接。例如，导电部30也可与电极14的绝缘层28的露出部接触。导电部30的一部分可位于钝化膜18上。导电部30也可只在电极14的区域内设置。导电部30可从凹部22的上方凸出。例如，导电部30可从钝化膜18(及绝缘层28)凸出。
另外，作为变形例，也可以在将外层部32留在钝化膜18上的状态下形成中心部34。此时，与中心部34连续的层在钝化膜18上方形成，因此对此层蚀刻。
如图2D所示，导电部30上可设置焊料36。详细讲，在导电部30中，在从第1面20凸出部分的前端面上设置焊料36。焊料36用焊锡等形成，也可用软焊料(soft solder)及硬焊料(hard solder)的任意一个来形成。焊料36可把导电部30以外的区域用保护层覆盖形成。
如图3A所示，半导体基板10在第1面20有多个芯片搭载区域38。多个芯片搭载区域38分别配置在平面上不同的区域。各个芯片搭载区域38也可排列配置在多个行多个列中。各个芯片搭载区域38可对应任意一个集成电路12(或者任意一个组的多个电极14)配置。换句话说，各个集成电路12形成在任意一个芯片搭载区域38。另外，这个时候导电部30和第2面(与第1面20相反的面)21是未贯通的。即导电部30的第2面21侧的前端部埋入在半导体基板10的内部。
如图3B所示，各个芯片搭载区域38上至少要堆叠一个半导体芯片40。一个芯片搭载区域38，可以堆叠一个半导体芯片40，也可堆叠多个(图3B中是三个)半导体芯片40。半导体芯片40上形成有集成电路(图中未画出)。在本实施方式中，半导体芯片40有贯通其两面的贯通电极42。半导体芯片40通过贯通电极42与半导体基板10的导电部30连接。贯通电极42和导电部30的电连接通过焊料36进行。多个半导体芯片40进行堆叠时，上下贯通电极42之间的电连接是通过焊料44进行的。因此，通过贯通电极42可实现两面的电导通，在2段以上堆叠时适用时特别有效。
半导体基板10的芯片搭载区域38有不良(例如集成电路12或者导电部30缺陷引起的不良)时，其芯片搭载区域38也可不安装半导体芯片40而作为空余空间。这样不用浪费良品半导体芯片40。或者，不设置空余空间，而在不良芯片搭载区域38堆叠虚设芯片。虚设芯片最好是具有与良品时的半导体芯片40一样或类似的外形的基材(例如半导体芯片或树脂芯片)。虚设芯片最好堆叠成与周围良品半导体芯片40几乎同样高度。虚设芯片进行堆叠能够使下述的密封工序的可靠性提高。
如图4A所示，半导体基板10的第1面20上设置密封材料46。密封材料46可以是树脂(例如环氧树脂)。密封材料46至少密封电连接部(例如贯通电极42之间的连接部、导电部30和贯通电极42之间的连接部)。密封材料46至少密封一个半导体芯片40。如图4A所示，也可对第1面20上的全部半导体芯片40进行密封。密封工序通过让液状的密封材料46的材料在第1面20上流动进行。半导体基板10上均匀配置多个半导体芯片40(及虚设芯片)时，即芯片搭载区域38上不设置空余空间时，可实现密封材料46的流动的均匀化。即密封材料46难以产生流动偏移，可以防止气泡的卷入。随之可提高密封工序的可靠性。
密封材料46可以采用印刷方式形成(例如丝网印刷方式)。如图4A所示，有开口部48的掩模(例如金属掩模)50形成在第1面20侧，密封材料46的材料填充至开口部48。此时利用擦浆板52让密封材料46的上面变平坦，使其与掩模50的高度相同。作为变形例，也可以采用分配器涂敷密封材料46的材料(浇灌工序)。也可用模具等进行密封材料46的成型(模塑工序)。或者也可以采用在喷墨打印机中应用的喷墨方式，喷出密封材料料46。
密封工序在将大气压减压过的处理室内进行。处理室内最好能够减压至真空(要求精度范围内的真空)状态。以此可防止密封材料46中残留气泡。随之半导体装置的可靠性也将提高。
然后，除去掩模50，可在半导体基板10上形成由密封材料46形成的密封部。如图4B所示，中，除去第2面21的一部分而半导体基板10减薄。例如，利用机械方法及化学方法中至少一种方法来磨削。对半导体基板10，也可用磨石等对表面进行磨削、研磨，也可实施蚀刻加工。在本实施方式中，因密封材料46加固了半导体基板10，使之半导体基板10的磨削、研磨及蚀刻等工序能够稳定进行。因此，没必要在半导体基板10上另外设置加固部件，可以简化制造工序及制造设备。半导体基板10的薄型化工序，可分成多次进行。例如，在第1次的薄型化工序中进行磨削、研磨直到在凹部22形成的绝缘层28快要露出为止，在第2次以后的薄型化工序中让绝缘层28露出。为使导电部30(详细讲是其凹部22内的部分)以覆盖在绝缘层28的状态凸出，可对半导体基板10的第2面21进行蚀刻。蚀刻，可以采用具有对半导体基板(例如Si)10的蚀刻量比对绝缘层(例如SiO2)28的蚀刻量多的性质的蚀刻剂进行。蚀刻剂也可以是SF6或者CF4或者Cl2气体。蚀刻可使用干式蚀刻装置。或者，蚀刻剂也可以是氟酸及硝酸的混合液或者是氟酸、硝酸及醋酸的混合液。
这样，导电部30能够在半导体基板10中从第1面20贯通至第2面21。导电部30称为贯通电极。在如图4B所示例中，导电部30从第2面21突起。导电部30的突起部份也可由绝缘层28覆盖。在这个堆叠结构的半导体装置(集合体)中，在第1面20上堆叠了多个半导体芯片40，第1面20上设置有密封材料46。有关本实施方式的半导体装置与上述说明的制造方法的内容相当。
接下来，如图5A～图6B所示，半导体基板10上设置有布线层(再配置布线层)60。另外，在图5A～图6B中省略了半导体芯片40及密封材料46。
如图5A所示，导电部30露出在第2面21上。详细讲，除去绝缘层28，导电部30露出第2面21。也可以除去导电部30的一部分而露出新生面。关于导电部30的露出，可适用用磨石的磨削、研磨工序，也可适用蚀刻工序。
如图5B所示，形成绝缘层(例如氧化膜或者氮化膜)54。绝缘层54用于切断半导体基板10和后述的布线层60之间的电连接。绝缘层54是除去导电部30，在第2面21的整个面上形成。绝缘层54也可以形成为覆盖至导电部30，然后除去(例如蚀刻)一部分，露出导电部30。或者，绝缘层54，也可避开导电部30形成。
作为变形例，如图4B所示，导电部30也可以在由绝缘层28覆盖的状态，在第2面21形成绝缘层54，通过除去绝缘层54及绝缘层28，露出导电部30。
如图5C所示，在第2面21侧形成树脂层56。树脂层56由1层或多个层形成。树脂层56避开导电部30形成。树脂层56也可形成在第2面21上的多个区域。例如，把树脂层56形成在由1组的多个电极14包围的区域上重叠形成。树脂层56也可让其相反面(底面)比上面大，把侧面倾斜至反对时。树脂层56可用聚酰亚胺树脂、硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、BCB(benzocyclobutene)、PBO(polybenzoxazole)等树脂形成。
如图5D所示，半导体基板10的第2面21侧形成布线层(例如铜(Cu)层)60。布线层60与导电部30电连接，在绝缘层54上及树脂层56上形成。布线层60形成1层或多层。布线层60也可包含扩散防止用阻挡层(例如Ti、Cr、Ni、TiW)。布线层60可以采用溅射、电镀、无电解电镀、喷墨方式和印刷方式的任意一种或多个组合形成。另外，布线层60利用平板印刷技术进行图案化。布线层60拥有线部62及与此连接的连接盘部64。线部62，其一部分与导电部30重叠，延伸至树脂层56之上。连接盘部64是电连接部，其宽度比线部62的宽度要大。连接盘部64最好形成在树脂层56上。这样，施加在连接盘部64的应力通过树脂层56能够得到有效的缓解。邻间的连接盘部64的间距，比相邻的导电部30(或者相邻的电极14)的间距要大。即就是说，多个连接盘部64进行间距变换。例如，多个连接盘部64以区域阵列状扩散。这样，多个连接盘部64(或者外部端子70)具有一定面，半导体装置的安装变得容易。
如图6A所示，在半导体基板10的第2面21侧形成绝缘层(例如焊锡保护层)66。绝缘层66形成为覆盖布线层60的一部分(例如连接盘部64的端部及线部62)。换言之，绝缘层66具有露出布线层60的一部分(例如连接盘部64的中央部)的开口部68。根据绝缘层66，能够防止布线层60的氧化、腐蚀、电接触不良等现象。
如图6B所示，也可以在布线层60上形成电连接的外部端子70。外部端子70设置在连接盘部64上。当绝缘层66的开口部68露出连接盘部64的中央部时，在连接盘部64的中央部上设置外部端子70。外部端子70和半导体基板10之间，介入树脂层56。外部端子70也可以是焊料。焊料例如由焊锡形成、由软焊料(soft solder)及硬焊料(hard solder)的任意一种形成。外部端子70可以做成球状例如是焊锡球。
绝缘层66上设置有覆盖层72。覆盖层72具有绝缘性，例如由树脂形成。覆盖层72连外部端子70的根部(下端部)也覆盖。覆盖层72具有在绝缘层66上形成的部分、和从该部分立起而覆盖外部端子70的根部的部分。覆盖层72，至少对外部端子70的根部加固。半导体装置安装后，可以由覆盖层72缓和施加在外部端子70上的应力。
这样，能够得到堆叠结构的半导体装置(集合体)。在该半导体装置上再次实施布线。在有关本实施方式的半导体装置中，与所述的有关制造方法的说明的内容相当。
在本实施方式中，半导体基板10实施薄型加工，在第1面20设置有半导体芯片40及密封材料46，半导体基板10被加固，因此布线层60及外部端子70能够稳定形成。
如图7A～图7B所示，进行切断工序(切割工序)。详细讲，切断相邻之间的芯片搭载区域38(或者相邻半导体芯片40)之间，获得多个单片(参照半导体装置(参照图8))。切断中可以使用切刀、也可使用激光(例如CO2激光、YAG激光)。也可以在切削后进行切断工序。本实施方式中，多次(例如两次)进行切削工序。或者通过一次切削工序，一起将密封材料46及半导体基板10切断。
如图7A所示，首先，用第1切刀74切削密封材料46。可以只对密封材料46进行切削。可以切削密封材料46的厚度方向的全部、也可切削一部分。此时，也可以不切削半导体基板10。或者，和密封材料46一起，对半导体基板10的一部分(例如表面部分)进行切削也无妨。根据第1切刀74的大小(厚度)，形成密封材料46的凹部76。
如图7(B)所示，用第2切刀78切削半导体基板10。可从第1面20侧切削半导体基板10，也可从第2面21侧切削。从第1面20开始切削时，第2切刀78进入到凹部76内。第2切刀78的宽度(厚度)比第1切刀74的宽度(厚度)小。作为变形例，与上述顺序相反，也可在半导体基板10的切削工序进行后，再进行密封材料46的切削工序。
这样，可以对多个对象物(密封材料46及半导体基板10)的各个对象物适用最好的切削方式。另外，即使第1切刀74粘附了切削粉末(例如密封材料46的切削粉末)时，由于采用与第1切刀不同的的第2切刀切削半导体基板10，可防止切削不良。
这样，如图8所示，能够得到堆叠结构的半导体装置(单体)。半导体装置1安装在电路基板(例如母板)1000上。电路基板1000上，形成布线图案1100，布线图案1100上电连接外部端子70。对于有关本实施方式的半导体装置，与所述的有关制造方法的说明的内容相当。另外，作为具有有关本发明实施方式的半导体装置的电子机器，图9表示笔记本型个人计算机2000，图10表示移动电话机3000。
作为本实施方式的变形例，使用未形成集成电路的半导体基板(例如硅基板)，替代半导体基板10，也可以适用上述内容。该半导体基板，成为半导体封装的插接板。因此，由于在半导体芯片40和电路基板1000之间介入半导体部分，比介入绝缘部分(例如树脂基板)，可以降低介电常数，抑制信号的延迟。
作为本实施方式的变形例，使用半导体基板以外的基板也可以适用上述内容。基板可以使用有机类(例如树脂基板)、无机类(例如玻璃基板)或者这些复合材料的任意一种。基板可使用刚性基板或者柔性基板。基板成为半导体组件的插接板。基板上不形成集成电路。贯通基板两面的导电部称之为通孔。其他可适用上述半导体基板10的内容。
(第2实施方式)
图11A～图11C表示有关本发明第2实施方式的半导体装置及其制造方法的图。在本实施方式中，半导体基板10的各个芯片搭载区域38中，至少堆叠一个半导体芯片90。如图11A所示，半导体芯片90可以面朝上焊接。这时，可适用引线接合技术。即，通过引线92将半导体芯片90与半导体基板10的导电部30电连接。作为变形例，半导体芯片90可采用倒装焊接法。然后，如图11B所示，在第1面20上设置密封材料46，如图11C所示，进行半导体基板10的薄型化工序。通过将半导体基板10减薄，让导电部30从第2面21凸出。导电部30的突起部分也可以被绝缘层38覆盖。然后，如图11C的箭头所示方向，切断相邻芯片搭载区域38(或者相邻半导体芯片90)之间，获得多个单片。在切断工序前，也可以在半导体基板10上形成布线层(再配置布线层)。其他详情可适用上述内容，有关本实施方式的半导体装置，与上述有关制造方法的说明的内容相当。
本发明不只局限在于上述实施方式，可有多种变形。例如，本发明包含和在实施方式中说明的构成实质上相同的构成(例如，功能、方法及结果相同的构成、或者目的及结果相同的构成)。另外，本发明包含将在实施方式中说明的非本质部分进行置换后的构成。本发明包含和在实施方式中说明的构成具有相同作用效果的构成，或者能够达到相同目的的构成。另外，本发明包含在实施方式中说明的构成上附加了公知技术后的构成。

Claims (23)

1、一种半导体装置的制造方法，其特征在于，包括：
步骤a，在第一面具有多个芯片搭载区域的基板的、起于所述第一面的凹部内形成导电部；
步骤b，在所述芯片搭载区域上堆叠半导体芯片；
步骤c，在所述基板的所述第一面上设置对至少一个半导体芯片进行密封的密封材料；和
步骤d，从第二面除去所述基板的一部分让其减薄，让所述导电部从所述第一面与所述第二面贯通。
2、根据权利要求1所述的半导体装置的制造方法，其特征在于，在所述步骤a～步骤d结束之后，进一步包括切断相邻所述芯片搭载区域之间，获得多个单片的步骤。
3、根据权利要求2所述的半导体装置的制造方法，其特征在于，采用第一切刀切削所述密封材料，采用第二切刀切削所述基板。
4、根据权利要求1～3中任一项所述的半导体装置的制造方法，其特征在于，所述步骤a包括：
在所述基板上形成所述凹部的步骤；
在所述凹部的内面上形成绝缘层的步骤；和
通过介入所述绝缘层在所述凹部内形成所述导电部的步骤。
5、根据权利要求1～3中任一项所述的半导体装置的制造方法，其特征在于，在所述步骤b中，在各个所述芯片搭载区域上至少搭载各一个芯片。
6、根据权利要求1～3中任一项所述的半导体装置的制造方法，其特征在于，所述步骤b中，在任选一个所述芯片搭载区域上堆叠虚设芯片。
7、根据权利要求6所述的半导体装置的制造方法，其特征在于，所述步骤b中，通过在所述芯片搭载区域上堆叠所述半导体芯片或者所述虚设芯片，在各个所述芯片搭载区域上至少搭载各一个芯片。
8、根据权利要求1～3中任一项所述的半导体装置的制造方法，其特征在于，
所述半导体芯片，具有贯通两面的贯通电极；
所述步骤b中，通过所述贯通电极，将所述半导体芯片与所述基板的所述导电部电连接。
9、根据权利要求1～3中任一项所述的半导体装置的制造方法，其特征在于，所述步骤b中，通过导线，将所述半导体芯片与所述基板的所述导电部电连接。
10、根据权利要求1～3中任一项所述的半导体装置的制造方法，其特征在于，所述步骤c中，在所述基板的所述第一面侧形成具有开口部的掩模，将所述密封材料填充到所述开口部。
11、根据权利要求1～3中任一项所述的半导体装置的制造方法，其特征在于，所述步骤c在比大气压减压的处理室内进行。
12、根据权利要求1～3中任一项所述的半导体装置的制造方法，其特征在于，在所述步骤d结束之后，进一步包括形成具有将所述导电部电连接的多个连接盘部的布线层的步骤。
13、根据权利要求12所述的半导体装置的制造方法，其特征在于，进一步包括在所述基板的所述第二面侧上形成树脂层的步骤；
所述连接盘部在所述树脂层上形成。
14、根据权利要求12所述的半导体装置的制造方法，其特征在于，进一步包括在所述连接盘部上设置外部端子的步骤。
15、根据权利要求1～3中任一项所述的半导体装置的制造方法，其特征在于，所述基板是半导体基板。
16、根据权利要求15所述的半导体装置的制造方法，其特征在于，
在所述半导体基板上形成多个集成电路；
所述集成电路在各个所述芯片搭载区域上形成，与所述导电部电连接。
17、根据权利要求1～3中任一项所述的半导体装置的制造方法，其特征在于，所述基板是插接板。
18、一种半导体装置，其特征在于，包括：
基板，其在第一面上具有多个芯片搭载区域，具有从所述第一面与第二面贯通的贯通电极；
半导体芯片，其被堆叠在所述基板的各个所述芯片搭载区域上；和
密封材料，其被设置在所述基板的所述第一面上，对至少一个半导体芯片进行密封。
19、根据权利要求18所述的半导体装置，其特征在于，所述基板是半导体基板。
20、根据权利要求19所述的半导体装置，其特征在于，
在所述半导体基板上形成多个集成电路；
所述集成电路在各个所述芯片搭载区域上形成，与所述贯通电极电连接。
21、根据权利要求18～20中任一项所述的半导体装置，其特征在于，
将相邻的所述芯片搭载区域之间切断后构成。
22、一种电路基板，其特征在于，安装有权利要求18～21中任一项所述的半导体装置而构成。
23、一种电子机器，其特征在于，具有权利要求18～21中任一项所述的半导体装置。
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