CN113056819B - 半导体模块、dimm模块以及它们的制造方法 - Google Patents
半导体模块、dimm模块以及它们的制造方法 Download PDFInfo
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- CN113056819B CN113056819B CN201980005707.2A CN201980005707A CN113056819B CN 113056819 B CN113056819 B CN 113056819B CN 201980005707 A CN201980005707 A CN 201980005707A CN 113056819 B CN113056819 B CN 113056819B
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Abstract
本发明提供一种能够稳定地对层叠的多个存储器芯片进行供电的半导体模块、DIMM模块以及它们的制造方法。本发明涉及一种半导体模块(1),具有多个存储器芯片(21),其具有:存储器衬底(10),其具有露出到一个面即配置面的电源电路(12);以及至少一个存储器单元(20),其配置在存储器衬底(10)的配置面,存储器单元(20)具有:多个存储器芯片(21),其将层叠方向(D)沿着配置面而配置;贯通电极(22),其在层叠方向(D)上贯通多个存储器芯片(21);以及电极层(23),其层叠在层叠方向(D)一端面,与贯通电极(22)和电源电路(12)连接。
Description
技术领域
本发明涉及一种半导体模块、DIMM模块以及它们的制造方法。
背景技术
以往,作为存储装置已知DRAM(Dynamic Random Access Memory,动态随机存取存储器)等易失性存储器(RAM)。对于DRAM要求大容量化,以能够承受运算装置(以下称为逻辑芯片)的高性能化和数据量的增大。因此,通过存储器(存储单元阵列、存储芯片)的微细化以及以平面方式增设单元来谋求大容量化。另一方面,由于由微细化导致的对噪声的脆弱性、裸片(die) 面积的增加等,这种大容量化达到了极限。
因此,最近开发了层叠多个平面式存储器来进行三维化(3D化)从而实现大容量化的技术。例如,提出了一种高密度电子模块,其堆叠并粘接多个集成电路芯片,并且设置了横跨集成电路芯片的直线状电导体(例如参照专利文献1)。
现有技术文献
专利文献
专利文献1:日本特表平3-501428号公报。
发明内容
发明要解决的问题
专利文献1所记载的高密度电子模块通过堆叠多个芯片衬底来谋求高密度化。由此,与将单个集成电路芯片配置在叠层支承衬底的情况相比,能够实现高密度化。
可是,如今存储器芯片的大容量化不断发展。因此,存储器芯片的耗电量也有增加的趋势。在专利文献1中,从配置在集成电路芯片的一侧面的电导体进行供电。像这样,仅从一侧面供电,可能会有对大容量化了的多个存储器芯片供电不足的情况。因此,优选能够稳定地对层叠的多个存储器芯片进行供电。
本发明的目的在于,提供一种能够稳定地对层叠的多个存储器芯片进行供电的半导体模块、DIMM模块以及它们的制造方法。
用于解决问题的方案
本发明涉及一种半导体模块,具有多个存储器芯片,其具有:存储器衬底,其具有露出到一个面即配置面的电源电路;以及至少一个存储器单元,其配置在所述存储器衬底的配置面,所述存储器单元具有:多个存储器芯片,其将层叠方向沿着所述配置面而配置;贯通电极,其在层叠方向上贯通多个所述存储器芯片;以及电极层,其层叠在层叠方向一端面,与所述贯通电极和所述电源电路连接。
此外,优选:半导体模块还具有:粘接层,其配置在邻接的一对存储器单元之间,与至少一个所述存储器单元的所述电极层接触。
此外,优选:半导体模块还具有:连接部,其配置在所述电极层的面内方向一端和所述电源电路之间,将所述电极层和所述电源电路电连接。
此外,优选:所述存储器芯片在与所述存储器衬底邻接的一端部具有能够与所述存储器衬底的通信电路通信的通信部。
此外,优选:半导体模块还具有:贴装部,其配置在所述通信部和所述通信电路之间,将所述存储器单元贴装在所述存储器衬底的配置面。
此外,本发明涉及一种DIMM模块,其具有:多个所述半导体模块;以及 DIMM衬底,其在至少一个面即载置面载置多个所述半导体模块。
此外,本发明涉及一种DIMM模块,其具有:多个所述半导体模块;DIMM 衬底,其在至少一个面即载置面载置多个所述半导体模块;以及散热器,其横跨多个所述半导体模块的各个存储器单元地配置,并且与所述粘接层接触地配置。
此外,本发明涉及一种半导体模块的制造方法,所述半导体模块具有多个存储器芯片,具有:存储器单元形成工序,层叠所述存储器芯片,并且形成贯通所述存储器芯片的贯通电极和配置在所述存储器芯片的层叠方向的一端面的电极层,从而形成存储器单元;存储器芯片配置工序,将所述存储器芯片配置在存储器衬底,所述存储器衬底具有露出到一个面即配置面的电源电路,所述存储器芯片配置工序将所述电极层的面内方向一端和所述电源电路相向配置;以及连接工序,对于所述存储器衬底电连接所述存储器单元。
此外,优选:半导体模块的制造方法还具有:粘接层形成工序,在所述存储器单元形成工序之后、所述存储器芯片配置工序之前,形成粘接层,所述粘接层用于将其他所述存储器单元粘接在所述存储器单元的所述电极层的层叠方向的一个面;以及粘接工序,在所述粘接层形成工序之后、所述存储器芯片配置工序之前,使用所述粘接层粘接两个所述存储器单元。
此外,优选:半导体模块的制造方法还具有:单片化工序,在所述存储器单元形成工序之后、所述粘接层形成工序之前,对所述存储器单元进行单片化。
此外,本发明涉及一种DIMM模块的制造方法,其具有:上述的半导体模块的制造方法;以及载置工序,在DIMM衬底的至少一个面即载置面载置多个已制造的所述半导体模块。
此外,本发明涉及一种DIMM模块的制造方法,其具有:上述的半导体模块的制造方法;载置工序,在DIMM衬底的至少一个面即载置面载置多个已制造的所述半导体模块;以及散热器配置工序,横跨多个所述半导体模块的各个存储器单元并与所述粘接层接触地配置散热器。
发明效果
根据本发明,能够提供一种能够稳定地对层叠的多个存储器芯片供电的半导体模块、DIMM模块以及它们的制造方法。
附图说明
图1为示出本发明的第一实施方式所涉及的半导体模块的立体图。
图2示出图1的A-A线剖视图。
图3为示出第一实施方式的半导体模块的一个制造过程的概要图。
图4为示出第一实施方式的半导体模块的一个制造过程的概要图。
图5为示出第一实施方式的半导体模块的一个制造过程的概要图。
图6为示出第一实施方式的半导体模块的一个制造过程的概要图。
图7为示出具有本发明的第二实施方式所涉及的半导体模块的半导体封装的立体图。
图8示出图7的B-B线剖视图。
图9为示出本发明的第三实施方式所涉及的DIMM模块的立体图。
图10为在第三实施方式所涉及的DIMM模块配置了散热器的立体图。
图11为示出本发明的变形例所涉及的半导体模块的立体图。
具体实施方式
以下,参照图1至图10对本发明的各实施方式所涉及的半导体模块1、 DIMM模块100及其制造方法进行说明。
各实施方式所涉及的半导体模块1例如为具有层叠的多个存储器芯片21 (DRAM芯片)的存储器部件。半导体模块1例如构成为配置有在衬底上层叠的多个存储器芯片21。此时,半导体模块1通过将存储器芯片21的层叠方向 D朝向被配置的存储器衬底10的面内方向,谋求被配置的存储器芯片21的片数的增加。
[第一实施方式]
接下来,参照图1至图6对本发明的第一实施方式所涉及的半导体模块1、 DIMM模块100及其制造方法进行说明。
本实施方式的半导体模块1例如为DRAM模块。如图1和图2所示,半导体模块1具有多个存储器芯片21。而且,半导体模块1通过沿着存储器衬底 10的面内方向配置多个存储器芯片21而构成。半导体模块1具有:存储器衬底10、存储器单元20、粘接层40、连接部50以及贴装部60。另外,粘接层 40也可以为例如在膜状的基材(未图示)的两面涂敷了粘接剂的构件。此外,粘接层40也可以作为对后述的邻接的存储器单元20间的间隙进行调节的间隔件发挥功能。
存储器衬底10例如为硅衬底。存储器衬底10例如为有源内插器(activeinterposer)。即,存储器衬底10具有在厚度方向贯通的多个电极。在本实施方式中,存储器衬底10具有一部分露出到一个面即配置面的电源电路12作为电极。此外,存储器衬底10具有配置在一个面侧的通信电路11(例如信号用上表面电极(非接触通信电路))。在本实施方式中,存储器衬底10具有能够非接触通信的通信电路11。此外,存储器衬底10在另一个面侧具有能够与其他衬底等电连接的凸块30。
存储器单元20层叠多个存储器芯片21而构成。存储器单元20中的至少一个配置在存储器衬底10的配置面。在本实施方式中,配置两个存储器单元 20。存储器单元20具有:存储器芯片21、贯通电极22以及电极层23。
存储器芯片21为包含存储电路的正视呈矩形的板状体。多片存储器芯片 21被层叠。在本实施方式中,四片存储器芯片21被层叠。存储器芯片21将层叠方向D沿着配置面而配置。此外,存储器芯片21在与存储器衬底10邻接的一端部具有能够与存储器衬底10通信的通信部121(例如信号用侧面电极(非接触通信电路))。
贯通电极22例如为由金属等导电体形成的过孔(via)。贯通电极22在层叠方向D上贯通多个存储器芯片21。具体而言,贯通电极22配置成沿着层叠方向D,从配置在一端的存储器芯片21到配置在另一端的存储器芯片21之前配置的存储器芯片21贯通。在本实施方式中,设置多个贯通电极22。
电极层23例如为由金属等导电体形成的板状体。电极层23层叠在层叠方向D一端面,与贯通电极22和电源电路12连接。具体而言,电极层23在配置在层叠方向D的一端侧的存储器芯片21的一端侧的面层叠,与贯通电极22 和电源电路12连接。
粘接层40为正视呈矩形的板状体。此外,粘接层40以在层叠方向D上与电极层23相同或大致相同的大小形成。粘接层40配置在邻接的一对存储器单元20之间。粘接层40与至少一个存储器单元20的电极层23接触。由此,粘接层40将一对存储器单元20彼此粘接。粘接层40使用绝缘材料形成。在本实施方式中,粘接层40由导热率较高的材料(例如氧化铍等基材)形成。
连接部50由金属等导电体形成。连接部50例如为微凸块(micro bump)。连接部50配置在电极层23的面内方向一端和电源电路12之间。连接部50将电极层23和电源电路12电连接。由此,连接部50构成为能够从存储器衬底10的电源电路12对电极层23进行供电。
贴装部60配置在存储器衬底10和存储器芯片21之间。即,贴装部60配置在通信部121和通信电路11之间。贴装部60将存储器单元20贴装在基础部的配置面。
接下来,对本实施方式所涉及的半导体模块1的工作进行说明。
存储器衬底10通过凸块30以及在厚度方向上贯通的电极和电源电路12 向连接部50供电。连接部50向存储器单元20的电极层23供电。然后,电极层23通过多个贯通电极22向各个存储器芯片21供电。
各个存储器芯片21经由通信部121与通信电路11通信。由此,各个存储器芯片21构成为能够与存储器衬底10直接通信。即,各个存储器芯片21构成为能够不受与其他存储器芯片21的同步等影响地通信。
接下来,对本实施方式所涉及的半导体模块1的制造方法进行说明。
本实施方式所涉及的半导体模块1的制造方法具有:存储器单元形成工序、单片化工序、粘接层形成工序、粘接工序、贴装部配置工序、连接部形成工序、存储器芯片配置工序以及连接工序。
首先,如图3所示,在存储器单元形成工序中,形成存储器单元20。具体而言,在层叠了多个存储器芯片21之后,形成贯通电极22和电极层23。即,层叠存储器芯片21,并且形成贯通存储器芯片21的贯通电极22和配置在存储器芯片21的层叠方向D的一端面的电极层23,从而形成存储器单元20。在此,在与层叠方向D交叉的方向上,以多个存储器单元20被连接的状态形成。即,在与层叠方向D交叉的方向上,以多个存储器芯片21被并列设置的状态形成。
接下来,实施单片化工序。在存储器单元形成工序之后、粘接层形成工序之前执行单片化工序。在单片化工序中,存储器单元20被单片化。例如,执行对在存储器单元形成工序中形成的存储器单元20进行单片化的切割。
接下来,实施粘接层形成工序。如图4所示,在粘接层形成工序中,形成粘接层40,所述粘接层40用于将其他存储器单元20粘接在存储器单元20的电极层23的层叠方向D的一个面。
接下来,实施粘接工序。如图5所示,在粘接工序中,使用粘接层40粘接两个存储器单元20。由此,两个存储器单元20在层叠方向D上重叠地配置。
接下来,实施贴装部配置工序。如图2所示,在贴装部配置工序中,例如,在与存储器衬底10的通信电路11重叠的位置配置层状的贴装部60。
接下来,实施连接部形成工序。如图6所示,在连接部形成工序中,在电极层23的面内方向一端(一侧面)形成连接部50。在连接部形成工序中,在各个存储器单元20形成连接部50。
接下来,实施存储器芯片配置工序。在存储器芯片配置工序中,将存储器芯片21配置在存储器衬底10,所述存储器衬底10具有露出到一个面即配置面的电源电路12。在存储器芯片配置工序中,将电极层23的面内方向一端与电源电路12相向配置。
接下来,实施连接工序。在连接工序中,对于存储器衬底10电连接所述存储器单元20。其后,在存储器衬底10的另一个面侧形成能够与其他衬底等电连接的凸块30。由此,形成如图1和图2所示的半导体模块1。
根据如上的第一实施方式所涉及的半导体模块1及其制造方法,起到以下的效果。
(1)一种具有多个存储器芯片21的半导体模块1,其具有:存储器衬底 10,其具有露出到一个面即配置面的电源电路12;以及至少一个存储器单元 20,其配置在存储器衬底10的配置面,存储器单元20具有:多个存储器芯片 21,其将层叠方向D沿着配置面而配置;贯通电极22,其在层叠方向D上贯通多个存储器芯片21;以及电极层23,其层叠在层叠方向D一端面,与贯通电极22和电源电路12连接。由此,能够经由电极层23和贯通电极22从存储器衬底10向各个存储器芯片21供电。因此,与从一侧面向存储器芯片21供电的情况相比,能够使供电稳定。因此,可提供能够实现存储器的大容量化的半导体模块1。
(2)半导体模块1还具有:粘接层40,其配置在邻接的一对存储器单元 20之间,与至少一个存储器单元20的电极层23接触。由此,在将存储器单元 20彼此粘接了的状态下,能够将层叠方向D朝向存储器衬底10的面内方向配置。因此,能够更加容易地进行存储器单元20对于存储器衬底10的安装。此外,通过将导热率高的材料用于粘接层40,能够期待作为散热片的效果。
(3)半导体模块1还具有:连接部50,其配置在电极层23的面内方向一端和电源电路12之间,将电极层23和电源电路12电连接。由此,因为能够得到存储器衬底10和电极层23之间的电连接,所以能够使从存储器衬底10 向存储器单元20的供电稳定。
(4)存储器芯片21在与存储器衬底10邻接的一端部具有能够与存储器衬底10通信的通信部121。由此,各个存储器芯片21能够不受其他存储器芯片21影响地与存储器衬底10通信。因此,与经由层叠方向D的一个端的存储器芯片21与全部存储器芯片21通信的情况相比,能够提供存储器芯片21的延迟较小的半导体模块1。
(5)半导体模块1还具有:贴装部60,其配置在通信部121和通信电路 11之间,将存储器单元20贴装在衬底的配置面。由此,因为存储器芯片21 的侧面被贴装在存储器衬底10,所以能够对于存储器衬底10稳定地安装存储器单元20。
(6)一种具有多个存储器芯片21的半导体模块1的制造方法,具有:存储器单元形成工序,层叠存储器芯片21,并且形成贯通存储器芯片21的贯通电极22和配置在存储器芯片21的层叠方向D的一端面的电极层23,从而形成存储器单元20;配置工序,将存储器芯片21配置在存储器衬底10,所述存储器衬底10具有露出到一个面即配置面的电源电路12,所述配置工序将电极层23的面内方向一端和电源电路12相向配置;以及连接工序,对于存储器衬底10电连接存储器单元20。由此,能够容易地得到使供电稳定了的半导体模块1。
(7)半导体模块1的制造方法还具有:粘接层形成工序,在存储器单元形成工序之后、配置工序之前,形成粘接层40,所述粘接层40用于将其他存储器单元20粘接在存储器单元20的电极层23的层叠方向D的一个面;以及粘接工序,在粘接层形成工序之后、配置工序之前,使用粘接层40粘接两个存储器单元20。由此,能够容易地连接两个存储器单元20。因此,能够容易地形成被对于存储器衬底10配置的多个存储器单元20。
(8)半导体模块1的制造方法还具有:单片化工序,在存储器单元形成工序之后、粘接层形成工序之前,对存储器单元20进行单片化。由此,能够容易地得到多个存储器单元20。
[第二实施方式]
接下来,使用图7和图8对本发明的第二实施方式所涉及的半导体模块1 及其制造方法进行说明。在说明第二实施方式时,对与前述的实施方式相同的结构要素标注相同标记,省略或简化其说明。
如图7和图8所示,第二实施方式所涉及的半导体模块1还具有封装衬底 70和密封部90,在这方面与第一实施方式不同。此外,第二实施方式所涉及的半导体模块1的存储器衬底10具有柱(pillar)31来代替凸块30,在这方面与第一实施方式不同。
封装衬底70例如为硅衬底或有机衬底。封装衬底70具有比存储器衬底 10更大的面积而构成。封装衬底70具有在厚度方向上贯通的、或者形成电连接路径的封装电极71。此外,封装衬底70在一端面与存储器衬底10相向,在另一端面具有露出的与封装电极71接触的焊球80。
密封部90对存储器衬底10和封装衬底70之间进行密封。具体而言,密封部90对与存储器衬底10的配置面相反的面和封装衬底70的一端面之间进行密封。
柱31例如为铜柱。在柱31的顶端部配置例如焊料,将存储器衬底10的电源电路12和封装衬底70的封装电极71之间导通。
接下来,对本实施方式的半导体模块1的制造方法进行说明。
在第一实施方式制造的半导体模块1中,将凸块30变更为柱31形成。然后,柱31与封装衬底70的封装电极71对齐,通过柱31的顶端部的焊料与封装电极71导通,然后由密封部90密封。由此,制造本实施方式的半导体模块 1。
根据如上的第二实施方式所涉及的半导体模块1及其制造方法,起到以下的效果。
(9)半导体模块1还具有封装衬底70和密封部90。由此,能够提供操作性好的半导体模块1。例如,通过采用依据JDEC(JEDEC Solid State Technology Association,JEDEC固态技术协会)的布局,能够提供通用性高的半导体模块1。
[第三实施方式]
接下来,使用图9和图10对本发明的第三实施方式所涉及的DIMM模块 100及其制造方法进行说明。
第三实施方式所涉及的DIMM模块100除了具有第一和第二实施方式的多个半导体模块1以外,还具有DIMM衬底101和散热器102。此外,第三实施方式所涉及的DIMM模块100的制造方法除了具有第一和第二实施方式的半导体模块1的制造方法以外,还具有载置工序和散热器配置工序。
如图9所示,DIMM衬底101在至少一个面即载置面载置多个半导体模块 1。在本实施方式中,DIMM衬底101载置八个半导体模块1。
如图10所示,散热器102为具有能够横跨DIMM衬底101所载置着的半导体模块1配置的面积的板状体。散热器102横跨多个半导体模块1的各个存储器单元20地配置,并且与粘接层40接触地配置。
接下来,对本实施方式所涉及的DIMM模块100的制造方法进行说明。
在载置工序中,在DIMM衬底101的至少一个面即载置面载置多个已制造的半导体模块1。在本实施方式中,在载置工序中,半导体模块1在DIMM 衬底101的一个面上空开规定的间隔直线状地配置。
接下来,实施散热器配置工序。在散热器配置工序中,横跨多个半导体模块1的各个存储器单元20并与粘接层40接触地配置散热器102。
接下来,对DIMM模块100的一例进行说明。
当使存储器芯片21的芯片厚度为10μm~20μm、一个存储器单元20中的存储器芯片21的层叠数为四片、粘接层40的厚度为20μm~50μm、粘接多个存储器单元20后的厚度最大为5mm时,存储器单元20向半导体模块1的搭载数为83个单元~38个单元,换算成存储器芯片21的搭载片数为332片~152 片,能够使用2GB(16Gb)的芯片实现664GB~304GB的存储器容量。具有八个半导体模块1的DIMM模块100能够实现5312GB~2432GB的存储器容量。
根据如上的第三实施方式所涉及的半导体模块1及其制造方法,起到以下的效果。
(10)DIMM模块100具有:上述的多个半导体模块1;DIMM衬底101,其在至少一个面即载置面载置多个半导体模块1;以及散热器102,其横跨多个半导体模块1的各个存储器单元20地配置,并且与粘接层40接触地配置。由此,能够实现大容量的存储器模块。此外,通过使散热器102与粘接层40 接触地配置,能够提供冷却效果更好的DIMM模块100。
(11)DIMM模块100的制造方法具有:上述的半导体模块1的制造方法;载置工序,在DIMM衬底101的至少一个面即载置面载置多个已制造的半导体模块1;以及散热器配置工序,横跨多个半导体模块1的各个存储器单元20 并与粘接层40接触地配置散热器102。由此,能够制造大容量且冷却效果好的存储器模块。
以上,对本发明的半导体模块1、DIMM模块100及其制造方法的优选的各实施方式进行了说明,但本发明不限于上述的实施方式,能够酌情变更。
例如,在上述实施方式中,半导体模块1也可以仅具有一个存储器单元 20。在该情况下,半导体模块1也可以不具有粘接层40。
此外,在上述第二实施方式中,如图11所示,存储器衬底10也可以具有配置在配置面的电源电路12和用于引线接合的引线W来代替在厚度方向上贯通的电极。与此相伴,存储器衬底10也可以不具有柱31。此外,半导体模块 1也可以不具有密封材料。在该情况下,存储器衬底10和封装衬底70直接连接。由此,因为不需要在厚度方向上贯通存储器衬底10的电源电极,所以能够抑制制造成本。
此外,在上述各实施方式中,如图6所示,在连接部形成工序中,在电极层23的面内方向一端(一侧面)形成连接部50,但不限于此。在连接部形成工序中,连接部50也可以形成在存储器衬底10的电源电路12的露出面。而且,在配置工序中,也可以配置成电极层23的面内方向一端(一侧面)与连接部50接触。由此,存储器芯片21也可以配置在存储器衬底10。
附图标记说明
1:半导体模块
10:存储器衬底
11:通信电路
12:电源电路
20:存储器单元
21:存储器芯片
22:贯通电极
23:电极层
30:凸块
40:粘接层
50:连接部
60:贴装部
70:封装衬底
71:封装电极
80:焊球
90:密封部
100:DIMM模块
101:DIMM衬底
102:散热器
121:通信部
D:层叠方向
Claims (11)
1.一种半导体模块,具有多个存储器芯片,所述半导体模块具有:
存储器衬底,其将一个面作为配置面,具有露出到所述配置面的电源电路;以及
至少一个存储器单元,其配置在所述存储器衬底的配置面,
所述存储器单元具有:
多个存储器芯片,其将层叠方向沿着所述配置面而配置;
贯通电极,其在层叠方向上贯通多个所述存储器芯片;以及
电极层,其层叠在配置于层叠方向一端面的所述存储器芯片,与所述贯通电极和所述电源电路连接,
所述存储器芯片在与所述存储器衬底邻接的一端部具有能够与所述存储器衬底的通信电路通信的通信部。
2.根据权利要求1所述的半导体模块,其还具有:
粘接层,其配置在邻接的一对存储器单元之间,与至少一个所述存储器单元的所述电极层接触。
3.根据权利要求2所述的半导体模块,其还具有:
连接部,其配置在所述电极层的面内方向一端和所述电源电路之间,将所述电极层和所述电源电路电连接。
4.根据权利要求3所述的半导体模块,其还具有:
贴装部,其配置在所述通信部和所述通信电路之间,将所述存储器单元贴装在所述存储器衬底的配置面。
5.一种DIMM模块,其具有:
多个半导体模块,所述半导体模块是权利要求1至4中任一项所述的半导体模块;以及
DIMM衬底,其将至少一个面作为载置面,载置多个所述半导体模块。
6.一种DIMM模块,其具有:
多个半导体模块,所述半导体模块是权利要求2至4中任一项所述的半导体模块;
DIMM衬底,其将至少一个面作为载置面,在所述载置面载置多个所述半导体模块;以及
散热器,其横跨多个所述半导体模块的各个存储器单元地配置,并且与所述粘接层接触地配置。
7.一种半导体模块的制造方法,所述半导体模块具有多个存储器芯片,所述半导体模块的制造方法具有:
存储器单元形成工序,层叠所述存储器芯片,并且形成贯通所述存储器芯片的贯通电极和配置在所述存储器芯片的层叠方向的一端面的电极层,从而形成存储器单元;
存储器芯片配置工序,将所述存储器芯片配置在存储器衬底,所述存储器衬底具有露出到一个面即配置面的电源电路,所述存储器芯片配置工序将所述电极层的面内方向一端和所述电源电路相向配置;以及
连接工序,对于所述存储器衬底电连接所述存储器单元,
在所述存储器芯片配置工序中,使通信部与所述存储器衬底邻接,所述通信部设在所述存储器芯片的面内方向一端部,能够与所述存储器衬底的通信电路通信。
8.根据权利要求7所述的半导体模块的制造方法,其还具有:
粘接层形成工序,在所述存储器单元形成工序之后、所述存储器芯片配置工序之前,形成粘接层,所述粘接层用于将其他所述存储器单元粘接在所述存储器单元的所述电极层的层叠方向的一个面;以及
粘接工序,在所述粘接层形成工序之后、所述存储器芯片配置工序之前,使用所述粘接层粘接两个所述存储器单元。
9.根据权利要求8所述的半导体模块的制造方法,其还具有:
单片化工序,在所述存储器单元形成工序之后、所述粘接层形成工序之前,对所述存储器单元进行单片化。
10.一种DIMM模块的制造方法,其具有:
权利要求8或9中任一项所述的半导体模块的制造方法;以及
载置工序,将DIMM衬底的至少一个面作为载置面,在所述载置面载置多个已制造的所述半导体模块。
11.一种DIMM模块的制造方法,其具有:
权利要求8或9所述的半导体模块的制造方法;
载置工序,将DIMM衬底的至少一个面作为载置面,在所述载置面载置多个已制造的所述半导体模块;以及
散热器配置工序,横跨多个所述半导体模块的各个存储器单元并与所述粘接层接触地配置散热器。
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