CN110720125B - 半导体模块 - Google Patents

半导体模块 Download PDF

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Publication number
CN110720125B
CN110720125B CN201780091509.3A CN201780091509A CN110720125B CN 110720125 B CN110720125 B CN 110720125B CN 201780091509 A CN201780091509 A CN 201780091509A CN 110720125 B CN110720125 B CN 110720125B
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Prior art keywords
ram
interposer
semiconductor module
pair
unit
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CN201780091509.3A
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CN110720125A (zh
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泷下隆治
安达隆郎
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Ultramemory Inc
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Ultramemory Inc
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Priority to CN202110068074.9A priority Critical patent/CN112802835A/zh
Publication of CN110720125A publication Critical patent/CN110720125A/zh
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    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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Abstract

本发明提供一种能够提高逻辑芯片和RAM间的带宽(bandwidth)的半导体模块。半导体模块(1)具有逻辑芯片、分别由层叠型RAM模块构成的一对RAM部(30)、使逻辑芯片与一对RAM部(30)分别电连接的第一中介层(10)、将逻辑芯片与一对RAM部(30)之间分别以能够通信的方式连接的连接部(40)，一个RAM部(30a)载置在第一中介层(10)，其一端部隔着连接部(40)与逻辑芯片的一端部在层叠方向(C)重叠配置，另一个RAM部(30b)隔着连接部(40)与一个RAM部(30a)重合，并沿逻辑芯片的外周配置。

Description

半导体模块
技术领域
本发明涉及一种半导体模块。
背景技术
以往，作为存储装置已知有DRAM(Dynamic Random Access Memory：动态随机访问存储器)等易失性存储器(RAM)。DRAM追求运算装置(以下称逻辑芯片)的高性能化、能够应对数据量的增大的大容量化。因此，通过存储器(存储器单元阵列、存储器芯片)的微型化和平面方向地增设单元来实现大容量化。另一方面，由于微型化所带来的对于噪声的薄弱性、晶模面积的增加等，此类大容量化已达极限。
因此，近年来开发了通过将平面的存储器层叠多个进行3维化(3D化)来实现大容量化的技术。另外，提出了通过将逻辑芯片和RAM重叠配置，将逻辑芯片和RAM的设置面积减小的半导体模块(例如，参考专利文献1～4)。
现有技术文献
专利文献
专利文献1：日本特表2014-512691号公报；
专利文献2：日本特表2013-501380号公报；
专利文献3：日本特开2010-232659号公报；
专利文献4：日本特开2010-80802号公报。
发明要解决的问题
然而，由于逻辑芯片的高性能化、数据量的增大，除了大容量化还要求逻辑芯片和RAM间的通信速度的提升。因此，期望能够提供一种能够增加逻辑芯片和RAM间的带宽(bandwidth)的半导体模块。
本发明的目的在于提供一种能够增加逻辑芯片以及RAM间的带宽(bandwidth)的半导体模块。
发明内容
本发明涉及一种半导体模块，其特征在于，具有：逻辑芯片；一对RAM部，其分别由层叠型RAM模块构成；第一中介层，其将所述逻辑芯片与一对所述RAM部分别电连接；连接部，其将所述逻辑芯片与一对所述RAM部分别以能够通信的方式连接，一个所述RAM部载置在所述第一中介层，并且其一端部隔着所述连接部与所述逻辑芯片的一端部在层叠方向重叠配置，另一个所述RAM部隔着所述连接部与一个所述RAM部重合，并沿所述逻辑芯片的外周的至少一边配置。
另外，优选一对所述RAM部分别具有层叠了存储器电路的存储器部和在所述存储器部一端侧层叠的接口芯片。
另外，优选在一对所述RAM部中，分别使所述接口芯片相向配置。
另外，优选在一对所述RAM部中，分别在与所述第一中介层相向的面的相反的一面侧配置所述接口芯片。
另外，优选所述另一个RAM部仅由所述存储器部构成。
另外，优选半导体模块进一步具有：第二中介层，其载置于所述另一个RAM部；第三中介层或封装基板，其载置所述第一中介层；键合线，其将所述第二中介层与所述第三中介层或封装基板电连接。
另外，优选半导体模块进一步具有：第二中介层，其载置于所述另一个RAM部；柱状部，其将所述第一中介层与所述第二中介层电连接。
另外，优选还具有在所述另一个RAM部和所述逻辑芯片载置的散热部。
另外，优选所述散热部具有与至少所述另一个RAM部和所述逻辑芯片中任一个相邻的衬垫部。
另外，优选一对所述RAM部分别具有俯视观察时形状及大小相同的层叠型RAM模块。
附图说明
图1是表示本发明的第一实施方式的半导体模块的概要俯视图。
图2是表示第一实施方式的半导体模块的层叠型RAM模块的剖视图。
图3是图1中沿A-A线的剖视图。
图4是第一实施方式半导体模块中安装了散热部的剖视图。
图5是表示第一实施方式的半导体模块中的电源供给和数据通信的流动的概念图。
图6是表示本发明的第二实施方式的半导体模块的剖视图。
图7是表示第二实施方式的半导体模块中的电源供给和数据通信的流动的概念图。
图8是表示本发明的第三实施方式的半导体模块的剖视图。
图9是表示第三实施方式的半导体模块中的电源供给和数据通信的流动的概念图。
图10是表示本发明的第四实施方式的半导体模块的概要俯视图。
图11是图10中沿B-B线的剖视图。
图12是图11的RAM部的局部放大图。
图13是表示第四实施方式的半导体模块中的电源供给和数据通信的流动的概念图。
图14是表示本发明的第五实施方式的半导体模块的剖视图。
具体实施方式
以下，参考附图对本发明的半导体模块的各实施方式进行说明。
各实施方式的半导体模块是例如将运算装置(以下称逻辑芯片)和层叠型RAM配置在中介层上的SIP(system in a package：系统级封装)。半导体模块配置在其它的中介层上，并使用微凸点进行电连接。半导体模块是能够从其它的中介层获得电源并且在与其它的中介层之间进行数据发送接收的装置。并且，在以下的实施方式中，将MPU作为逻辑芯片的一例进行说明。
[第一实施方式]
接下来，参考图1～图5对本发明的第一实施方式中的半导体模块1进行说明。
如图1～图4所示，半导体模块1具有第一中介层10、MPU20、一对RAM部30、连接部40和散热部50。
如图1和图3所示，第一中介层10是俯视观察时呈矩形的板状体，在其内部形成有电路。第一中介层10与后述的MPU20以及一对RAM部30的分别电连接。第一中介层10配置在其它的中介层或封装基板(未图示)上，一侧的面(下表面)例如使用微凸点M1与其它的中介层或封装基板电连接。并且，下文中将第一中介层10的厚度方向作为层叠方向C进行说明。另外，将层叠方向C中从第一中介层10朝向其它的中介层或封装基板的方向作为下方进行说明。另外，将层叠方向C中与下方相反的方向作为上方进行说明。
MPU20是俯视观察时呈矩形的板状体。如图3所示，MPU20的下表面侧配置有作为电源端子、通信端子和接地端子发挥功能的电路面21。MPU20的电路面21经由在第一中介层10上表面构成的柱P(例如Cu柱)与第一中介层10电连接。
一对RAM部30分别由俯视观察时呈矩形的层叠型RAM模块构成。一对RAM部30例如分别由层叠型DRAM模块构成。如图1所示，一对RAM部30配置在第一中介层10的上表面，虽未特别限制，以包围MPU20的方式配置。本实施方式中，虽未特别限制，一对RAM部30配置8个，在MPU20的每条边各配置2组。一对RAM部30分别具备俯视观察时形状大小相同的层叠型RAM模块。例如，一对RAM部30各自以同一批次制造得来的。
如图3所示，一对RAM部30的一个(以下称一个RAM部30a)载置于第一中介层10。另外，一个RAM部30a的一端部隔着后述的连接部40与MPU20的一端部在层叠方向C重叠配置。具体来说，一个RAM部30a的一端部以介于MPU20的一端部和第一中介层10之间的方式配置。通过将多个该一个RAM部30a配置在第一中介层10上，形成了由多个该一个RAM部30a包围的矩形区域。由一个RAM部30a形成的矩形区域形成为比MPU20的下表面的面积小的面积。一个RAM部30a中与第一中介层10的上表面
相向的下表面使用微凸点M2与第一中介层10电连接。
如图1和图3所示，一对RAM部30的另一个(以下称另一个RAM部30b)隔着后述的连接部40与一个RAM部30a重叠接合。另外，另一个RAM部30b沿MPU20的外周配置。即，另一个RAM部30b与MPU20相邻配置，与层叠方向C垂直的一个端面(一个侧面)与MPU20的一个侧面相向配置。
通过多个该另一个RAM部30b配置在一个RAM部30a上，形成了由多个该另一个RAM部30b包围的矩形区域。由另一个RAM部30b形成的矩形区域形成为MPU20的下表面的面积以上的面积。即，另一个RAM部30b在偏移了与MPU20重合的一个RAM部30a的重叠宽度L(介于第一中介层10和MPU20之间的一个RAM部30a的一端部的进入的长度)以上的状态下与一个RAM部30a重叠接合。由此，另一个RAM部30b被配置为从与一个RAM部30a的一端部相反一侧的另一端的边缘以重叠宽度L以上的距离突出。
如图2所示，以上的一对RAM部30分别具有存储器部31和接口芯片32。本实施方式中，一对RAM部30分别在与第一中介层10相向的面(下表面)相反的面(上表面)侧配置后述的接口芯片32。即，一个RAM部30a的后述接口芯片32经由后述连接部40与MPU20的电路面21相向配置。另外，另一个RAM部30b的后述接口芯片32配置在与后述连接部40相向的面(下表面)相反的面(上表面)侧。
存储器部31形成为俯视观察时呈矩形的板状体，层叠存储器电路33a地形成。具体来说，关于存储器部31，在上表面具有存储器电路33a的俯视观察时呈矩形的板状体的晶模33b在层叠方向C层叠地形成。晶模33b是内部形成有电路的Si基板，层叠的晶模33b分别与相邻的晶模33b电连接。将层叠的晶模33b间连接的电源端子和接地端子例如由无凸点TSV形成，信号线由TCI(ThruChip Interface：经芯片接口)形成。
接口芯片32形成为俯视观察时呈矩形的板状体。接口芯片32层叠在存储器部31的一端侧(上表面侧)。具体来说，接口芯片32层叠在层叠方向C最上方层叠的晶模33b的存储器电路33a上。在接口芯片32的上表面形成有用于通信的通信电路32a。将接口芯片32与存储器部31间连接的电源端子和接地端子例如由无凸点TSV形成，信号线由TCI形成。
连接部40是将MPU20与一对RAM部30分别连接的通信接口，例如形成为层状。连接部40将MPU20与一对RAM部30间连接以能够通信。即，MPU20和一对RAM部30间连接为可通信。连接部40配置在与一个RAM部30a的面中载置于第一中介层10的面(下表面)相反的面(上表面)。即，在连接部40中，一部分被一对RAM部30夹住配置，另一部分被一个RAM部30a和MPU20夹住配置。连接部40例如是各向异性导电膜(ACF)，作为电源端子和信号线的发挥功能。
如图4所示，散热部50载置在另一个RAM部30b和MPU20。即，散热部50遍及另一个RAM部30b和MPU20地配置。本实施方式中，散热部50配置成覆盖另一个RAM部30b和MPU20的上表面(与第一中介层10相向的面相反的面)。也可以构成为在散热部50和另一个RAM部30b和MPU20之间夹有热传导率高的软膏、粘合剂或其它板状物质。
接下来对半导体模块1的运作进行说明。
首先，如图5所示，从第一中介层10向MPU20供给电源W1。另外，从第一中介层10向一个RAM部30a供给电源W2。向一个RAM部30a供给的电源W1也经由连接部40供给至另一个RAM部30b。另外，MPU20与第一中介层10接地连接(接地G1)。一对RAM部30与第一中介层10接地连接(接地G2)。并且，也可以经由连接部40从接口芯片32向MPU20供给电源W4和接地G4。
在向一对RAM部30存储数据的情况下，首先，从第一中介层10向MPU20发送数据D1。MPU20将基于数据D1进行运算的运算结果作为存储信号(数据D2)向一对RAM部30发送。即，从MPU20发送的存储信号通过MPU20的电路面21和连接部40而被发送至一个RAM部30a的接口芯片32。
接口芯片32基于存储信号中包含的地址，将存储信号中包含的数据存储在存储器部31(数据D3)。此时接口芯片32对另一个RAM部30b进行控制。即，在存储信号中包含的地址被包含于另一个RAM部30b中的情况下，接口芯片32将包含于存储信号中的数据存储在另一个RAM部30b中对应的地址。
另一方面，在从一对RAM部30加载数据的情况下，首先，从第一中介层10向MPU20发送加载信号(数据D6)。即，从MPU20发送的加载信号通过MPU20的电路面21和连接部40被发送至一个RAM部30a的接口芯片32。
接口芯片32基于加载信号中包含的地址，从存储器部31中相应的地址加载数据(数据D5)。此时，接口芯片32对另一个RAM部30b也进行控制。即，在加载信号中包含的地址被包含在另一个RAM部30b中的情况下，接口芯片32从另一个RAM部30b的相应的地址加载数据。接口芯片32将加载的数据通过连接部40发送给MPU20(数据D4)。
根据如上所述的第一实施方式的半导体模块1，具有以下效果。
(1)将半导体模块1构成为，包含MPU20(逻辑芯片)、分别由层叠型RAM模块构成的一对RAM部30、将MPU20与一对RAM部30分别电连接的第一中介层10、将MPU20与一对RAM部30分别连接以能够通信的连接部40。并且，将一对RAM部30的一个一端部隔着连接部40与MPU20的一端部在层叠方向C上重叠配置，将一对RAM部30的另一个隔着连接部40与一个RAM部30a重合，并且沿MPU20的外周的至少一边配置。由此，能够经由连接部40将MPU20与一对RAM部30分别直接地连接，所以能够缩短一对RAM部30的每个与MPU20间的信号线。由此，能够扩大MPU20与一对RAM部30间的带宽。另外，通过以层叠型RAM模块将RAM部30构成为一对，能够容易地使RAM部30的容量增加。进而，能够分别制作层叠型RAM模块，与以单体的层叠型RAM模块制作RAM部30的情况相比，能够提高良品率。
(2)将一对RAM部30分别构成为，包含存储器电路33a层叠而成的存储器部31、在存储器部31一端侧层叠的接口芯片32。由此，能够使用接口芯片32来控制存储器部31。由此，能够恰当地控制存储器部31。
(3)在一对RAM部30中，分别在与第一中介层10相向的面相反的面侧配置接口芯片32。由此，能够无需改变RAM部30的层叠方向的朝向地进行配置，所以提高了制作的容易性。
(4)将半导体模块1进一步构成为，包含载置在另一个RAM部30b和MPU20的散热部50。由此，能够效率地从RAM部30和MPU20的双方进行散热。
(5)将一对RAM部30分别构成为，包含俯视观察时形状大小相同的层叠型RAM模块。由此，能够不必以单独的规格制作与一对RAM部30中每一个对应的层叠型RAM模块，所以能够降低制作成本。
(6)经由连接部40从接口芯片32向MPU20供给电源W4和接地G4。由此，能够向驱动接口芯片32和MPU20间的信号线的驱动电路供给共通的电源，能够有效地抑制因电源噪声的相位偏移引起的误动作。
[第二实施方式]
接下来，参考图6～图7对本发明的第二实施方式的半导体模块1A进行说明。在对第二实施方式的说明中，对相同构成要素赋予相同符号，省略或简略化其说明。
如图6所示，第二实施方式的半导体模块1A在一对RAM部30分别与接口芯片32相向配置这一点上与第一实施方式不同。如图7所示，在第二实施方式的半导体模块1A中，一个RAM部30a的接口芯片32与另一个RAM部30b各自的接口芯片32对各RAM部30的存储器部31进行管理，这一点与第一实施方式不同。
根据如上所述的第二实施方式的半导体模块1A，具有以下效果。
(7)在一对RAM部30中，分别使接口芯片32相向配置。由此，能够通过独立的接口芯片32控制各一对RAM部30。
[第三实施方式]
接下来，参考图8以及图9对本发明的第三实施方式的半导体模块1B进行说明。在对第三实施方式的说明中，对相同构成要素赋予相同符号，将省略或简略化其说明。
如图8所示，第三实施方式的半导体模块1B在另一个RAM部30b仅由存储器部31构成这一点上与第一和第二实施方式不同。如图9所示，在第三实施方式的半导体模块1B中，与第一实施方式同样地一个RAM部30a的接口芯片32对一对RAM部30的双方进行管理。
根据如上所述的第三实施方式的半导体模块1B，达到以下效果。
(8)将另一个RAM部30b仅由存储器部31构成。由此，能够提高半导体模块1B的良品率，同时可以降低制作成本。
[第四实施方式]
接下来，参考图10～图13对本发明的第四实施方式的半导体模块1C进行说明。在对第四实施方式的说明中，对相同构成要素赋予相同符号，省略或简略化其说明。
如图10～图12所示，第四实施方式的半导体模块1C在具有第二中介层60、第三中介层或封装基板80和键合线70这一点上与第二实施方式不同。
第二中介层60形成为俯视观察时呈矩形。第二中介层60例如载置在另一个RAM部30b上，使用微凸点M3与另一个RAM部30b电连接。本实施方式中，第二中介层60形成为在俯视观察时与另一个RAM部30b大致相同的形状以及大小。
第三中介层或封装基板80载置第一中介层10。第三中介层或封装基板80使用微凸点M1与第一中介层10电连接。
键合线70配置为用于向另一个RAM部30b供给电源W3和接地G3。键合线70的一端使用结合区等与第三中介层或封装基板80连接，另一端使用结合区等与第二中介层60连接。
接下来对半导体模块1C的动作进行说明。
如图13所示，针对第二中介层60，经由键合线70从第三中介层或封装基板80供给电源W3。从第二中介层60供给电源W3至另一个RAM部30b。另一个RAM部30b与第二中介层60接地(接地G3)。
根据如上所述的第四实施方式的半导体模块1C，达到以下效果。
(9)将半导体模块1C进一步构成为，包含载置在另一个RAM部30b的第二中介层60、载置第一中介层10的第三中介层或封装基板80、以及将第二中介层60与第三中介层或封装基板80电连接的键合线70。由此，能够独立地向一对RAM部30的每个供电，能够稳定地对RAM部30供电。
[第五实施方式]
接下来，参考图14对本发明的第五实施方式的半导体模块1D进行说明。在对第五实施方式的说明中，对相同构成要素赋予相同符号，省略或简略化其说明。
如图14所示，第五实施方式的半导体模块1D在取代键合线70而具有导电性的柱状部90这一点上与第五实施方式不同。
柱状部90例如是Cu柱，配置成为用于向另一个RAM部30b供给电源W5和接地G5。柱状部90的一端与第一中介层10的上表面连接，另一端与第二中介层60的下表面连接。柱状部90沿着第二中介层60的下表面4边中距MPU20最远位置的边而配置有多根。换言之，柱状部90沿第二中介层60的下表面的沿MPU20的外周配置的2边中较远侧的边而配置有多根。本实施方式中，柱状部90在每一对RAM部30(第二中介层60)配置6根。
接下来对半导体模块1D的动作进行说明。
如图14所示，针对第二中介层60，经由柱状部90从第一中介层10供给电源W5。另外，第二中介层60与第一中介层10接地(接地G5)。
根据如上所述的第五实施方式的半导体模块1D，达到以下效果。
(10)将半导体模块1D进一步构成为，包含在另一个RAM部30b载置的第二中介层60、将第一中介层10与第二中介层60电连接的柱状部90。由此，能够独立地对一对RAM部30的每一个供电，因此能够稳定地对RAM部30供电。另外，由于柱状部90的另一端与另一个RAM部30b相对的第二中介层60的下表面连接，所以能够在第二中介层60的下表面侧配置柱状部90的连接位置和另一个RAM部30b的连接位置这两者。由此，能够无需使第二中介层60贯通地从柱状部90向另一个RAM部30b供给电源(电源W3、W5)和接地(接地G3、G5)，因此能够使半导体模块1D的制作成本降低。
[第六实施方式]
接下来，对本发明的第六实施方式的半导体模块进行说明。在对第六实施方式的说明中，对相同构成要素赋予相同符号，省略或简略化其说明。
第五实施方式的半导体模块在散热部50具有衬垫部(未图示)这一点上与第一～第五实施方式不同。
在MPU20的上表面和另一个RAM部30b的上表面间存在高低差时，衬垫部形成为填补高低差的厚度。衬垫部至少与另一个的RAM部30b和MPU20中任意一个相邻。衬垫部以平面形成相对面，以能够与另一个RAM部30b或MPU20的上表面接触。
根据如上所述的第六实施方式的半导体模块，达到以下效果。
(11)散热部构成为包含至少与另一个的RAM部30b以及MPU20中任意一个相邻的衬垫部。由此，即便是在RAM部和MPU20间不共面的情况，也可以设置散热部。
以上虽然是对本发明的半导体模块所优选的各实施方式进行说明，但是本发明并不限于所述的实施方式，能够进行适宜地变更。
例如，所述实施方式中，将对层叠的晶模33b间进行连接的电源端子和接地端子作为无凸点TSV，信号线作为TCI。另外，虽然将对接口芯片32与存储器部31间进行连接的电源端子和接地端子的组合作为无凸点TSV，信号线作为TCI，但对此没有限定。例如，可以设为以下表1中示出的组合。
表1
RAM部层叠方向电源端子 RAM部层叠方向信号线
1 无凸点TSV TCI
2 无凸点TSV TSV+Hybrid Bonding
3 无凸点TSV 无凸点TSV
4 TSV+Hybrid Bonding TCI
5 TSV+Hybrid Bonding TSV+Hybrid Bonding
6 TSV+Hybrid Bonding 无凸点TSV
7 ACF TCI
8 ACF ACF
另外，TCI是ThruChipInterface的缩写。
另外，所述实施方式中，虽然将连接部40作为ACF，但对此没有限定。例如，可以将连接部40依照以下表2构成。
表2
Figure BDA0002298541750000121
另外，所述第四实施方式中，散热部50也可以不与键合线70和第二中介层60的连接部分重叠的大小来形成。作为其它的变形例，散热部50为比从第二中介层60起的键合线70的高度高的高度，也可以具有不与键合线70和第二中介层60的连接部分重叠的大小的衬垫部。
另外，所述实施方式中，虽然从第一中介层10向MPU20和一对RAM部30供给电源W1、W2，但对此没有限定。例如，如图5所示，也可以从MPU20供给电源W4和接地G4，相反地，也可以从一对RAM部30供给电源W4和接地G4。
另外，运算装置并不限定是MPU，可以广泛地应用于全体逻辑芯片，存储器并不限定是DRAM，可以广泛地应用包括非易失性RAM(例如MRAM、ReRAM、FeRAM等)的全体RAM(Random Access Memory)。
附图标记说明
1，1A，1B，1C，1D：半导体模块；
10：第一中介层；
20：MPU；
30：一对RAM部；
30a：一个RAM部；
30b：另一个RAM部；
31：存储器部；
32：接口芯片；
40：连接部；
50：散热部；
60：第二中介层；
70：键合线；
80：第三中介层或封装基板。

Claims (10)

1.一种半导体模块，其特征在于，具有：
逻辑芯片；
一对RAM部，其分别由层叠型RAM模块构成；
第一中介层，其将所述逻辑芯片与一对所述RAM部分别电连接；
连接部，其将所述逻辑芯片与一对所述RAM部之间分别以能够通信的方式连接，
一个所述RAM部载置在所述第一中介层，并且其一端部隔着所述连接部与所述逻辑芯片的一端部在层叠方向重叠配置，
另一个所述RAM部隔着所述连接部与一个所述RAM部重合，并沿所述逻辑芯片的外周的至少一边配置。
2.根据权利要求1所述的半导体模块，其中，
一对所述RAM部分别具有：
存储器部，其具有被层叠了的存储器电路；以及
接口芯片，其层叠在所述存储器部的一端侧。
3.根据权利要求2所述的半导体模块，其中，
一对所述RAM部被配置成相互地使所述接口芯片相向。
4.根据权利要求2所述的半导体模块，其中，
在一对所述RAM部中，分别在与所述第一中介层相向的面的相反的一面侧配置所述接口芯片。
5.根据权利要求2所述的半导体模块，其中，
另一个所述RAM部仅由所述存储器部构成。
6.根据权利要求1至5中任一项所述的半导体模块，还具有：
第二中介层，其载置于另一个所述RAM部；
第三中介层或封装基板，其载置所述第一中介层；
键合线，其将所述第二中介层与所述第三中介层或封装基板电连接。
7.根据权利要求1至5中任一项所述的半导体模块，还具有：
第二中介层，其载置于另一个所述RAM部；
柱状部，其将所述第一中介层与所述第二中介层电连接。
8.根据权利要求1中所述的半导体模块，还具有：
散热部，其载置于另一个所述RAM部和所述逻辑芯片。
9.根据权利要求8所述的半导体模块，其中
所述散热部具有至少与另一个所述RAM部和所述逻辑芯片中任意一方相邻的衬垫部。
10.根据权利要求1中所述的半导体模块，其中
一个所述RAM部和另一个所述RAM部包含俯视观察时形状及大小相同的层叠型RAM模块。
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CN101159311A (zh) * 2006-10-04 2008-04-09 海力士半导体有限公司 非易失性存储器件及其制造方法
JP2008251917A (ja) * 2007-03-30 2008-10-16 Renesas Technology Corp 半導体装置

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