CN102044452A - 层迭封装堆栈式集成电路封装系统及其制造方法 - Google Patents

层迭封装堆栈式集成电路封装系统及其制造方法 Download PDF

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Publication number
CN102044452A
CN102044452A CN2010105161016A CN201010516101A CN102044452A CN 102044452 A CN102044452 A CN 102044452A CN 2010105161016 A CN2010105161016 A CN 2010105161016A CN 201010516101 A CN201010516101 A CN 201010516101A CN 102044452 A CN102044452 A CN 102044452A
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integrated circuit
silicon
encapsulation
storehouse
hole
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CN102044452B (zh
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朴炯相
梁悳景
崔大植
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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SMITH WAFER PACKAGE CORP
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
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Abstract

本发明涉及一种层迭封装堆栈式集成电路封装系统及其制造方法。该集成电路封装系统的制造方法包含以下步骤：形成顶部封装，包含：提供具有硅通孔的硅通孔插入件，将堆栈集成电路裸片耦合至该硅通孔并测试顶部封装；形成基部封装，包含：提供衬底，将基部集成电路裸片耦合至该衬底并测试基部封装；以及，在该顶部封装与该基部封装之间耦合堆栈互连。

Description

层迭封装堆栈式集成电路封装系统及其制造方法
技术领域
本发明大致涉及集成电路封装系统，且尤其涉及层迭封装(package-on-package)堆栈的系统。
背景技术
为了形成当前的半导体封装而将半导体芯片接置在衬底(substrate)或插入件(interposer)时，该衬底或插入件通常由塑料材料或陶瓷材料制成。该些材料尤其优先使用于芯片组装技术采用倒装芯片(flip-chip)方法的情况，该倒装芯片方法利用焊球(solder ball)建立芯片与衬底/插入件之间的电性连接。当后续在封装上施加大幅波动的温度或湿度的情况下使用或测试该已组装的器件时，可能会出现显着的失效率(failure rate)，特征为破裂(crack)，尤其是在焊点(solder joint)处破裂，以及封装元件脱层(delamination)。
出于缩小如手持电话的电子产品中组装半导体器件所需的板面积的考虑，当前的半导体器件经常在封装中使用垂直堆栈芯片。该芯片堆栈往往包含尺寸显着不同的芯片，并且通常利用引线键合(wirebonding)技术组装至由塑料或陶瓷材料制成的插入件上。随后，将该插入件上的堆栈组装至衬底上，该衬底具有焊球，以供与外部元件互连。在温度循环和高湿度情况下针对该器件观察发现，由于焊点破裂或元件脱层而造成的可靠性失效率特别高。
为了将集成电路接合至其它电路，通常将该集成电路接置在引线框架(lead frame)或衬底上。各集成电路都具有焊垫(bonding pad)，分别通过极细的金线或铝线连接至引线框架的引脚指垫(lead fingerpad)。接着在模塑塑料或陶瓷体中分别囊装(encapsulate)该些元件，从而形成集成电路封装。
随着集成电路封装技术的发展，单一电路板或衬底上接置的集成电路数目不断增加。新的封装设计在形状因子(form factor)上，例如集成电路的物理尺寸或形状上，更为紧凑，并显着提高了集成电路的总体密度。不过，集成电路密度一直受限于衬底上可用于接置各集成电路的“实际空间(real estate)”。更大型形状因子的系统，例如个人电脑、计算服务器、以及存储服务器在相同或更小的“实际空间”中需要更多的集成电路。更为严重的是，对便携式个人电子设备，例如手机、数码相机、音乐播放器、个人数字助理(PDA)以及基于位置器件的需求进一步推动了对集成电路密度的需求。
集成电路密度的增加促进了多芯片封装的发展，该多芯片封装中可封装有多个集成电路。各封装向各集成电路提供机械支持，并提供一层或多层互连线，以将该些集成电路电性连接至周围电路。目前的多芯片封装，通常也称作多芯片模块(multi-chip module)，通常包括PCB衬底，其上直接接置一组独立集成电路元件。已发现这样的多芯片封装增加了集成电路密度、促进了集成电路的微型化、提升了信号传播速度、降低了集成电路的总体尺寸和重量、改善了性能并降低了成本-即计算器产业的全部主要目标。
无论是垂直布局或是水平布局的多芯片封装都存在问题，因为它们通常必须在集成电路和集成电路连接能够测试之前预先组装好。因此，当在多芯片模组中接置并连接集成电路时，无法单独测试各集成电路和连接，并且在组装进大型电路之前无法识别确认好的裸片(known-good-die；KGD)。因此，该无法识别确认好的裸片的制造工艺不太可靠并且更容易产生组装缺陷。
而且，典型多芯片封装中，垂直堆栈集成电路出现的问题超过水平布局集成电路封装的问题，从而使得制造工艺更加复杂化。因此更加难以测试并确定各集成电路的实际失效模式。此外，在组装或测试期间，衬底和集成电路经常被损坏，从而使制造工艺复杂化并增加了成本。该垂直堆栈集成电路存在的问题多于其优点。
封装堆栈还存在设计局限。在许多堆栈结构中，顶部封装在中心区域不能够有系统互连，因为该区域通常被下层器件的塑料封装罩体占用。为追求更多的集成功能，该局限可能阻碍使用该封装类型的设计。长期以来，封装重叠一直是额外互连的障碍，它在围绕封装外部具有大量互连的器件中是个问题。
因此，仍然需要层迭封装堆栈式集成电路封装系统以提供具有高良率(yield)的更小与更可靠的封装。鉴于消费者电子产品日益缩小的尺寸以及在有限空间中对更复杂功能的需求，发现这些问题的答案变得极为迫切。鉴于日益加剧的商业竞争压力以及不断增长的消费者预期和市场上产品差异化的日渐缩小，发现这些问题的答案变得更为迫切。此外，降低成本、提高性能以及应付竞争压力的持续需要更增加了发现上述问题的答案的紧迫性。
长期以来人们一直在试图寻求这些问题的解决方案，但现有发展未给出任何教导或启示的解决方案，因此，上述问题的解决方案一直未能得到解决。
发明内容
本发明提供一种集成电路封装系统的制造方法，包含以下步骤：形成顶部封装，包含：提供具有硅通孔的硅通孔插入件，将堆栈集成电路裸片耦合至该硅通孔并测试该顶部封装；形成基部封装，包含：提供衬底，将基部集成电路裸片耦合至该衬底并测试该基部封装；以及，在该顶部封装与该基部封装之间耦合堆栈互连。
本发明提供一种集成电路封装系统，包含：顶部封装，包含：具有硅通孔的硅通孔插入件，以及，耦合至该硅通孔的堆栈集成电路裸片；形成基部封装，包含：衬底，以及，耦合至该衬底的基部集成电路裸片；以及，在该顶部封装与该基部封装之间的堆栈互连。
在本发明的某些实施例中，在上述步骤或元件之外还可具有其它步骤或元件，或者采用其它步骤或元件替代上述步骤或元件。本领域的技术人员在参照附图并阅读下列详细说明之后将明白所述步骤或元件。
附图说明
图1为本发明第一实施例中层迭封装堆栈式集成电路封装系统的剖视图；
图2为本发明第二实施例中层迭封装堆栈式集成电路封装系统的剖视图；
图3为本发明第三实施例中层迭封装堆栈式集成电路封装系统的剖视图；
图4为本发明第四实施例中层迭封装堆栈式集成电路封装系统的剖视图；
图5为本发明第五实施例中层迭封装堆栈式集成电路封装系统的剖视图；
图6为本发明第六实施例中层迭封装堆栈式集成电路封装系统的剖视图；
图7为本发明第七实施例中层迭封装堆栈式集成电路封装系统的剖视图；
图8为本发明第八实施例中层迭封装堆栈式集成电路封装系统的剖视图；
图9为本发明一实施例中一节硅通孔晶片的剖视图；
图10为处于制造的切单阶段的硅通孔晶片的剖视图；
图11为处于制造的裸片接置阶段的第一顶部封装组件的剖视图；
图12为处于制造的引线键合阶段的第二顶部封装组件的剖视图；
图13为处于制造的分离阶段的第三顶部封装组件的剖视图；
图14为处于制造的模塑阶段的顶部封装阵列的剖视图；
图15为处于制造的切单和接置阶段的上部封装组件的剖视图；
图16为处于制造的互连形成阶段的上部封装阵列的剖视图；
图17为处于制造的完成阶段的集成电路封装系统的阵列的剖视图；
图18为处于制造的裸片接置阶段的硅通孔晶片组件的剖视图；
图19为处于制造的线路固定施加阶段的硅通孔晶片组件的剖视图；
图20为处于制造的切单阶段的硅通孔晶片组件的剖视图；
图21为处于制造的分离阶段的硅通孔晶片的剖视图；
图22为处于制造的模塑阶段的顶部封装阵列的剖视图；
图23为处于制造的接置阶段的上部封装元件的剖视图；
图24为处于制造的互连形成阶段的上部封装元件的剖视图；
图25为处于制造的完成阶段的集成电路封装系统的阵列的剖视图；以及
图26为本发明一实施例中集成电路封装系统的制造方法的流程图。
具体实施方式
下面详细描述实施例以使本领域的技术人员能够制造和使用本发明。应了解，基于本揭露内容可使其它实施例显而易见，并且可作系统、工艺或机械的变化而不背离本发明的范围。
下面的描述中给出诸多特定细节以利于充分理解本发明。不过，显而易见的是，可在不具有这些特定细节的情况下实施本发明。为避免模糊本发明，对一些已知的电路、系统配置和工艺步骤均不作详细揭露。
显示系统实施例的附图是半示意图，并非按比例绘制。更详细地说，为清楚起见，图中对一些尺寸进行放大显示。同样，尽管为描述方便，附图部分的视图通常都显示类似的方位，但图中的此类描述大多是随意的。一般而言，可在任意方位下执行本发明。
出于清楚、简化和便于理解的目的，对于所揭露的具有一些共同特征的多个实施例，彼此类似的特征通常采用类似的参考标记。将实施例编号为第一实施例、第二实施例等仅是出于描述方便的目的，并不具有任何其它意义或意图限制本发明。
需要说明的是，这里将术语“水平”定义为在不考虑方位的情况下，与硅通孔插入件的平面或表面平行的平面。例如术语“垂直”指垂直于所定义的水平的方向。“上方”、“下方”、“底部”、“顶部”、“侧面”(例如“侧壁”中)、“高于”、“低于”、“上面”、“之上”、“下面”等术语都相对所述水平面定义，如附图所示。这里所用的术语“上”指元件之间直接接触而没有任何干预材料。
这里所用的术语“工艺”包含形成所描述结构所需的材料或光阻材料的沉积、图案化、曝光、显影、蚀刻、清洗和/或所述材料或光阻材料的去除等步骤。
现参考图1，图1显示本发明第一实施例中层迭封装堆栈式集成电路封装系统100的剖视图。该层迭封装堆栈式集成电路封装系统100的剖视图描述基部封装102，例如裸片朝上型塑料球栅阵列(plastic ballgrid array；PBGA)，其基部集成电路裸片104接置在衬底108的元件侧106。
衬底108，例如层压衬底或陶瓷衬底，具有系统侧110，通孔112将系统侧110的触点(contact)114耦合至元件侧106的触点114。基部集成电路裸片104可通过粘接剂116，例如裸片附着材料，接置于元件侧106。
电性互连118，例如焊线(bond wire)，可将基部集成电路裸片104耦合至元件侧106的触点114。模塑基部封装体120可囊装基部集成电路裸片104、电性互连118以及部分元件侧106。元件侧106的一些触点114保持外露状态。
可在衬底108的系统侧110的触点114上形成系统互连122，例如焊球(solder ball)、焊料凸块(solder bump)、焊料柱(solder column)或柱形凸块(stud bump)。系统互连122可电性连接至元件侧106的触点114、基部集成电路裸片104或其组合。
顶部封装124可包含堆栈互连126，例如焊球、焊料柱或柱形凸块。硅通孔插入件128，例如具有硅通孔130的集成电路裸片，可耦合至堆栈互连126。硅通孔插入件128可具有作用面(active side)132和背面(back side)134。硅通孔插入件128的作用面132可包含集成电路(未图示)。
堆栈集成电路裸片136可通过粘接剂116接置于作用面132上。电性互连118可将堆栈集成电路裸片136耦合至作用面132上的硅通孔130。最终的电路可电性连接堆栈集成电路裸片136、硅通孔插入件128、基部集成电路裸片104、系统互连122或其组合。
通过模塑环氧模塑化合物(epoxy molding compound)以囊装堆栈集成电路裸片136、电性互连118以及硅通孔插入件128的作用面132和垂直面140，从而形成顶部封装体138。顶部封装体138留下外露的硅通孔插入件128的背面134。
已发现，通过去除在顶部封装124上衬底的必要性，顶部封装124可降低了集成电路封装系统100的厚度。硅通孔插入件128可提供附着表面以将顶部封装124电性连接至其它器件。顶部封装124和基部封装102可在组装之前进行测试，以提升制造良率并降低成本。
堆栈集成电路裸片136和基部集成电路裸片104的数目和位置仅为示例，还可具有其它配置。在各种情况下都可在上述封装内堆栈多个裸片。
现参考图2，图2显示本发明第二实施例中层迭封装堆栈式集成电路封装系统200的剖视图。该集成电路封装系统200的剖视图描述基部封装202，其基部集成电路裸片104接置在衬底108的元件侧106。
衬底108，例如层压衬底或陶瓷衬底，具有系统侧110，通孔112将系统侧110的触点114耦合至元件侧106的触点114。基部集成电路裸片104可通过粘接剂116，例如裸片附着材料，接置于元件侧106。
电性互连118，例如焊线，可将基部集成电路裸片104耦合至元件侧106的触点114。还可在元件侧106的触点114上接置堆栈互连126，例如焊球、焊料柱或柱形凸块。模塑基部封装体204可囊装基部集成电路裸片104、电性互连118、堆栈互连126以及部分元件侧106。元件侧106的触点114无一外露于模塑基部封装体204，但堆栈互连126的顶部可突出于模塑基部封装体204，以供进一步的连接。
可在衬底108的系统侧110的触点114上形成系统互连122，例如焊球、焊料凸块、焊料柱或柱形凸块。系统互连122可电性连接至元件侧106的触点114、基部集成电路裸片104或其组合。
顶部封装206可通过硅通孔插入件128，例如具有耦合至堆栈互连126的硅通孔130的集成电路裸片耦合至堆栈互连126。硅通孔插入件128可具有作用面132和背面134。硅通孔插入件128的作用面132可包含集成电路(未图示)。
堆栈集成电路裸片136可通过粘接剂116接置在作用面132上。电性互连118可将堆栈集成电路裸片136耦合至作用面132上的硅通孔130。最终的电路可电性连接堆栈集成电路裸片136、硅通孔插入件128、基部集成电路裸片104、系统互连122或其组合。
通过模塑环氧模塑化合物以囊装堆栈集成电路裸片136、电性互连118以及硅通孔插入件128的作用面132和垂直面140，从而形成顶部封装体138。顶部封装体138留下外露的硅通孔插入件128的背面134。
顶部封装206和基部封装202可在组装之前进行测试，以提升制造良率并降低成本。已发现，通过包装在模塑基部封装体204内的堆栈互连126，，可降低组装前所述封装的脆弱性。现参考图3，图3显示本发明第三实施例中层迭封装堆栈式集成电路封装系统300的剖视图。该集成电路封装系统300的剖视图描述基部封装302，例如裸片朝下型塑料球栅阵列(PBGA)，其基部集成电路裸片304接置在具有开孔(opening)的衬底306的元件侧106。
衬底306，例如层压衬底或陶瓷衬底，具有系统侧110，通孔112将系统侧110的触点114耦合至元件侧106的触点114。基部集成电路裸片304可通过粘接剂116，例如裸片附着材料，以作用面朝下的方式接置于元件侧106。
电性互连118，例如焊线，可通过所述开孔将基部集成电路裸片304耦合至系统侧110的触点114。模塑基部封装体120可囊装基部集成电路裸片304、电性互连118以及部分元件侧106。元件侧106的一些触点114保持外露状态。
可在衬底108的系统侧110的触点114上形成系统互连122，例如焊球、焊料凸块、焊料柱或柱形凸块。系统互连122可电性连接至元件侧106的触点114、基部集成电路裸片304或其组合。
顶部封装124可包含堆栈互连126，例如焊球、焊料柱或柱形凸块。硅通孔插入件128，例如具有硅通孔130的集成电路裸片，可耦合至堆栈互连126。硅通孔插入件128可具有作用面132和背面134。硅通孔插入件128的作用面132可包含集成电路(未图示)。
堆栈集成电路裸片136可通过粘接剂116接置在作用面132上。电性互连118可将堆栈集成电路裸片136耦合至作用面132上的硅通孔130。最终的电路可电性连接堆栈集成电路裸片136、硅通孔插入件128、基部集成电路裸片304、系统互连122或其组合。
通过模塑环氧模塑化合物以囊装堆栈集成电路裸片136、电性互连118以及硅通孔插入件128的作用面132和垂直面140，从而形成顶部封装体138。顶部封装体138留下外露的硅通孔插入件128的背面134。
现参考图4，图4显示本发明第四实施例中层迭封装堆栈式集成电路封装系统400的剖视图。该集成电路封装系统400的剖视图描述基部封装102，其中，顶部封装402通过堆栈互连126耦合至衬底108的元件侧106上的触点114。
顶部封装402可包含堆栈互连126，例如焊球、焊料柱或柱形凸块。硅通孔插入件128，例如具有硅通孔130的集成电路裸片，可耦合至堆栈互连126。硅通孔插入件128可具有作用面132和背面134。硅通孔插入件128的作用面132可包含集成电路(未图示)。
堆栈集成电路裸片404，例如倒装芯片型集成电路裸片，可通过芯片互连406接置在作用面132上。可在作用面132与堆栈集成电路裸片404之间施加底部填充材料408。可通过作用面132上的硅通孔130耦合该堆栈集成电路裸片404。最终的电路可电性连接堆栈集成电路裸片404、硅通孔插入件128、基部集成电路裸片104、系统互连122或其组合。
通过模塑环氧模塑化合物以囊装堆栈集成电路裸片136、电性互连118以及硅通孔插入件128的作用面132和垂直面140，从而形成顶部封装体138。顶部封装体138留下外露的硅通孔插入件128的背面134。
现参考图5，图5显示本发明第五实施例中层迭封装堆栈式集成电路封装系统500的剖视图。该集成电路封装系统500的剖视图描述基部封装102，其中，顶部封装502通过堆栈互连126耦合至衬底108的元件侧106上的触点114。
顶部封装502可包含堆栈互连126，例如焊球、焊料柱或柱形凸块。硅通孔插入件128，例如具有硅通孔130的集成电路裸片，可耦合至堆栈互连126。硅通孔插入件128可具有作用面132和背面134。硅通孔插入件128的作用面132可包含集成电路(未图示)。
堆栈集成封装504可通过粘接剂116接置在作用面132上。堆栈集成封装504，例如塑料球栅阵列，可以顶面朝下方式置于作用面132上。
堆栈集成封装504可包含堆栈衬底506，其大体与基部封装102的衬底108类似。堆栈集成电路裸片508可通过粘接剂116接置在堆栈衬底506上。电性互连118可将堆栈集成电路裸片508耦合至堆栈衬底506。可在堆栈集成电路裸片508、堆栈衬底506以及电性互连118上施加模塑化合物而形成集成封装体510。
堆栈集成封装504可通过电性互连118耦合至作用面132上的硅通孔130。最终的电路可电性连接堆栈集成电路裸片508、硅通孔插入件128、基部集成电路裸片104、系统互连122或其组合。
通过模塑环氧模塑化合物以囊装堆栈集成封装136、电性互连118以及硅通孔插入件128的作用面132和垂直面140，从而形成顶部封装体138。顶部封装体138留下外露的硅通孔插入件128的背面134。
现参考图6，图6显示本发明第六实施例中层迭封装堆栈式集成电路封装系统600的剖视图。该集成电路封装系统600的剖视图描述基部封装102，其中，顶部封装602通过堆栈互连126耦合至衬底108的元件侧106上的触点114。
顶部封装602可包含堆栈互连126，例如焊球、焊料柱或柱形凸块。硅通孔插入件128，例如具有硅通孔130的集成电路裸片，可耦合至堆栈互连126。硅通孔插入件128可具有作用面132和背面134。硅通孔插入件128的作用面132可包含集成电路(未图示)。
可通过插入件互连606，例如焊球或焊料凸块，将附加硅通孔插入件604耦合至硅通孔插入件128。附加(additional)硅通孔插入件604可电性连接至硅通孔插入件128、基部集成电路裸片104、系统互连122或其组合。硅通孔插入件堆栈608可在顶部封装602内提供硅通孔插入件128的阵列。
通过模塑环氧模塑化合物以囊装附加硅通孔插入件604、插入件互连606以及硅通孔插入件128的作用面132和垂直面140，从而形成顶部封装体138。顶部封装体138留下外露的硅通孔插入件128的背面134。
尽管图6中显示由三块硅通孔插入件128形成硅通孔插入件堆栈608，但应了解，其仅为示例，且硅通孔插入件128可实施为不同数目。已发现，硅通孔插入件堆栈608可提供极短的互连长度，插入件互连606在1微米至5微米范围内。硅通孔插入件堆栈608还允许优化裸片尺寸，从而提升良率并改进性能。
已发现，硅通孔插入件堆栈608以及插入件互连606的使用还提供了高数据传输带宽，同时由于热损失减少而降低了功耗。缩小的互连长度相应降低了线路阻抗，从而减少了损失。
现参考图7，图7显示本发明第七实施例中层迭封装堆栈式集成电路封装系统700的剖视图。该集成电路封装系统700的剖视图描述基部封装702，其中，顶部封装402通过堆栈互连126耦合至衬底108的元件侧106上的触点114。
基部封装702可包含基部集成电路裸片704，例如倒装芯片型集成电路裸片，其可通过芯片互连406耦合至衬底108的元件侧106上的触点114。模塑基部封装体120可选择性囊装基部集成电路裸片704、芯片互连406、底部填充材料408以及部分元件侧106。元件侧106的一些触点114保持外露状态。
顶部封装402可包含堆栈互连126。硅通孔插入件128，例如具有硅通孔130的集成电路裸片，可耦合至堆栈互连126。硅通孔插入件128可具有作用面132和背面134。硅通孔插入件128的作用面132可包含集成电路(未图示)。
堆栈集成电路裸片404可通过芯片互连406接置在作用面132上。可在作用面132与堆栈集成电路裸片404之间施加底部填充材料408。可通过作用面132上的硅通孔130耦合堆栈集成电路裸片404。最终的电路可电性连接堆栈集成电路裸片404、硅通孔插入件128、基部集成电路裸片704、系统互连122或其组合。
通过模塑环氧模塑化合物以囊装堆栈集成电路裸片136、电性互连118以及硅通孔插入件128的作用面132和垂直面140，从而形成顶部封装体138。顶部封装体138留下外露的硅通孔插入件128的背面134。
现参考图8，图8显示本发明第八实施例中层迭封装堆栈式集成电路封装系统800的剖视图。该集成电路封装系统800的剖视图描述基部封装702，其中，顶部封装602通过堆栈互连126耦合至衬底108的元件侧106上的触点114。
附加硅通孔插入件604可电性连接至硅通孔插入件128、基部集成电路裸片704、系统互连122或其组合。
现参考图9，图9显示本发明一实施例中一节硅通孔晶片900的剖视图。该节硅通孔晶片900的剖视图描述硅通孔晶片902，其接置在例如晶片支持架或胶带的载体(carrier)904上。
硅通孔晶片902可在其作用面132上设置集成电路。电路迹线(trace)906可将该集成电路(未图示)耦合至硅通孔130，以使电路分布至背面134，从而允许进一步的附着。
现参考图10，图10显示处于制造的切单(singulation)阶段的硅通孔晶片1000的剖视图。该硅通孔晶片1000的剖视图描述接置在载体904上的晶片1002。
晶片1002可具有硅通孔130，该硅通孔130耦合于作用面132的电路迹线906与背面134的电路迹线906之间。如锯切(saw)或剪切(shear)的切单器件1004可将晶片1002在接置于载体904的情况下分成一组硅通孔插入件128。
现参考图11，图11显示处于制造的裸片接置阶段的第一顶部封装组件1100的剖视图。该第一顶部封装组件1100的剖视图描述接置于载体904上的硅通孔插入件组128。堆栈集成电路裸片136可置于该硅通孔插入件128上。可在硅通孔插入件128与堆栈集成电路裸片136之间施加粘接剂116。
现参考图12，图12显示处于制造的引线键合阶段的第二顶部封装组件1200的剖视图。该第二顶部封装组件1200的剖视图描述具有电性互连118耦合在堆栈集成电路裸片136与硅通孔插入件128的硅通孔130之间的第一顶部封装组件1100。
现参考图13，图13显示处于制造的分离阶段的第三顶部封装组件1300的剖视图。该第三顶部封装组件1300的剖视图描述在附着于载体904的情况下相互分离的第二顶部封装组件1200。
间隔距离1302足以提供硅通孔插入件128之间的模塑沟道。可在不从载体904去除硅通孔插入件128的情况下进行间隔距离1302的设置。
现参考图14，图14显示处于制造的模塑阶段的顶部封装阵列1400的剖视图。该顶部封装阵列1400的剖视图描述形成模塑化合物1402以囊装硅通孔插入件128、堆栈集成电路裸片136以及电性互连118。由于受载体904阻挡而仅硅通孔插入件128的背面134外露于模塑化合物1402。
现参考图15，图15显示处于制造的切单和接置阶段的上部封装组件1500的剖视图。该上部封装组件1500的剖视图描述对图14所示的顶部封装阵列1400进行切单而形成的顶部封装的阵列206。
现参考图16，图16显示处于制造的互连形成阶段的上部封装阵列1600的剖视图。该上部封装阵列1600的剖视图描述通过附着堆栈互连126而形成的顶部封装124。现在，该顶部封装为供测试和接置。
现参考图17，图17显示处于制造的完成阶段的集成电路封装系统的阵列1700的剖视图。该集成电路封装系统的阵列1700的剖视图描述处于完成阶段并为供组装于下一级系统(未图示)的阵列型集成电路封装系统100的阵列。
现参考图18，图18显示处于制造的裸片接置阶段的硅通孔晶圆组件1800的剖视图。该硅通孔晶圆组件1800的剖视图描述在一替代制造工艺中，通过粘接剂116在硅通孔晶片1802上接置堆栈集成电路裸片136。
该堆栈集成电路裸片136位于后续制造步骤中将要切单的区域。堆栈集成电路裸片136通过电性互连118耦合至硅通孔晶片1802。硅通孔晶片1802可接置于载体904上以在工艺中保护背面134。
现参考图19，图19显示处于制造的线路固定施加阶段的硅通孔晶片组件1900的剖视图。该硅通孔晶片组件1900的剖视图描述在硅通孔晶片组件1800具有形成在电性互连118上的保护层1902，该保护层1902例如由线路固定树脂材料构成。
现参考图20，图20显示处于制造的切单阶段的硅通孔晶片组件2000的剖视图。该硅通孔晶片组件2000的剖视图描述使用切单器件1004进行切单硅通孔晶片组件1900后的硅通孔晶片组件1900。
现参考图21，图21显示处于制造的分离阶段的硅通孔晶片2100的剖视图。该硅通孔晶片2100的剖视图描述在附着在载体904的情况下相互分离的顶部封装组件2102的切单单元。
间隔距离1302足以提供各顶部封装组件2102之间的模塑沟道。可在不从载体904去除顶部封装组件2102的情况下进行间隔距离1302的设置。
现参考图22，图22显示处于制造的模塑阶段的顶部封装阵列2200的剖视图。该顶部封装阵列2200的剖视图描述形成模塑化合物以囊装堆栈集成电路裸片136、围绕电性互连118的线路固定树脂材料1902以及硅通孔插入件128除背面134以外的所有表面。背面134被载体904阻挡。
现参考图23，图23显示处于制造的接置阶段的上部封装组件2300的剖视图。该上部封装组件2300的剖视图描述对图22所示的顶部封装阵列2200切单后形成的顶部封装206的阵列。
现参考图24，图24显示处于制造的互连形成阶段的上部封装组件2400的剖视图。该上部封装组件2400的剖视图描述通过附着堆栈互连126后形成的顶部封装124。现在，该顶部封装为供测试和接置。
现参考图25，图25显示处于制造的完成阶段的集成电路封装系统100的阵列的剖视图。该集成电路封装系统100的阵列的剖视图描述处于完成阶段并为供组装于下一级系统(未图示)的集成电路封装系统100的阵列。
现参考图26，图26显示本发明一实施例中集成电路封装系统的制造方法2600的流程图。该方法2600包含：在方块2602中，形成顶部封装，包含：提供具有硅通孔的硅通孔插入件，将堆栈集成电路裸片耦合至该硅通孔，以及，测试顶部封装；在方块2604中，形成基部封装，包含：提供衬底，将基部集成电路裸片耦合至该衬底，以及，测试基部封装；以及，在方块2606中，在该顶部封装与该基部封装之间耦合堆栈互连。
所述方法、工艺、装置、器件、产品和/或系统是简单明了、经济有效、不复杂、灵活多变而有效，可通过应用现有技术而进行意料不到的、非显而易见的实施，且因此适于经济有效地制造与现有制造方法或工艺以及技术完全兼容的层迭封装堆栈式系统。
本发明的再一个重要态样是其有益地支持与服务降低成本、简化系统、提高性能的历史性发展趋势。
因此，本发明的上述以及其它有益的态样因此提升了技术状态至至少下一水平。
尽管本文结合特定实施例描述了本发明，应当理解的是，根据上述说明，对于本领域技术人员而言，进行许多替换、更改和变化是显而易见的。因此，所有此类替换、更改和变化均落入权利要求范围中。上述内容或附图所示内容均为描述性质，而非限制本发明。

Claims (10)

1.一种集成电路封装系统的制造方法，包括以下步骤：
形成顶部封装，包含：
提供具有硅通孔的硅通孔插入件，
将堆栈集成电路裸片耦合至该硅通孔，以及
测试该顶部封装；
形成基部封装，包含：
提供衬底，
将基部集成电路裸片耦合至该衬底，以及
测试该基部封装；以及
在该顶部封装与该基部封装之间耦合堆栈互连。
2.如权利要求1所述的方法，进一步包括在该堆栈集成电路裸片与该硅通孔插入件上形成模塑化合物的步骤。
3.如权利要求1所述的方法，进一步包括以下步骤：
形成包含该堆栈集成电路裸片的堆栈集成封装；以及
在该堆栈集成封装与该硅通孔插入件之间耦合电性互连。
4.如权利要求1所述的方法，其中，形成该顶部封装的步骤包含：
通过插入件互连将附加硅通孔插入件耦合至该硅通孔插入件的步骤；以及
在该硅通孔插入件、该附加硅通孔插入件以及该插入件互连上形成模塑化合物的步骤，该步骤包含留下外露的该硅通孔插入件的背面。
5.如权利要求1所述的方法，其中，在该顶部封装与该基部封装之间耦合该堆栈互连的步骤包含在该堆栈集成电路裸片、该硅通孔插入件、该基部集成电路裸片或其组合之间形成电性连接。
6.一种集成电路封装系统，包括：
顶部封装，包含：
具有硅通孔的硅通孔插入件，以及
耦合至该硅通孔的堆栈集成电路裸片；
形成基部封装，包含：
衬底，以及
耦合至该衬底的基部集成电路裸片；以及
在该顶部封装与该基部封装之间的堆栈互连。
7.如权利要求6所述的系统，进一步包括形成在该堆栈集成电路裸片与该硅通孔插入件上的模塑化合物。
8.如权利要求6所述的系统，进一步包括：
包含该堆栈集成电路裸片的堆栈集成封装；以及
在该堆栈集成封装与该硅通孔插入件之间的电性互连。
9.如权利要求6所述的系统，其中，该顶部封装包含：
通过插入件互连耦合至该硅通孔插入件的附加硅通孔插入件；以及
在该硅通孔插入件、该附加硅通孔插入件以及该插入件互连上的模塑化合物，其包含外露的该硅通孔插入件的背面。
10.如权利要求6所述的系统，其中，该顶部封装与该基部封装之间的该堆栈互连包含该堆栈集成电路裸片、该硅通孔插入件、该基部集成电路裸片或其组合之间的电性连接。
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TW201130109A (en) 2011-09-01
CN102044452B (zh) 2015-07-01
SG189741A1 (en) 2013-05-31
US20110089552A1 (en) 2011-04-21
TWI512942B (zh) 2015-12-11
SG170678A1 (en) 2011-05-30

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