TWI652783B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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Abstract
本揭露提供一種半導體裝置及其製造方法。在本揭露之實施例中,該半導體裝置包含一積體電路晶粒;設置於該積體電路晶粒上的至少一導電終端;設置於該積體電路晶粒上的一框架,其中該框架實質暴露該至少一導電終端;以及設置於該框架中的至少一導電凸塊,其中該至少一導電凸塊電連接該至少一導電終端。
Description
本揭露明係關於一種具有導電凸塊的半導體裝置及其製造方法,其中半導體裝置具有非常精細的間距(fine-pitch)、高散熱特性、低翹曲、以及最小化的凸塊製程應力(bumping stress)。
積體電路(IC)結構的封裝技術持續發展,以符合微小化與安裝可信賴度(mounting reliability)的要求。近來,由於電子產品對微小化與高功能需求,此一技術領域已揭露各種技術,以因應該等需求。
如所周知,半導體晶片在操作時會產生熱量。在操作過程中,隨著半導體的溫度升高與下降,矽與金屬或金屬物質之間不同的熱膨脹係數可在半導體晶片中造成應力,此一現象在半導體晶片操作過程中會顯著惡化晶片中矽/金屬接合的完整性與可信賴度。當操作溫度改變時,個別材料的位移改變;若熱膨脹係數差異造成的應力無法釋放,則可能造成封裝結構的斷裂。
再者,來自晶片操作的熱量通常造成積體電路結構的功能障礙。當晶片溫度增加時,其可能相對影響小剖面的接線,因而破壞積體電路結構的正常功能。因此,近年來,隨著半導體封裝的微小化,積體電路結構中
的散熱問題已吸引越來越多的關注。
一般而言,封裝產業中使用兩種不同的信號接頭接合(signal joint binding)方法,分別習知的打線接合(wire bonding,WB)與進階的覆晶接合(flip chip bonding,FCB)。在安裝至應用印刷電路板(PCB)或其他邏輯封裝上之前,此等接合方法係用於形成IC封裝。
只要半導體裝置設計考量線迴路(wire looping),打線接合技術之成本低且製程可變化,因而仍為最廣泛用於IC組裝產業中的信號接頭(signal joint)。當面臨打線接合過多問題時,SiP(系統封裝)模組與矽間隔物一併採用打線接合。
此外,依照接頭尺寸/間距/高度以及應用領域,存有不同的FCB構造。不論FCB型式,相較於打線接合封裝,使用FCB製程的主要效應為熱/電效能較高且封裝尺寸架構較小。特別地,由於輸入/輸出(I/O)數量非常多,大部分的邏輯晶粒係使用FCB製程。
上文之「先前技術」說明僅係提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不構成本揭露之先前技術,且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露明係關於一種具有導電凸塊的半導體裝置及其製造方法,其中半導體裝置具有非常精細的間距(fine-pitch)、高散熱特性、低翹曲、以及最小化的凸塊製程應力(bumping stress)。
本揭露提供一種半導體裝置。在本揭露之實施例中,該半導體裝置包括:一積體電路晶粒;至少一導電終端,設置於該積體電路晶粒上;一框架,設置於該積體電路晶粒上,其中該框架實質暴露該至少一導電終
端;以及至少一導電凸塊,設置於該框架中,其中該至少一導電凸塊電連接該至少一導電終端。
在本揭露之實施例中,該框架係一支撐層,包含非導電材料,該非導電材料係選自於包括矽與二氧化矽組成的群組。
在本揭露之實施例中,該框架包括:一支撐層,包含非導電材料,該非導電材料係選自於包括矽與二氧化矽組成的群組;以及一中介層,設置於該支撐層與該積體電路晶粒之間。
在本揭露之實施例中,該半導體裝置另包括至少一導電接頭,設置於該至少一導電凸塊與該至少一導電終端之間,並且該至少一導電接頭與該至少一導電凸塊形成至少一導電插塞。
在本揭露之實施例中,該至少一導電接頭與該至少一導電凸塊係由不同材料製成。
在本揭露之實施例中,該至少一導電凸塊之剖面圖具有一實質非球形側壁。
在本揭露之實施例中,該至少一導電凸塊之剖面圖具有一實質垂直側壁。
本揭露另提供一種半導體封裝。在本揭露之實施例中,該半導體封裝包括:一半導體裝置,具有至少一導電終端;一框架,設置於該半導體裝置上,其中該框架實質暴露該至少一導電終端;至少一導電凸塊,設置於該框架中,其中該至少一導電凸塊電連接該至少一導電終端;一物件,具有至少一導電墊;以及一黏著層,設置於該半導體裝置與該物件之間。
在本揭露之實施例中,該框架係一支撐層,包含非導電材料,該非導電材料係選自於包括矽與二氧化矽組成的群組。
在本揭露之實施例中,該框架包括:一支撐層,包含非導電材料,該非導電材料係選自於包括矽與二氧化矽組成的群組;以及一中介層,設置於該支撐層與該積體電路晶粒之間。
在本揭露之實施例中,該半導體封裝另包括至少一導電接頭,設置於該至少一導電凸塊與該至少一導電終端之間,並且該至少一導電接頭與該至少一導電凸塊形成至少一導電插塞。
在本揭露之實施例中,該至少一導電接頭與該至少一導電凸塊係由不同材料製成。
在本揭露之實施例中,該至少一導電凸塊之剖面圖具有一實質非球形側壁。
在本揭露之實施例中,該至少一導電凸塊之剖面圖具有一實質垂直側壁。
本揭露另提供一種半導體封裝的製造方法。在本揭露之實施例中,該半導體封裝的製造方法包括以下步驟:製備具有至少一導電終端的一半導體裝置;形成一框架於該半導體裝置上,其中該框架實質暴露該至少一導電終端;以及形成至少一導電凸塊於該框架中,其中該至少一導電凸塊電連接該至少一導電終端。
本揭露另提供一種半導體封裝的製造方法。在本揭露之實施例中,該半導體封裝的製造方法包括以下步驟:製備具有至少一導電終端的半導體裝置;形成具有至少一開孔的一框架與導電接頭於該半導體裝置上,其中該至少一開孔與該導電接頭係設置於該至少一導電終端上方;以及形成至少一導電凸塊於該框架的該至少一開孔中,其中該至少一導電凸塊電連接該至少一導電終端。
在本揭露之實施例中,形成一框架於該半導體裝置上的步驟包括:形成一支撐層於該半導體裝置上,該支撐層包含非導電材料,該非導電材料係選自於包括矽與二氧化矽組成的群組;形成一蝕刻遮罩層,具有至少一開口於該支撐層上,其中該至少一開口係設置於該至少一導電終端上方;以及進行一蝕刻製程,藉由使用該蝕刻遮罩層,以形成至少一開孔於該支撐層中,其中該至少一開孔暴露該至少一導電終端。
在本揭露之實施例中,形成一框架於該半導體裝置上的步驟包括:形成一中介層於該半導體裝置上;形成一支撐層於該中介層上,該支撐層包含非導電材料,該非導電材料係選自於包括矽與二氧化矽組成的群組;形成一蝕刻遮罩層,具有至少一開口於該支撐層上,其中該至少一開口係設置於該至少一導電終端上方;以及進行一蝕刻製程,藉由使用該蝕刻遮罩層,以形成至少一開孔於該支撐層中,其中該至少一開孔暴露該至少一導電終端。
在本揭露之實施例中,形成至少一導電凸塊於該框架中的步驟包括進行一鍍膜製程。
在本揭露之實施例中,該製造方法另包括以下步驟:製備一物件,具有至少一導電墊;以及以一黏著層附接該半導體裝置至該物件,該黏著層設置於該半導體裝置與該物件之間,其中該等導電墊電連接該至少一導電凸塊。
在本揭露的一些實施例中,該框架定義導電凸塊的邊界,亦即本揭露在形成凸塊之前先形成該框架。在本揭露之實施例中,藉由微影製程與蝕刻製程,形成該框架中的該至少一開孔,其可形成極精細間距的至少一開孔(該導電凸塊),並且可形成具非常精細尺寸的導電凸塊。因此,本揭
露可實施具有高輸入/輸出密度的半導體裝置。
在本揭露的一些實施例中,導電凸塊係受到矽或氧化矽的框架所環繞;相對地,先前技術的凸塊係由樹脂環繞。由於矽或氧化矽的框架之導熱性高於樹脂,因而該框架具有高散熱性質。此外,矽或氧化矽的框架之強度與剛度(stiffness)皆高於樹脂,半導體裝置與框架整體具有高應力(造成導電凸塊受到較低的熱應力),並且可減少半導體裝置的翹曲。
在先前技術中,模塑料與黏著層在積體電路晶粒的電路部分形成界面,因而在積體電路晶粒的電路部分易於發生破裂。相對地,在本揭露之實施例中,模塑料與黏著層在沒有電路的框架形成界面,因而可避免在積體電路晶粒中發生晶粒破裂。
10A‧‧‧積體電路晶粒
11‧‧‧基板部
13‧‧‧電互連部
13'‧‧‧電互連部
90‧‧‧模塑料
100A‧‧‧半導體封裝
100B‧‧‧半導體封裝
100C‧‧‧半導體封裝
100D‧‧‧半導體封裝
130A‧‧‧框架
130B‧‧‧複合框架
131‧‧‧中介層
133‧‧‧支撐層
135A‧‧‧複合疊層
135B‧‧‧複合疊層
140‧‧‧導電凸塊
140'‧‧‧導電凸塊
141‧‧‧導電終端
141'‧‧‧導電終端
143‧‧‧導電接頭
145‧‧‧複合插塞
150‧‧‧蝕刻遮罩層
151‧‧‧開口
153‧‧‧開孔
200‧‧‧物件
201‧‧‧導電墊
203‧‧‧黏著層
220‧‧‧焊球
參閱詳細說明與申請專利範圍結合考量圖式時,可得以更全面了解本申請案之揭示內容,圖式中相同的元件符號係指相同的元件。
圖1係一剖面示意圖,例示本揭露實施例的半導體封裝。
圖2係一剖面示意圖,例示本揭露實施例的半導體封裝。
圖3係一剖面示意圖,例示本揭露實施例的半導體封裝。
圖4係一剖面示意圖,例示本揭露實施例的半導體封裝。
圖5至圖10係剖面示意圖,例示本揭露實施例的晶片封裝之製造方法。
圖11至圖16係剖面示意圖,例示本揭露實施例的晶片封裝之製造方法。
圖17至圖22係剖面示意圖,例示本揭露實施例的晶片封裝之製造方法。
圖23至圖28係剖面示意圖,例示本揭露實施例的晶片封裝之製造方法。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式,說明本揭露之實施例,然而本揭露並不受限於該實施例。此外,以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性,然而並非每一實施例必須包含該特定特徵、結構或是特性。再者,重複使用「在實施例中」一語並非必須指相同實施例,然而可為相同實施例。
本發明係關於一種具有導電凸塊(bump)的半導體封裝及其製造方法。為了使得本揭露可被完全理解,以下說明提供詳細的步驟與結構。顯然,本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外,已知的結構與步驟不再詳述,以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而,除了詳細說明之外,本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容,而是由申請專利範圍定義。
圖1係一剖面示意圖,例示本揭露實施例的半導體封裝。在本揭露之實施例中,半導體封裝100A包括具有複數個導電終端141的積體電路晶粒10A;設置於積體電路晶粒10A上的框架130A;以及設置於框架130A中的複數個導電凸塊140,其中框架130A實質暴露該等導電終端141,以及該等導電凸塊140電連接該等導電終端141。在本揭露之實施例中,半導
體封裝100A另包括具有複數個導電墊201的物件200;設置於積體電路晶粒10A與物件200之間的黏著層203;以及囊封積體電路晶粒10A的模塑料90。
在本揭露之實施例中,積體電路晶粒10A係包含複數個積體電路晶粒的積體電路晶圓。在本揭露之實施例中,積體電路晶粒10A係晶圓上的複數個積體電路晶粒其中之一。在本揭露之實施例中,積體電路晶粒10A係從晶圓分割的積體電路晶粒。在本揭露之實施例中,積體電路晶粒10A係記憶體晶片,例如DRAM晶片或是快閃記憶體晶片。已知記憶體晶片包括用於定址(addressing)多個記憶體胞元的位址輸入終端、用於輸入資料至記憶體胞元/自記憶體胞元輸出資料的資料輸入/輸出終端、以及電源供應終端。
在本揭露之實施例中,積體電路晶粒10A包含基板部11與設置於基板部11上方的電互連部13。在本揭露之實施例中,基板部11可包含矽晶圓。例如,基板部11可包含單晶矽晶圓、包含碳化矽(SiC)層或矽鍺(SiGe)層的塊狀矽晶圓、或包含絕緣層的絕緣體覆矽(silicon-on-insulator,SOI)晶圓。在本實施例中,基板部11為單晶矽塊狀晶圓。在本揭露之實施例中,至少一積體電路晶粒10A可包含多個單元裝置,其可形成於基板部11中以及/或基板部11上,並且該等單元裝置可包含金屬氧化物半導體(metal-oxide-semiconductor,MOS)電晶體。
在本揭露之實施例中,積體電路晶粒10A可另包含設置於基板部11與模塑料90之間的第一電互連部(未繪示於圖式中),而電互連部13係作為第二電互連部。在本揭露之實施例中,基板部11可視需要包含貫穿矽通道(未繪示於圖式中),將第一電互連部電連接至第二電互連部。
在本揭露之實施例中,框架130A為支撐層,由選自於包括矽與二氧化矽所組成的群組之非導電材料形成。在本揭露之實施例中,框架130A定義導電凸塊140的邊界,導電凸塊140之剖面圖具有實質非球形側壁。在本揭露之實施例中,該等導電凸塊140之剖面圖具有實質垂直的側壁。在本揭露之實施例中,物件200為封裝電路基板、矽/玻璃插入件、或另一積體電路晶粒;其中該等導電凸塊140係分別附接至該等導電墊201。在本揭露之實施例中,黏著層203為非等向性導電膜(anisotropic conductive film,ACF)、非等向性導電黏著物(anisotropic conductive adhesive,ACA)、非導電膜/漿(nonconductive film/paste,NCF/NCP)、底膠填充物(uderfill,UF)、模製底膠填充物(molding uderfill,MUF)等等。ACF或ACA包括絕緣膜或絕緣黏著物,其中導電粒子分散於絕緣膜或絕緣黏著物內。NCF/NCP或UF/MUF包括絕緣膜或黏著物,其中非導電粒子分散於絕緣膜/黏著物內。
在本揭露的一些實施例中,導電凸塊140係由矽或氧化矽的框架130A環繞;相對地,先前技術的凸塊係由樹脂環繞。由於矽或氧化矽的框架130A的導熱性高於樹脂,因而框架130A具有高散熱性質。此外,矽或氧化矽的框架130A的強度或剛度(stiffness)皆高於樹脂,積體電路晶粒10A與框架130A整體具有高應力(造成導電凸塊140受到較低的熱應力),並且可減少積體電路晶粒10A的翹曲。
在先前技術中,模塑料與黏著層在積體電路晶粒的電路部分形成界面,因而在積體電路晶粒的電路部分易於發生破裂。相對地,在本揭露之實施例中,模塑料90與黏著層203在沒有電路的框架130A形成界面,因而可避免在積體電路晶粒10A中發生晶粒破裂。
圖2係一剖面示意圖,例示本揭露實施例的半導體封裝。圖2中的半導體封裝100B係類似於圖1所示的半導體封裝100A,差別在於半導體封裝100B使用複合框架(composite frame)130B。在本揭露之實施例中,複合框架130B包括中介層131與支撐層133,其中中介層131係設置於支撐層133與積體電路晶粒10A之間。在本揭露之實施例中,支撐層133包含非導電材料,該非導電材料係選自於包括矽與二氧化矽所組成的群組。在本揭露之實施例中,中介層131為積體電路晶粒10A的保護層或黏膠層,用於改良支撐層133與積體電路晶粒之間的黏附。
圖3係一剖面示意圖,例示本揭露實施例的半導體封裝。圖3的半導體封裝100C係類似於圖2的半導體封裝100B,差別在於半導體封裝100C使用複合插塞(composite plug)145,以電連接該等導電終端141與該等導電墊201。在本揭露之實施例中,該等複合插塞145各自包括導電接頭143與導電凸塊140',其中導電凸塊140'係設置於導電接頭143與導電墊201之間。在本揭露之實施例中,該等導電接頭143與該等導電凸塊140'係由導電材料製程,例如銅與錫。在本揭露之實施例中,該等導電接頭143與該等導電凸塊140'係由不同的導電材料製程,例如導電接頭143係由銅製成,導電凸塊140'係由錫製成。
圖4係一剖面示意圖,例示本揭露實施例的半導體封裝。圖4的半導體封裝100D係類似於圖2的半導體封裝100B,差別在於半導體封裝100D的積體電路晶粒10B使用嵌置的導電終端141'。在本揭露之實施例中,積體電路晶粒10B包括基板部11與設置於基板部11上的電互連部13'。在圖4中,積體電路晶粒10B之嵌置的導電終端141'係設置於電互連部13'中,而在圖2中,積體電路晶粒10A的導電終端141係設置於電互連部13上方
圖5至圖10係剖面示意圖,例示說明本揭露實施例的晶片封裝100B之製造方法。
參閱圖5,藉由沉積、微影以及蝕刻製程,在基板部11上形成電互連部13。接著,藉由包含沉積、微影與蝕刻製程,在電互連部13上形成複數個導電終端141,以形成積體電路晶粒10A;之後,藉由沉積製程,在積體電路晶粒10A上形成保護層131A。在本揭露之實施例中,基板部11可包含電晶體,該電晶體係設置於受到隔離結構環繞的主動區域(active area,AA)中,該隔離結構例如淺溝槽隔離(shallow trench isolation,STI)。在本揭露之實施例中,藉由後段金屬化技術,在基板部11上形成電互連部13。
參閱圖6,在積體電路晶粒10A上形成支撐層133,其中支撐層133係由非導電材料形成,該非導電材料係選自於包括矽與二氧化矽所組成的群組。在本揭露之實施例中,藉由融合接合技術,在積體電路晶粒10A上形成支撐層133。融合接合技術的細節係揭露於文獻(An Overview of Patterned Metal/Dielectric Surface Bonding:Mechanism,Alignment and Characterization,J.Electrochem.Soc.2011 volume 158,issue 6,P81-P86),其全文合併於本文中做為參考並且將不再重述。
參閱圖7,藉由微影製程在支撐層133上形成蝕刻遮罩層150,例如具有複數個開口151的光阻層,其中該等開口151係設置於該等導電終端141上方。接著,進行蝕刻製程(例如乾蝕刻製程),藉由使用蝕刻遮罩層150而於支撐層133中形成複數個開孔153,其中該等開孔153暴露該等終端141。
參閱圖8,剝除蝕刻遮罩層150,並且藉由金屬鍍膜製程在支撐層133
的該等開孔153中形成複數個導電凸塊140,其中該等導電凸塊140分別電連接該等導電終端141。在本揭露之實施例中,支撐層133與該等開孔153係作為定義導電凸塊140的邊界之框架;由於該等開孔153係由乾蝕刻製程形成,因而導電凸塊140之剖面圖具有實質非球形側壁。在本揭露之實施例中,由於該等開孔153係由乾蝕刻製程形成,因而該等導電凸塊140之剖面圖具有實質垂直的側壁。
參閱圖9,將圖8的製品(article)翻轉並且附接至具有複數個導電墊201的物件200,其中黏著層203設置於積體電路晶粒10A與物件200之間。接著,形成模塑料90以囊封積體電路晶粒10A,並且於物件200上形成複數個焊球220,以形成半導體封裝100B,如圖10所示。
在本揭露的實施例中,框架130B定義該等導電凸塊140的邊界,亦即本揭露在形成凸塊140之前先形成框架130B。在本揭露之實施例中,藉由微影製程與蝕刻製程在框架130B中形成開孔153,該微影製程與蝕刻製程可形成極精細間距的開孔153(導電凸塊140),並且可形成非常精細尺寸的導電凸塊140。因此,本揭露可實現具有高輸入/輸出密度的半導體裝置。
在本揭露之實施例中,可藉由圖5至圖10揭露的製程,實質製造半導體封裝100A,其中保護層131A與支撐層133應包含相同材料,例如氧化矽或矽。
在本揭露之實施例中,可藉由圖5至圖10揭露的製程,實質製造半導體封裝100D,其中該等導電終端141係形成於電互連部13中。
圖11至圖16係剖面示意圖,例示本揭露實施例的晶片封裝100B之製造方法。
參閱圖11,藉由沉積、微影以及蝕刻製程,在基板部11上形成電互連部13。接著,藉由沉積、微影與蝕刻製程,在電互連部13上形成複數個導電終端141,以形成積體電路晶粒10A;之後,附接黏膠層131B於積體電路晶粒10A上。
參閱圖12,在積體電路晶粒10A上形成支撐層133,其中支撐層1、33包含非導電材料,該非導電材料係選自於包括矽與二氧化矽所組成的群組。
參閱圖13,藉由微影製程在支撐層133上形成蝕刻遮罩層150,例如具有複數個開口151的光阻層,其中該等開口151係設置於該等導電終端141上方。接著,藉由使用蝕刻遮罩層150,進行蝕刻製程(例如乾蝕刻製程),以形成複數個開孔153於支撐層133中,其中該等開孔153暴露該等導電終端141。
參閱圖14,剝除蝕刻遮罩層150,並且進行金屬鍍膜製程,以形成複數個導電凸塊140於支撐層133的複數個開孔153中,其中該等導電凸塊140電連接該等導電終端141。在本揭露之實施例中,支撐層133係作為框架,定義導電凸塊140的邊界,導電凸塊140之剖面圖具有實質非球形側壁。在本揭露之實施例中,該等導電凸塊140之剖面圖具有實質垂直的側壁。
參閱圖15,將圖14的製品翻轉且附接至具有複數個導電墊201的物件200,其中黏著層203設置於積體電路晶粒10A與物件200之間。接著,形成模塑料90以囊封積體電路晶粒10A,並且形成複數個焊球220於物件200上,以形成半導體封裝100B,如圖16所示。
圖17至圖22係剖面示意圖,例示本揭露實施例的晶片封裝100B之製
造方法。
參閱圖17,藉由沉積、微影以及蝕刻製程,在基板部11上形成電互連部13。接著,藉由沉積、微影以及蝕刻製程,在電互連部13上形成複數個導電終端141,以形成積體電路晶粒10A。接著,附接複合疊層(composite laminate)135A至積體電路晶粒10A上,如圖18所示。在本揭露之實施例中,複合疊層135A包括黏膠層131;設置於黏膠層131上的支撐層133。
參閱圖19,藉由微影製程在支撐層133上形成蝕刻遮罩層150,例如具有複數個開口151的光阻層,其中該等開口151係設置於該等導電終端141上方。接著,藉由使用蝕刻遮罩層150而進行蝕刻製程(例如乾蝕刻製程),以於支撐層133中形成複數個開孔153,其中該等開口153暴露該等導電終端141。
參閱圖20,剝除蝕刻遮罩層150,並且進行金屬鍍膜製程以形成複數個導電凸塊140於支撐層133的複數個開孔153中,其中該等導電凸塊電連接複數個導電終端141。在本揭露之實施例中,支撐層133係作為框架,定義導電凸塊140的邊界,導電凸塊140之剖面圖具有實質非球形側壁。在本揭露之實施例中,該等導電凸塊140之剖面圖具有實質垂直的側壁。
參閱圖21,將圖20的製品翻轉並且附接至具有複數個導電墊201的物件200,其中黏著層203設置於積體電路晶粒10A與物件200之間。接著,形成模塑料90以囊封積體電路晶粒10A,並且形成複數個焊球220於物件200上,因而形成半導體封裝100B,如圖22所示。
圖23至圖28係剖面示意圖,例示本揭露實施例的晶片封裝100C之製造方法。
參閱圖23,藉由沉積、微影以及蝕刻製程,在基板部11上形成電互連部13。接著,藉由沉積、微影以及蝕刻製程,在電互連部13上形成複數個導電終端141,以形成積體電路晶粒10A。接著,附接複合疊層(composite laminate)135B至積體電路晶粒10A上,如圖24所示。在本揭露之實施例中,複合疊層135B包括黏膠層131;設置於黏膠層131上的支撐層133;以及設置於支撐層133中的複數個導電接頭143。在本揭露之實施例中,導電接頭143可視需要形成於黏膠層131中。
參閱圖25,藉由微影製程在支撐層133上形成蝕刻遮罩層150,例如具有複數個開口151的光阻層,其中該等開口151係設置於該等導電終端141上方。接著,藉由使用蝕刻遮罩層150而進行蝕刻製程(例如乾蝕刻製程),以於支撐層133中形成複數個開孔153,其中該等開口153暴露該等導電接頭143。
參閱圖26,剝除蝕刻遮罩層150,並且進行金屬鍍膜製程以形成複數個導電凸塊140'於支撐層133的複數個開孔153中,其中該等導電凸塊140'經由複數個導電接頭143而電連接複數個導電終端141,導電接頭143與導電凸塊140'形成複合插塞145。在本揭露之實施例中,支撐層133係作為框架,定義複合插塞145的邊界,複合插塞145之剖面圖具有實質非球形側壁。在本揭露之實施例中,複合插塞145之剖面圖具有實質垂直的側壁。
參閱圖27,將圖26的製品翻轉並且附接至具有複數個導電墊201的物件200,黏著層203設置於積體電路晶粒10A與物件200之間。接著,形成模塑料90以囊封積體電路晶粒10A,並且形成複數個焊球220於物件200上,因而形成半導體封裝100C,如圖28所示。
本揭露提供一種半導體裝置。在本揭露之實施例中,該半導體裝置
包括:一積體電路晶粒;至少一導電終端,設置於該積體電路晶粒上;一框架,設置於該積體電路晶粒上,其中該框架實質暴露該至少一導電終端;以及至少一導電凸塊,設置於該框架中,其中該至少一導電凸塊電連接該至少一導電終端。
本揭露另提供一種半導體封裝。在本揭露之實施例中,該半導體封裝包括:一半導體裝置,具有至少一導電終端;一框架,設置於該半導體裝置上,其中該框架實質暴露該至少一導電終端;至少一導電凸塊,設置於該框架中,其中該至少一導電凸塊電連接該至少一導電終端;一物件,具有至少一導電墊;以及一黏著層,設置於該半導體裝置與該物件之間。
本揭露另提供一種半導體封裝的製造方法。在本揭露之實施例中,該半導體封裝的製造方法包括以下步驟:製備具有至少一導電終端的一半導體裝置;形成一框架於該半導體裝置上,其中該框架實質暴露該至少一導電終端;以及形成至少一導電凸塊於該框架中,其中該至少一導電凸塊電連接該至少一導電終端。
本揭露另提供一種半導體封裝的製造方法。在本揭露之實施例中,該半導體封裝的製造方法包括以下步驟:製備具有至少一導電終端的半導體裝置;形成具有至少一開孔的一框架與導電接頭於該半導體裝置上,其中該至少一開孔與該導電接頭係設置於該至少一導電終端上方;以及形成至少一導電凸塊於該框架的該至少一開孔中,其中該至少一導電凸塊電連接該至少一導電終端。
在本揭露的一些實施例中,該框架定義導電凸塊的邊界,亦即本揭露在形成凸塊之前先形成該框架。在本揭露之實施例中,藉由微影製程與蝕刻製程,形成該框架中的該至少一開孔,其可形成極精細間距的至少一
開孔(該導電凸塊),並且可形成具非常精細尺寸的導電凸塊。因此,本揭露可實施具有高輸入/輸出密度的半導體裝置。
在本揭露的一些實施例中,導電凸塊係受到矽或氧化矽的框架所環繞;相對地,先前技術的凸塊係由樹脂環繞。由於矽或氧化矽的框架之導熱性高於樹脂,因而該框架具有高散熱性質。此外,矽或氧化矽的框架之強度與剛度(stiffness)皆高於樹脂,半導體裝置與框架整體具有高應力(造成導電凸塊受到較低的熱應力),並且可減少半導體裝置的翹曲。
在先前技術中,模塑料與黏著層在積體電路晶粒的電路部分形成界面,因而在積體電路晶粒的電路部分易於發生破裂。相對地,在本揭露之實施例中,模塑料與黏著層在沒有電路的框架形成界面,因而可避免在積體電路晶粒中發生晶粒破裂。
雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。
再者,本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
Claims (17)
- 一種半導體裝置,包括:一積體電路晶粒;至少一導電終端,設置於該積體電路晶粒上;一框架,設置於該積體電路晶粒上,其中該框架實質暴露該至少一導電終端;以及至少一導電凸塊,設置於該框架中,其中該至少一導電凸塊電連接該至少一導電終端;其中該框架係一支撐層,包含非導電材料,該非導電材料係選自於包括矽與二氧化矽組成的群組。
- 如請求項1所述之半導體裝置,其中該框架包括:一中介層,設置於該支撐層與該積體電路晶粒之間。
- 如請求項1所述之半導體裝置,另包括至少一導電接頭,設置於該至少一導電凸塊與該至少一導電終端之間,並且該至少一導電接頭與該至少一導電凸塊形成至少一導電插塞。
- 如請求項3所述之半導體裝置,其中該至少一導電接頭與該至少一導電凸塊係由不同材料製成。
- 如請求項1所述之半導體裝置,其中該至少一導電凸塊之剖面圖具有一實質非球形側壁。
- 如請求項1所述之半導體裝置,其中該至少一導電凸塊之剖面圖具有一實質垂直側壁。
- 一種半導體封裝,包括:一半導體裝置,具有至少一導電終端;一框架,設置於該半導體裝置上,其中該框架實質暴露該至少一導電終端;其中該框架係一支撐層,包含非導電材料,該非導電材料係選自於包括矽與二氧化矽組成的群組;至少一導電凸塊,設置於該框架中,其中該至少一導電凸塊電連接該至少一導電終端;一物件,具有至少一導電墊;以及一黏著層,設置於該半導體裝置與該物件之間。
- 如請求項7所述之半導體封裝,其中該框架包括:一中介層,設置於該支撐層與該半導體裝置之間。
- 如請求項7所述之半導體封裝,另包括至少一導電接頭,設置於該至少一導電凸塊與該至少一導電終端之間,並且該至少一導電接頭與該至少一導電凸塊形成至少一導電插塞。
- 如請求項9所述之半導體封裝,其中該至少一導電接頭與該至少一導電凸塊係由不同材料製成。
- 如請求項7所述之半導體封裝,其中該至少一導電凸塊之剖面圖具有一實質非球形側壁。
- 如請求項7所述之半導體封裝,其中該至少一導電凸塊之剖面圖具有一實質垂直側壁。
- 一種半導體封裝的製造方法,包括以下步驟:製備具有至少一導電終端的一半導體裝置;形成一框架於該半導體裝置上,其中該框架實質暴露該至少一導電終端;其中該框架係一支撐層,包含非導電材料,該非導電材料係選自於包括矽與二氧化矽組成的群組;以及形成至少一導電凸塊於該框架中,其中該至少一導電凸塊電連接該至少一導電終端。
- 如請求項13所述之半導體封裝的製造方法,其中形成一框架於該半導體裝置上的步驟包括:形成該支撐層於該半導體裝置上;形成一蝕刻遮罩層,具有至少一開口於該支撐層上,其中該至少一開口係設置於該至少一導電終端上方;以及進行一蝕刻製程,藉由使用該蝕刻遮罩層,以形成至少一開孔於該支撐層中,其中該至少一開孔暴露該至少一導電終端。
- 如請求項13所述之半導體封裝的製造方法,其中形成一框架於該半導體裝置上的步驟包括:形成一中介層於該半導體裝置上;形成該支撐層於該中介層上;形成一蝕刻遮罩層,具有至少一開口於該支撐層上,其中該至少一開口係設置於該至少一導電終端上方;以及進行一蝕刻製程,藉由使用該蝕刻遮罩層,以形成至少一開孔於該支撐層中,其中該至少一開孔暴露該至少一導電終端。
- 如請求項13所述之半導體封裝的製造方法,其中形成至少一導電凸塊於該框架中的步驟包括進行一鍍膜製程。
- 如請求項13所述之半導體封裝的製造方法,另包括以下步驟:製備一物件,具有至少一導電墊;以及以一黏著層附接該半導體裝置至該物件,該黏著層設置於該半導體裝置與該物件之間,其中該等導電墊電連接該至少一導電凸塊。
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