CN107634043A - 半导体装置、半导体封装及其制造方法 - Google Patents

半导体装置、半导体封装及其制造方法 Download PDF

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Publication number
CN107634043A
CN107634043A CN201610999452.4A CN201610999452A CN107634043A CN 107634043 A CN107634043 A CN 107634043A CN 201610999452 A CN201610999452 A CN 201610999452A CN 107634043 A CN107634043 A CN 107634043A
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China
Prior art keywords
conductive
framework
semiconductor device
projection
supporting layer
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CN201610999452.4A
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English (en)
Inventor
林柏均
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Nanya Technology Corp
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Nanya Technology Corp
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Publication of CN107634043A publication Critical patent/CN107634043A/zh
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Abstract

本公开提供一种半导体装置、半导体封装及其制造方法。在本公开的实施例中，该半导体装置包含一集成电路晶粒；设置于该集成电路晶粒上的至少一导电终端；设置于该集成电路晶粒上的一框架，其中该框架实质暴露该至少一导电终端；以及设置于该框架中的至少一导电凸块，其中该至少一导电凸块电连接该至少一导电终端。

Description

半导体装置、半导体封装及其制造方法
技术领域
本公开涉及一种具有导电凸块的半导体装置及其制造方法，其中半导体装置具有非常精细的间距(fine-pitch)、高散热特性、低翘曲、以及最小化的凸块工艺应力(bumpingstress)。
背景技术
集成电路(IC)结构的封装技术持续发展，以符合微小化与安装可信赖度(mounting reliability)的要求。近来，由于电子产品对微小化与高功能需求，此一技术领域已公开各种技术，以因应该等需求。
如所周知，半导体晶片在操作时会产生热量。在操作过程中，随着半导体的温度升高与下降，硅与金属或金属物质之间不同的热膨胀系数可在半导体晶片中造成应力，此一现象在半导体晶片操作过程中会显著恶化晶片中硅/金属接合的完整性与可信赖度。当操作温度改变时，个别材料的位移改变；若热膨胀系数差异造成的应力无法释放，则可能造成封装结构的断裂。
再者，来自晶片操作的热量通常造成集成电路结构的功能障碍。当晶片温度增加时，其可能相对影响小剖面的接线，因而破坏集成电路结构的正常功能。因此，近年来，随着半导体封装的微小化，集成电路结构中的散热问题已吸引越来越多的关注。
一般而言，封装产业中使用两种不同的信号接头接合(signal joint binding)方法，分别公知的打线接合(wire bonding，WB)与进阶的倒装芯片接合(flip chip bonding，FCB)。在安装至应用印刷电路板(PCB)或其他逻辑封装上之前，此等接合方法用于形成IC封装。
只要半导体装置设计考虑线回路(wire looping)，打线接合技术的成本低且工艺可变化，因而仍为最广泛用于IC组装产业中的信号接头(signal joint)。当面临打线接合过多问题时，SiP(系统封装)模块与硅间隔物一并采用打线接合。
此外，依照接头尺寸/间距/高度以及应用领域，存有不同的FCB构造。不论FCB型式，相较于打线接合封装，使用FCB工艺的主要效应为热/电效能较高且封装尺寸架构较小。特别地，由于输入/输出(I/O)数量非常多，大部分的逻辑晶粒使用FCB工艺。
上文的「现有技术」说明仅是提供背景技术，并未承认上文的「现有技术」说明公开本公开的标的，不构成本公开的现有技术，且上文的「现有技术」的任何说明均不应作为本案的任一部分。
发明内容
本公开涉及一种具有导电凸块的半导体装置及其制造方法，其中半导体装置具有非常精细的间距(fine-pitch)、高散热特性、低翘曲、以及最小化的凸块工艺应力(bumpingstress)。
本公开提供一种半导体装置。在本公开的实施例中，该半导体装置包括：一集成电路晶粒；至少一导电终端，设置于该集成电路晶粒上；一框架，设置于该集成电路晶粒上，其中该框架实质暴露该至少一导电终端；以及至少一导电凸块，设置于该框架中，其中该至少一导电凸块电连接该至少一导电终端。
在本公开的实施例中，该框架是一支撑层，包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组。
在本公开的实施例中，该框架包括：一支撑层，包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组；以及一中介层，设置于该支撑层与该集成电路晶粒之间。
在本公开的实施例中，该半导体装置另包括至少一导电接头，设置于该至少一导电凸块与该至少一导电终端之间，并且该至少一导电接头与该至少一导电凸块形成至少一导电插塞。
在本公开的实施例中，该至少一导电接头与该至少一导电凸块由不同材料制成。
在本公开的实施例中，该至少一导电凸块的剖面图具有一实质非球形侧壁。
在本公开的实施例中，该至少一导电凸块的剖面图具有一实质垂直侧壁。
本公开另提供一种半导体封装。在本公开的实施例中，该半导体封装包括：一半导体装置，具有至少一导电终端；一框架，设置于该半导体装置上，其中该框架实质暴露该至少一导电终端；至少一导电凸块，设置于该框架中，其中该至少一导电凸块电连接该至少一导电终端；一物件，具有至少一导电垫；以及一粘着层，设置于该半导体装置与该物件之间。
在本公开的实施例中，该框架是一支撑层，包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组。
在本公开的实施例中，该框架包括：一支撑层，包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组；以及一中介层，设置于该支撑层与该集成电路晶粒之间。
在本公开的实施例中，该半导体封装另包括至少一导电接头，设置于该至少一导电凸块与该至少一导电终端之间，并且该至少一导电接头与该至少一导电凸块形成至少一导电插塞。
在本公开的实施例中，该至少一导电接头与该至少一导电凸块由不同材料制成。
在本公开的实施例中，该至少一导电凸块的剖面图具有一实质非球形侧壁。
在本公开的实施例中，该至少一导电凸块的剖面图具有一实质垂直侧壁。
本公开另提供一种半导体封装的制造方法。在本公开的实施例中，该半导体封装的制造方法包括以下步骤：制备具有至少一导电终端的一半导体装置；形成一框架于该半导体装置上，其中该框架实质暴露该至少一导电终端；以及形成至少一导电凸块于该框架中，其中该至少一导电凸块电连接该至少一导电终端。
本公开另提供一种半导体封装的制造方法。在本公开的实施例中，该半导体封装的制造方法包括以下步骤：制备具有至少一导电终端的半导体装置；形成具有至少一开孔的一框架与导电接头于该半导体装置上，其中该至少一开孔与该导电接头设置于该至少一导电终端上方；以及形成至少一导电凸块于该框架的该至少一开孔中，其中该至少一导电凸块电连接该至少一导电终端。
在本公开的实施例中，形成一框架于该半导体装置上的步骤包括：形成一支撑层于该半导体装置上，该支撑层包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组；形成一蚀刻掩模层，具有至少一开口于该支撑层上，其中该至少一开口设置于该至少一导电终端上方；以及进行一蚀刻工艺，通过使用该蚀刻掩模层，以形成至少一开孔于该支撑层中，其中该至少一开孔暴露该至少一导电终端。
在本公开的实施例中，形成一框架于该半导体装置上的步骤包括：形成一中介层于该半导体装置上；形成一支撑层于该中介层上，该支撑层包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组；形成一蚀刻掩模层，具有至少一开口于该支撑层上，其中该至少一开口设置于该至少一导电终端上方；以及进行一蚀刻工艺，通过使用该蚀刻掩模层，以形成至少一开孔于该支撑层中，其中该至少一开孔暴露该至少一导电终端。
在本公开的实施例中，形成至少一导电凸块于该框架中的步骤包括进行一镀膜工艺。
在本公开的实施例中，该制造方法另包括以下步骤：
制备一物件，具有至少一导电垫；以及以一粘着层附接该半导体装置至该物件，该粘着层设置于该半导体装置与该物件之间，其中该等导电垫电连接该至少一导电凸块。
在本公开的一些实施例中，该框架定义导电凸块的边界，亦即本公开在形成凸块之前先形成该框架。在本公开的实施例中，通过微影工艺与蚀刻工艺，形成该框架中的该至少一开孔，其可形成极精细间距的至少一开孔(该导电凸块)，并且可形成具非常精细尺寸的导电凸块。因此，本公开可实施具有高输入/输出密度的半导体装置。
在本公开的一些实施例中，导电凸块受到硅或氧化硅的框架所环绕；相对地，现有技术的凸块由树脂环绕。由于硅或氧化硅的框架的导热性高于树脂，因而该框架具有高散热性质。此外，硅或氧化硅的框架的强度与刚度(stiffness)皆高于树脂，半导体装置与框架整体具有高应力(造成导电凸块受到较低的热应力)，并且可减少半导体装置的翘曲。
在现有技术中，模塑料与粘着层在集成电路晶粒的电路部分形成界面，因而在集成电路晶粒的电路部分易于发生破裂。相对地，在本公开的实施例中，模塑料与粘着层在没有电路的框架形成界面，因而可避免在集成电路晶粒中发生晶粒破裂。
附图说明
参阅详细说明与权利要求结合考虑附图时，可得以更全面了解本申请案的公开内容，附图中相同的元件符号是指相同的元件。
图1是一剖面示意图，例示本公开实施例的半导体封装。
图2是一剖面示意图，例示本公开实施例的半导体封装。
图3是一剖面示意图，例示本公开实施例的半导体封装。
图4是一剖面示意图，例示本公开实施例的半导体封装。
图5至图10是剖面示意图，例示本公开实施例的晶片封装的制造方法。
图11至图16是剖面示意图，例示本公开实施例的晶片封装的制造方法。
图17至图22是剖面示意图，例示本公开实施例的晶片封装的制造方法。
图23至图28是剖面示意图，例示本公开实施例的晶片封装的制造方法。
其中，附图标记说明如下：
10A 集成电路晶粒
11 基板部
13 电互连部
13' 电互连部
90 模塑料
100A 半导体封装
100B 半导体封装
100C 半导体封装
100D 半导体封装
130A 框架
130B 复合框架
131 中介层
133 支撑层
135A 复合叠层
135B 复合叠层
140 导电凸块
140' 导电凸块
141 导电终端
141' 导电终端
143 导电接头
145 复合插塞
150 蚀刻掩模层
151 开口
153 开孔
200 物件
201 导电垫
203 粘着层
220 焊球
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
「一实施例」、「实施例」、「例示实施例」、「其他实施例」、「另一实施例」等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用「在实施例中」一语并非必须指相同实施例，然而可为相同实施例。
本发明涉及一种具有导电凸块(bump)的半导体封装及其制造方法。为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制本领域技术人员已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的较佳实施例详述如下。然而，除了详细说明之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容，而是由权利要求定义。
图1是一剖面示意图，例示本公开实施例的半导体封装。在本公开的实施例中，半导体封装100A包括具有多个导电终端141的集成电路晶粒10A；设置于集成电路晶粒10A上的框架130A；以及设置于框架130A中的多个导电凸块140，其中框架130A实质暴露该等导电终端141，以及该等导电凸块140电连接该等导电终端141。在本公开的实施例中，半导体封装100A另包括具有多个导电垫201的物件200；设置于集成电路晶粒10A与物件200之间的粘着层203；以及囊封集成电路晶粒10A的模塑料90。
在本公开的实施例中，集成电路晶粒10A是包含多个集成电路晶粒的集成电路晶圆。在本公开的实施例中，集成电路晶粒10A是晶圆上的多个集成电路晶粒其中之一。在本公开的实施例中，集成电路晶粒10A是从晶圆分割的集成电路晶粒。在本公开的实施例中，集成电路晶粒10A是存储器晶片，例如DRAM晶片或是快闪存储器晶片。已知存储器晶片包括用于定址(addressing)多个存储器胞元的位址输入终端、用于输入资料至存储器胞元/自存储器胞元输出资料的资料输入/输出终端、以及电源供应终端。
在本公开的实施例中，集成电路晶粒10A包含基板部11与设置于基板部11上方的电互连部13。在本公开的实施例中，基板部11可包含硅晶圆。例如，基板部11可包含单晶硅晶圆、包含碳化硅(SiC)层或硅锗(SiGe)层的块状硅晶圆、或包含绝缘层的绝缘体覆硅(silicon-on-insulator，SOI)晶圆。在本实施例中，基板部11为单晶硅块状晶圆。在本公开的实施例中，至少一集成电路晶粒10A可包含多个单元装置，其可形成于基板部11中以及/或基板部11上，并且该等单元装置可包含金属氧化物半导体(metal-oxide-semiconductor，MOS)晶体管。
在本公开的实施例中，集成电路晶粒10A可另包含设置于基板部11与模塑料90之间的第一电互连部(未绘示于附图中)，而电互连部13作为第二电互连部。在本公开的实施例中，基板部11可视需要包含贯穿硅通道(未绘示于附图中)，将第一电互连部电连接至第二电互连部。
在本公开的实施例中，框架130A为支撑层，由选自于包括硅与二氧化硅所组成的群组的非导电材料形成。在本公开的实施例中，框架130A定义导电凸块140的边界，导电凸块140的剖面图具有实质非球形侧壁。在本公开的实施例中，该等导电凸块140的剖面图具有实质垂直的侧壁。在本公开的实施例中，物件200为封装电路基板、硅/玻璃插入件、或另一集成电路晶粒；其中该等导电凸块140分别附接至该等导电垫201。在本公开的实施例中，粘着层300为各向异性各向同性导电膜(anisotropic conductive film，ACF)、各向异性各向同性导电粘着物(anisotropic conductive adhesive，ACA)、非导电膜/浆(nonconductive film/paste，NCF/NCP)、底胶填充物(uderfill，UF)、模制底胶填充物(molding uderfill，MUF)等等。ACF或ACA包括绝缘膜或绝缘粘着物，其中导电粒子分散于绝缘膜或绝缘粘着物内。NCF/NCP或UF/MUF包括绝缘膜或粘着物，其中非导电粒子分散于绝缘膜/粘着物内。
在本公开的一些实施例中，导电凸块140由硅或氧化硅的框架130A环绕；相对地，现有技术的凸块由树脂环绕。由于硅或氧化硅的框架130A的导热性高于树脂，因而框架130A具有高散热性质。此外，硅或氧化硅的框架130A的强度或刚度(stiffness)皆高于树脂，集成电路晶粒10A与框架130A整体具有高应力(造成导电凸块140受到较低的热应力)，并且可减少集成电路晶粒10A的翘曲。
在现有技术中，模塑料与粘着层在集成电路晶粒的电路部分形成界面，因而在集成电路晶粒的电路部分易于发生破裂。相对地，在本公开的实施例中，模塑料90与粘着层203在没有电路的框架130A形成界面，因而可避免在集成电路晶粒10A中发生晶粒破裂。
图2是一剖面示意图，例示本公开实施例的半导体封装。图2中的半导体封装100B类似于图1所示的半导体封装100A，差别在于半导体封装100B使用复合框架(compositeframe)130B。在本公开的实施例中，复合框架130B包括中介层131与支撑层133，其中中介层131设置于支撑层133与集成电路晶粒10A之间。在本公开的实施例中，支撑层133包含非导电材料，该非导电材料选自于包括硅与二氧化硅所组成的群组。在本公开的实施例中，中介层131为集成电路晶粒10A的保护层或粘胶层，用于改良支撑层133与集成电路晶粒之间的粘附。
图3是一剖面示意图，例示本公开实施例的半导体封装。图3的半导体封装100C类似于图2的半导体封装100B，差别在于半导体封装100C使用复合插塞(composite plug)145，以电连接该等导电终端141与该等导电垫201。在本公开的实施例中，该等复合插塞145各自包括导电接头143与导电凸块140'，其中导电凸块140'设置于导电接头143与导电垫201之间。在本公开的实施例中，该等导电接头143与该等导电凸块140'由导电材料工艺，例如铜与锡。在本公开的实施例中，该等导电接头143与该等导电凸块140'由不同的导电材料工艺，例如导电接头143由铜制成，导电凸块140'由锡制成。
图4是一剖面示意图，例示本公开实施例的半导体封装。图4的半导体封装100D类似于图2的半导体封装100B，差别在于半导体封装100D的集成电路晶粒10B使用嵌置的导电终端141'。在本公开的实施例中，集成电路晶粒10B包括基板部11与设置于基板部11上的电互连部13'。在图4中，集成电路晶粒10B的嵌置的导电终端141'设置于电互连部13'中，而在图2中，集成电路晶粒10A的导电终端141设置于电互连部13上方
图5至图10是剖面示意图，例示说明本公开实施例的晶片封装100B的制造方法。
参阅图5，通过沉积、微影以及蚀刻工艺，在基板部11上形成电互连部13。接着，通过包含沉积、微影与蚀刻工艺，在电互连部13上形成多个导电终端141，以形成集成电路晶粒10A；之后，通过沉积工艺，在集成电路晶粒10A上形成保护层131A。在本公开的实施例中，基板部11可包含晶体管，该晶体管设置于受到隔离结构环绕的主动区域(active area，AA)中，该隔离结构例如浅沟槽隔离(shallow trench isolation，STI)。在本公开的实施例中，通过后段金属化技术，在基板部11上形成电互连部13。
参阅图6，在集成电路晶粒10A上形成支撑层133，其中支撑层133由非导电材料形成，该非导电材料选自于包括硅与二氧化硅所组成的群组。在本公开的实施例中，通过融合接合技术，在集成电路晶粒10A上形成支撑层133。融合接合技术的细节公开于文献(AnOverview of Patterned Metal/Dielectric Surface Bonding:Mechanism,Alignmentand Characterization,J.Electrochem.Soc.2011volume 158,issue 6,P81-P86)，其全文合并于本文中做为参考并且将不再重述。
参阅图7，通过微影工艺在支撑层133上形成蚀刻掩模层150，例如具有多个开口151的光致抗蚀剂层，其中该等开口151设置于该等导电终端141上方。接着，进行蚀刻工艺(例如干蚀刻工艺)，通过使用蚀刻掩模层150而于支撑层133中形成多个开孔153，其中该等开孔153暴露该等终端141。
参阅图8，剥除蚀刻掩模层150，并且通过金属镀膜工艺在支撑层133的该等开孔153中形成多个导电凸块140，其中该等导电凸块140分别电连接该等导电终端141。在本公开的实施例中，支撑层133与该等开孔153作为定义导电凸块140的边界的框架；由于该等开孔153由干蚀刻工艺形成，因而导电凸块140的剖面图具有实质非球形侧壁。在本公开的实施例中，由于该等开孔153由干蚀刻工艺形成，因而该等导电凸块140的剖面图具有实质垂直的侧壁。
参阅图9，将图8的制品(article)翻转并且附接至具有多个导电垫201的物件200，其中粘着层203设置于集成电路晶粒10A与物件200之间。接着，形成模塑料90以囊封集成电路晶粒10A，并且于物件200上形成多个焊球220，以形成半导体封装100B，如图10所示。
在本公开的实施例中，框架130B定义该等导电凸块140的边界，亦即本公开在形成凸块140之前先形成框架130B。在本公开的实施例中，通过微影工艺与蚀刻工艺在框架130B中形成开孔153，该微影工艺与蚀刻工艺可形成极精细间距的开孔153(导电凸块140)，并且可形成非常精细尺寸的导电凸块140。因此，本公开可实现具有高输入/输出密度的半导体装置。
在本公开的实施例中，可通过图5至图10公开的工艺，实质制造半导体封装100A，其中保护层131A与支撑层133应包含相同材料，例如氧化硅或硅。
在本公开的实施例中，可通过图5至图10公开的工艺，实质制造半导体封装100D，其中该等导电终端141形成于电互连部13中。
图11至图16是剖面示意图，例示本公开实施例的晶片封装100B的制造方法。
参阅图11，通过沉积、微影以及蚀刻工艺，在基板部11上形成电互连部13。接着，通过沉积、微影与蚀刻工艺，在电互连部13上形成多个导电终端141，以形成集成电路晶粒10A；之后，附接粘胶层131B于集成电路晶粒10A上。
参阅图12，在集成电路晶粒10A上形成支撑层133，其中支撑层133包含非导电材料，该非导电材料选自于包括硅与二氧化硅所组成的群组。
参阅图13，通过微影工艺在支撑层133上形成蚀刻掩模层150，例如具有多个开口151的光致抗蚀剂层，其中该等开口151设置于该等导电终端141上方。接着，通过使用蚀刻掩模层150，进行蚀刻工艺(例如干蚀刻工艺)，以形成多个开孔153于支撑层133中，其中该等开孔153暴露该等导电终端141。
参阅图14，剥除蚀刻掩模层150，并且进行金属镀膜工艺，以形成多个导电凸块140于支撑层133的多个开孔153中，其中该等导电凸块140电连接该等导电终端141。在本公开的实施例中，支撑层133作为框架，定义导电凸块140的边界，导电凸块140的剖面图具有实质非球形侧壁。在本公开的实施例中，该等导电凸块140的剖面图具有实质垂直的侧壁。
参阅图15，将图14的制品翻转且附接至具有多个导电垫201的物件200，其中粘着层203设置于集成电路晶粒10A与物件200之间。接着，形成模塑料90以囊封集成电路晶粒10A，并且形成多个焊球220于物件200上，以形成半导体封装100B，如图16所示。
图17至图22是剖面示意图，例示本公开实施例的晶片封装100B的制造方法。
参阅图17，通过沉积、微影以及蚀刻工艺，在基板部11上形成电互连部13。接着，通过沉积、微影以及蚀刻工艺，在电互连部13上形成多个导电终端141，以形成集成电路晶粒10A。接着，附接复合叠层(composite laminate)135A至集成电路晶粒10A上，如图18所示。在本公开的实施例中，复合叠层135B包括粘胶层131；设置于粘胶层131上的支撑层133；以及设置于粘胶层131与支撑层133之间的多个导电接头143。
参阅图19，通过微影工艺在支撑层133上形成蚀刻掩模层150，例如具有多个开口151的光致抗蚀剂层，其中该等开口151设置于该等导电终端141上方。接着，通过使用蚀刻掩模层150而进行蚀刻工艺(例如干蚀刻工艺)，以于支撑层133中形成多个开孔153，其中该等开口153暴露该等导电终端141。
参阅图20，剥除蚀刻掩模层150，并且进行金属镀膜工艺以形成多个导电凸块140于支撑层133的多个开孔153中，其中该等导电凸块电连接多个导电终端141。在本公开的实施例中，支撑层133作为框架，定义导电凸块140的边界，导电凸块140的剖面图具有实质非球形侧壁。在本公开的实施例中，该等导电凸块140的剖面图具有实质垂直的侧壁。
参阅图21，将图20的制品翻转并且附接至具有多个导电垫201的物件200，其中粘着层203设置于集成电路晶粒10A与物件200之间。接着，形成模塑料90以囊封集成电路晶粒10A，并且形成多个焊球220于物件200上，因而形成半导体封装100B，如图22所示。
图23至图28是剖面示意图，例示本公开实施例的晶片封装100C的制造方法。
参阅图23，通过沉积、微影以及蚀刻工艺，在基板部11上形成电互连部13。接着，通过沉积、微影以及蚀刻工艺，在电互连部13上形成多个导电终端141，以形成集成电路晶粒10A。接着，附接复合叠层(composite laminate)135B至集成电路晶粒10A上，如图24所示。在本公开的实施例中，复合叠层135B包括粘胶层131；设置于粘胶层131上的支撑层133；以及设置于支撑层133中的多个导电接头143。在本公开的实施例中，导电接头143可视需要形成于粘胶层131中。
参阅图25，通过微影工艺在支撑层133上形成蚀刻掩模层150，例如具有多个开口151的光致抗蚀剂层，其中该等开口151设置于该等导电终端141上方。接着，通过使用蚀刻掩模层150而进行蚀刻工艺(例如干蚀刻工艺)，以于支撑层133中形成多个开孔153，其中该等开口153暴露该等导电终端141。
参阅图26，剥除蚀刻掩模层150，并且进行金属镀膜工艺以形成多个导电凸块140'于支撑层133的多个开孔153中，其中该等导电凸块140'经由多个导电接头143而电连接多个导电终端141，导电接头143与导电凸块140'形成复合插塞145。在本公开的实施例中，支撑层133作为框架，定义复合插塞145的边界，复合插塞145的剖面图具有实质非球形侧壁。在本公开的实施例中，复合插塞145的剖面图具有实质垂直的侧壁。
参阅图27，将图26的制品翻转并且附接至具有多个导电垫201的物件200，粘着层203设置于集成电路晶粒10A与物件200之间。接着，形成模塑料90以囊封集成电路晶粒10A，并且形成多个焊球220于物件200上，因而形成半导体封装100C，如图28所示。
本公开提供一种半导体装置。在本公开的实施例中，该半导体装置包括：一集成电路晶粒；至少一导电终端，设置于该集成电路晶粒上；一框架，设置于该集成电路晶粒上，其中该框架实质暴露该至少一导电终端；以及至少一导电凸块，设置于该框架中，其中该至少一导电凸块电连接该至少一导电终端。
本公开另提供一种半导体封装。在本公开的实施例中，该半导体封装包括：一半导体装置，具有至少一导电终端；一框架，设置于该半导体装置上，其中该框架实质暴露该至少一导电终端；至少一导电凸块，设置于该框架中，其中该至少一导电凸块电连接该至少一导电终端；一物件，具有至少一导电垫；以及一粘着层，设置于该半导体装置与该物件之间。
本公开另提供一种半导体封装的制造方法。在本公开的实施例中，该半导体封装的制造方法包括以下步骤：制备具有至少一导电终端的一半导体装置；形成一框架于该半导体装置上，其中该框架实质暴露该至少一导电终端；以及形成至少一导电凸块于该框架中，其中该至少一导电凸块电连接该至少一导电终端。
本公开另提供一种半导体封装的制造方法。在本公开的实施例中，该半导体封装的制造方法包括以下步骤：制备具有至少一导电终端的半导体装置；形成具有至少一开孔的一框架与导电接头于该半导体装置上，其中该至少一开孔与该导电接头设置于该至少一导电终端上方；以及形成至少一导电凸块于该框架的该至少一开孔中，其中该至少一导电凸块电连接该至少一导电终端。
在本公开的一些实施例中，该框架定义导电凸块的边界，亦即本公开在形成凸块之前先形成该框架。在本公开的实施例中，通过微影工艺与蚀刻工艺，形成该框架中的该至少一开孔，其可形成极精细间距的至少一开孔(该导电凸块)，并且可形成具非常精细尺寸的导电凸块。因此，本公开可实施具有高输入/输出密度的半导体装置。
在本公开的一些实施例中，导电凸块受到硅或氧化硅的框架所环绕；相对地，现有技术的凸块由树脂环绕。由于硅或氧化硅的框架的导热性高于树脂，因而该框架具有高散热性质。此外，硅或氧化硅的框架的强度与刚度(stiffness)皆高于树脂，半导体装置与框架整体具有高应力(造成导电凸块受到较低的热应力)，并且可减少半导体装置的翘曲。
在现有技术中，模塑料与粘着层在集成电路晶粒的电路部分形成界面，因而在集成电路晶粒的电路部分易于发生破裂。相对地，在本公开的实施例中，模塑料与粘着层在没有电路的框架形成界面，因而可避免在集成电路晶粒中发生晶粒破裂。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的精神与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
再者，本申请案的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。本领域技术人员可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，此等工艺、机械、制造、物质组成物、手段、方法、或步骤包含于本申请案的权利要求内。

Claims (19)

1.一种半导体装置，包括：
一集成电路晶粒；
至少一导电终端，设置于该集成电路晶粒上；
一框架，设置于该集成电路晶粒上，其中该框架实质暴露该至少一导电终端；以及
至少一导电凸块，设置于该框架中，其中该至少一导电凸块电连接该至少一导电终端。
2.如权利要求1所述的半导体装置，其中该框架是一支撑层，包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组。
3.如权利要求1所述的半导体装置，其中该框架包括：
一支撑层，包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组；以及
一中介层，设置于该支撑层与该集成电路晶粒之间。
4.如权利要求1所述的半导体装置，还包括至少一导电接头，设置于该至少一导电凸块与该至少一导电终端之间，并且该至少一导电接头与该至少一导电凸块形成至少一导电插塞。
5.如权利要求4所述的半导体装置，其中该至少一导电接头与该至少一导电凸块由不同材料制成。
6.如权利要求1所述的半导体装置，其中该至少一导电凸块的剖面图具有一实质非球形侧壁。
7.如权利要求1所述的半导体装置，其中该至少一导电凸块的剖面图具有一实质垂直侧壁。
8.一种半导体封装，包括：
一半导体装置，具有至少一导电终端；
一框架，设置于该半导体装置上，其中该框架实质暴露该至少一导电终端；
至少一导电凸块，设置于该框架中，其中该至少一导电凸块电连接该至少一导电终端；
一物件，具有至少一导电垫；以及
一粘着层，设置于该半导体装置与该物件之间。
9.如权利要求8所述的半导体封装，其中该框架是一支撑层，包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组。
10.如权利要求8所述的半导体封装，其中该框架包括：
一支撑层，包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组；以及
一中介层，设置于该支撑层与该集成电路晶粒之间。
11.如权利要求8所述的半导体封装，还包括至少一导电接头，设置于该至少一导电凸块与该至少一导电终端之间，并且该至少一导电接头与该至少一导电凸块形成至少一导电插塞。
12.如权利要求11所述的半导体封装，其中该至少一导电接头与该至少一导电凸块由不同材料制成。
13.如权利要求8所述的半导体封装，其中该至少一导电凸块的剖面图具有一实质非球形侧壁。
14.如权利要求8所述的半导体封装，其中该至少一导电凸块的剖面图具有一实质垂直侧壁。
15.一种半导体封装的制造方法，包括以下步骤：
制备具有至少一导电终端的一半导体装置；
形成一框架于该半导体装置上，其中该框架实质暴露该至少一导电终端；以及
形成至少一导电凸块于该框架中，其中该至少一导电凸块电连接该至少一导电终端。
16.如权利要求15所述的半导体封装的制造方法，其中形成一框架于该半导体装置上的步骤包括：
形成一支撑层于该半导体装置上，该支撑层包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组；
形成一蚀刻掩模层，具有至少一开口于该支撑层上，其中该至少一开口设置于该至少一导电终端上方；以及
进行一蚀刻工艺，通过使用该蚀刻掩模层，以形成至少一开孔于该支撑层中，其中该至少一开孔暴露该至少一导电终端。
17.如权利要求15所述的半导体封装的制造方法，其中形成一框架于该半导体装置上的步骤包括：
形成一中介层于该半导体装置上；
形成一支撑层于该中介层上，该支撑层包含非导电材料，该非导电材料选自于包括硅与二氧化硅组成的群组；
形成一蚀刻掩模层，具有至少一开口于该支撑层上，其中该至少一开口设置于该至少一导电终端上方；以及
进行一蚀刻工艺，通过使用该蚀刻掩模层，以形成至少一开孔于该支撑层中，其中该至少一开孔暴露该至少一导电终端。
18.如权利要求15所述的半导体封装的制造方法，其中形成至少一导电凸块于该框架中的步骤包括进行一镀膜工艺。
19.如权利要求15所述的半导体封装的制造方法，还包括以下步骤：
制备一物件，具有至少一导电垫；以及
以一粘着层附接该半导体装置至该物件，该粘着层设置于该半导体装置与该物件之间，其中所述至少一导电垫电连接该至少一导电凸块。
CN201610999452.4A 2016-07-18 2016-11-01 半导体装置、半导体封装及其制造方法 Pending CN107634043A (zh)

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