CN1383197A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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Publication number
CN1383197A
CN1383197A CN02118367A CN02118367A CN1383197A CN 1383197 A CN1383197 A CN 1383197A CN 02118367 A CN02118367 A CN 02118367A CN 02118367 A CN02118367 A CN 02118367A CN 1383197 A CN1383197 A CN 1383197A
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China
Prior art keywords
hole
conducting resinl
intermediate connector
circuit substrate
semiconductor device
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CN02118367A
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English (en)
Inventor
东谷秀树
中村祯志
安藤大藏
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of CN1383197A publication Critical patent/CN1383197A/zh
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Abstract

本发明提供一种用导电胶将具有狭窄间距配置电极的半导体元件及电路基片高可靠性电气连接的半导体装置及制造这种半导体装置的制造方法。该制造方法包含以下各工序:在半导体部上形成多个半导体电极的工序;在电路基片上形成多个基片电极的工序;将半导体部及电路基片的一方粘接到由绝缘性材料组成的中间连接体上的第1粘接工序;在中间连接体上形成与多个半导体电极的位置及多个基片电极的位置对应的多个贯通孔的工序;通过各贯通孔将各半导体电极和各基片电极电气连接的工序;将半导体部及电路基片的另一方粘接到中间连接体上的第2粘接工序。

Description

半导体装置的制造方法及半导体装置
技术领域
本发明涉及将半导体元件高密度的封装在电路基片上的技术。
背景技术
半导体元件的封装密度已经很高，为了应对封装面积的减小和电极数的增加、近年来提出了各种各样的高密度封装方法。它的一个例子是将在电极部上形成了凸台部的半导体元件用倒装法安装在电路基片上的方法(美国专利第4,661,192号公报、特开平6-224259号公报)。图13是倒装法封装的现有的半导体装置的剖面图。
图13所示的现有的半导体装置由半导体元件901、电路基片907、将半导体元件901和电路基片907电气连接的突起电极905、导电胶909及密封树脂911组成。
电路基片907是所有层都是填隙式镀金属夹层孔(IVH：Interstitial ViaHole)结构的多层电路基片、为确保与半导体元件901的电气连接、设置了电极913。在半导体元件901上形成了多个电极903。在各个电极903上设有突起电极905、进一步导电胶909覆盖了它的一部分。半导体元件901和电路基片907由突起电极905将导电胶909按压在电极913上而电气连接一起。密封树脂911充填在半导体元件901和电路基片907之间、填埋二者的间隙。由此、将半导体元件901固定在电路基片907上。
以下，参照图14(a)～(e)、具体的说明现有的半导体装置的封装方法。
图14(a)示出半导体元件901。半导体元件901有电极903。首先，用引线接合法在电极903上形成凸台905。凸台905有2段突起的形状。它的形成步骤如下。首先，将在Au引线前端上形成的球(ball)热压在电极903上、形成2段突起的下段部。接着，移动毛细管、用形成的Au引线环形成上段部。在这种状态下，2段突起凸台的高度不匀、而且前端部也不平坦。因此，将2段突起凸台加压进行高度的均一化和前端部的平坦化。这样，在电极903上形成凸台905。
图14(b)是表示涂敷了导电胶909的半导体元件的图。导电胶909复印在凸台905上。具体的说，例如用刮刀刀片法在旋转园盘上涂敷均匀厚度的导电胶909、将凸台905放到涂敷过的导电胶909上、提升它进行复印。
图14(c)是表示对准前的半导体元件901和电路基片907的图。对准是为将半导体元件901上的凸台905和电路基片907上的电极913高精度连接而进行的。
图14(d)是表示对准后的半导体元件901和电路基片907的图。把凸台905上的导电胶909放到电路基片907的电极913上，使导电胶909加热硬化。由此，使凸台905和电极913电气性、物理性连接。
图14(e)是表示用树脂911密封后的半导体元件901和电路基片907的图。树脂911是环氧树脂型材料。在半导体元件901的周围及半导体元件901和电路基片907的间隙处注入树脂911、使树脂911硬化进行密封。这样，由电路基片907和半导体元件901的树脂模型化、完成将半导体元件901倒装连接在电路基片907上的现有的半导体装置。
发明内容
与图14(b)相关连、复印在各凸台905上的导电胶909的量对各个凸台905来说必然产生一定程度的偏差。因此，将半导体元件901的电极和电路基片907的电极913电气连接时，当将导电胶909复印量多的凸台905放到电极913上时，导电胶905就扩展到邻近的电极或者导电胶上，有时产生短路。这种情况在各电极903间及各电极913间处于狭窄的情况时就成为问题。
本发明的目的是对具有狭窄间距配置电极的半导体元件及电路基片、能够用导电胶实现高可靠性的电气连接。
采用本发明，制造将半导体部和电路基片电气连接的半导体装置的方法包含以下工序：在所述半导体部上形成多个半导体电极的工序；在所述电路基片上形成多个基片电极的工序；将所述半导体部和所述电路基片的一方连接到由绝缘性材料组成的中间连接体上的第1粘接工序；根据所述多个半导体电极的位置及所述多个基片电极的位置、在所述中间连接体上形成多个贯通孔的工序；通过各贯通孔、将各半导体电极和各基片电极电气连接的工序；将所述半导体部和所述电路基片的另一方粘接到所述中间连接体上的第2粘接工序。由此达到上述目的。
电气连接的所述工序，也可以包含以下工序：在所述多个半导体电极及所述多个基片电极的至少一方上形成多个凸台的工序；在所述各贯通孔上填充导电胶的工序；将各凸台埋没在所述各贯通孔内的所述导电胶中、通过所述多个凸台及所述导电胶、将各半导体电极和各基片电极电气连接的工序。
形成多个贯通孔的所述工序也可以包含以下工序：测量所述多个半导体电极的位置及所述多个基片电极的位置的至少一方、取得位置数据的工序；基于测量的所述位置数据、特定所述中间连接体上的多个位置的工序；在被特定的所述中间连接体上的各位置上、形成所述各贯通孔的工序。
所述多个半导体电极及所述多个基片电极的各个都是在表面上形成包含树脂的被膜的金属层、形成多个贯通孔的所述工序也可以是除去所述被膜、使所述金属层露出来。
形成多个贯通孔的所述工序也可以是形成使壁面倾斜的所述各贯通孔。
填充导电胶的所述工序也可以包含从所述各贯通孔的底部到开口部注入所述导电胶的工序和从所述开口部梳理规定数量的导电胶的工序。
注入导电胶的所述工序也可以对导电胶加压使之吐出、从所述各贯通孔的底部开始到开口部为止的注入。
所述第1粘接工序及所述第2粘接工序也可以是由加压将所述中间连接体粘接在所述半导体部及所述电路基片上、封锁所述各贯通孔。
所述导电胶含有导电性粒子和非导电的树脂，封锁所述各贯通孔的工序也可以包含：在所述中间连接体和所述半导体部及所述电路基片的至少一方的界面上设置仅能流出所述非导电性树脂的间隙的工序；由加压使所述导电胶致密化、使所述非导电性树脂从各贯通孔流出的工序；封锁所述导电性粒子残留下的所述各贯通孔的工序。
所述中间连接体进一步包含加压收缩材料、所述第1粘接工序及第2粘接工序也可以是由加压使所述中间连接体收缩、使所述导电胶致密化。
所述中间连接体进一步包含热硬化树脂，所述第1粘接工序由加热使包含热硬化树脂的所述中间连接体的一部分硬化、将所述半导体部及所述电路基片的一方粘接到所述中间连接体上。
所述第2粘接工序也可以由加热使所述中间连接体硬化、将所述半导体部及所述电路基片和所述中间连接体粘接。
还有，注入导电胶的所述工序也可以是在导电胶上加压、吐出大于从各贯通孔的容积减去被埋没的各凸台的容积的分量，而且，小于各贯通孔容积的分量的所述导电胶。
采用本发明的半导体装置，具有：有多个半导体电极的半导体部；有多个基片电极的电路基片；粘接在所述半导体部及所述电路基片上的、被夹持的、是由绝缘材料组成的中间连接体；有充填了导电胶的多个贯通孔；有通过各贯通孔内的所述导电胶、将各半导体电极及各基片电极电气连接的中间连接体。所述各半导体电极及所述各基片电极是在表面上形成包含树脂被膜的金属层、在所述各贯通孔内所述被膜被除去、与所述导电胶连接。由此、达到上述目的。
所述各贯通孔的壁面也可以倾斜。
在所述多个半导体电极及所述多个基片电极的至少一方也可以形成多个凸台。
所述多个凸台的每一个也可以是2段突起形状。
附图说明
图1(a)是表示实施方式1的半导体装置全部结构的剖面图。(b)是半导体装置的部分放大图。
图2(a)～(f)是说明半导体装置的第1制造工序的图。
图3(a)是在带有倾斜的、在中间连接体上形成的贯通孔周围的放大图。(b)是显示表面处理层的、在贯通孔内露出的部分的除去结果的图。
图4(a)～(e)是显示具有比下段部还大的凸台直径的凸台的形成顺序图。
图5是显示形成蘑菇状凸台的半导体元件的图。
图6(a)是显示在半导体元件和电路基片粘接前将导电胶充填在贯通孔内的中间连接体的图。(b)是显示将半导体元件和电路基片粘接后的中间连接体的图。
图7(a)是显示在与电路基片粘接后、与半导体元件粘接前，导电胶充填贯通孔的中间连接体的图。(b)是显示将电路基片和半导体元件粘接后的中间连接体的图。
图8是说明实施方式1的半导体装置的第2制造工序的图。
图9(a)是显示实施方式2的半导体装置的结构的剖面图。(b)是半导体装置的部分放大图。
图10是说明实施方式2的半导体装置的制造工序的图。
图11是显示实施方式2的变形例的半导体装置全部结构的剖面图。
图12是显示实施方式3的半导体装置全部结构的剖面图。
图13是倒装法封装的现有的半导体装置的剖面图。
图14(a)～(e)是说明现有的半导体装置封装工序的图。符号说明
101—半导体元件，103—电极，105—凸台，106—涂敷薄膜，107—中间连接体，109—贯通孔，111—导电胶，113—电路基片，115—电极，119—贯通孔(填隙式镀金属夹层孔)，120、130—电气连接部，121—布线层，123—绝缘层，125—导电体，801—半导体元件，802—电路基片，803—导线，804—电极，805—半导体元件的封装结构体，806—模制树脂，901—半导体元件，903—电极，905—凸台，907—电路基片，909—导电胶，911—密封树脂，913—电极。
具体实施方式
首先，本发明的半导体装置，用导电胶和凸台将半导体元件和电路基片电气的连接起来。进一步、本发明的半导体装置在半导体元件和电路基片之间设置有连接二者、具有与半导体元件的电极及电路基片的电极相对应形成的贯通孔的中间连接体。半导体元件和电路基片的电气连接由将凸台压入充填在贯通孔内的导电胶上进行。由于导电胶封入贯通孔内、能够防止导电胶扩展到相邻的电气连接产生的短路。
以下，参照附图、说明本发明的实施方式1～3。功能相同的构成要素注以相同的参照符号。
(实施方式1)
图1(a)示出实施方式1半导体装置100的全体构造的剖面图。半导体装置100由半导体元件101、中间连接体107、电路基片113和多个电气连接部120构成。
半导体元件101是封装在电路基片113上的元件、通过各电气连接部120与电路基片113电气的、物理的连接。
电路基片113、是所有层都具有填隙式镀金属夹层孔(IVH：InterstitialVia Hole)结构的树脂多层电路基片。电路基片113在成为绝缘层芯子123的任意位置上具有多个贯通孔119。图1(b)是半导体装置100的部分放大图。由于在贯通孔119中填充了导电体125、能确保分别设置在芯子123表面和背面的布线层121间的导通。由于在电路基片113上使用了全层IVH结构的树脂多层电路基片、能够更高密度的收容布线。进一步，由于全层IVH结构的树脂多层电路基片具有高耐压力性，当施加压力将半导体元件101封装在电路基片113上时，能够提高半导体元件101的封装成品率。
电气连接部120分别由作为半导体元件101外部电极的电极103、设在电极103上的凸台105、与电极103相对应设在电路基片113上的电极115和将凸台105和电极115连接起来的导电胶111组成。电气连接部120存在多个。对应的电极103和电极115、利用后述的中间连接体107电气连接。就是说，半导体元件101和电路基片113电气连接。由于用凸台105和导电胶111能够确保半导体元件101和电路基片113的电气连接、即使在半导体装置100上施加热冲击等的应力情况下，导电胶111也能吸收集中在半导体元件101和电路基片113连接部上的应力、不失去电气连接。由此，能确保稳定的电气连接。
中间连接体107设在半导体元件101和电路基片113之间。中间连接体107在与电极103及电极115对应的位置上具有为连接半导体元件101和电路基片113的贯通孔109。在贯通孔109的内部，配置有使电极103及电极115更密封的导电胶111和设在电极103上的凸台105。导电胶111由于贯通孔109的壁面抑制向水平方向的流出。由此，能够防止导电胶111扩展到邻接的电气连接部120，防止相邻电气连接部120间的短路。因此，电气连接部120能够以狭窄的间距配置，能以高密度连接半导体元件101和电路基片113。
在不存在中间连接体107的情况下，当施加热冲击等的温度应力时，应力将集中向半导体元件101和电路基片113连接的部分。但是，由于设置了中间连接体107，能够抑制这样的应力集中。这是因为半导体元件101的全面与中间连接体107粘接、能够回避应力仅仅加在粘接部分。应力是因为半导体元件101和电路基片113的热膨胀系数差产生的。特别是，中间连接体107最好由热膨胀系数在半导体元件101的热膨胀系数和电路基片113的热膨胀系数之间的材料形成。当将这样的中间连接体107设置的与半导体元件101和电路基片113粘附时，上述的因热膨胀系数差引起的应力能被中间连接体107吸收。这样，更能减低施加在半导体元件101和电路基片113的连接部的应力。
中间连接体107，例如，可以是焊接片等的电绝缘性树脂。但是，采用加热加压时能在厚度方向压缩的电气绝缘性基材更好。这是因为能够更加强固凸台105、导电胶111和电路基片113上的电极115间的连接。更具体的说明参照图2的(f)在后面叙述。作为能压缩的电气绝缘性基材，例如，可以采用将未硬化的环氧树脂含浸在芳族聚酰胺无纺布上使空孔残留下来的聚脂胶片、及将未硬化环氧树脂含浸在多孔质的薄膜基材上使空孔残留下来的薄膜基材。由于在这样的可压缩性电气绝缘基材中存在空孔、由加热·加压环氧树脂成分流出、空孔被树脂填埋。其结果，电气绝缘性基材沿厚度方向收缩。
其次，参照图2(a)～(f)说明半导体装置100(图1)的第1制造工序。
图2(a)是显示半导体元件101的图。首先，在半导体元件101上通过溅射形成为了进行半导体元件101向外部电气连接的金属层的电极103。电极103的材质一般与半导体元件101的布线材料相同，例如含微量硅、铜的铝。进一步，在电极103的表面上也可以设置由镍、铜、金等的各种电极材料构成的金属层。
接着，在这样形成的电极103上，形成具有2段突起形状的Au凸台105。不将凸台105形成在设在电路基片113上的电极115上，而形成在电极103上的理由是因为半导体元件101比电路基片113的表面平坦性优秀，形成的凸台105的高度偏差小，其结果，各电气连接部120的偏差也小，能够确保稳定的电气连接。此外，凸台105的形状和材料并不仅限于此。
说明具有2段突起形状凸台105的形成顺序。首先，将在Au前端上形成的球热压在电极103上，形成2段突起的下段部，就是说，形成与电极103连接一侧的那一段。接着，用使毛细管移动形成的Au引线环形成上段部(前端部)。在图中，前端部的凸台直径比下段部的凸台直径小。在这种状态下，2段突起凸台105的高度不是均一的，而且，前端部也缺乏平坦性。因此，将2段突起凸台105加压，进行高度的均一化及前端部的平坦化。这样，凸台105形成在电极103上。
其次，图2(b)是表示粘贴了中间连接体107的电路基片113的图。粘贴在电路基片113上后，在中间连接体107的相反一面上设有涂敷薄膜106。也可以预先在中间连接体107的一方的面上设置薄膜基材，而且，在相反的面上设置涂敷薄膜106，由在电路基片113的希望的位置上叠层薄膜基材，将中间连接体107粘贴向电路基片11上。作为叠层的条件，最好不使包含在中间连接体107内的热硬化树脂完全硬化。这是为了在以后的工序中，当将半导体元件101和中间连接体107叠层连接时能得到足够的粘接力。
接着图2(c)示出形成了多个贯通孔109的中间连接体107。更正确的说，贯通孔109贯通涂敷薄膜106  中间连接体107。贯通孔109最好用激光形成。激光加工进行直到电路基片113上的电极115露出为止。请留意最好使贯通孔109的壁面带有倾斜的形状。这是因为贯通孔109的壁面一旦带有倾斜、当充填导电胶111时，能够更容易的充填导电胶111。此外，当用激光形成贯通孔109时，涂敷薄膜106使用具有吸收用来加工的激光波长特性的材料。一般的说，是PET薄膜、PEN薄膜。
图3(a)是在中间连接体107上形成的带有倾斜贯通孔109的周围的放大图。由于贯通孔109的涂敷薄膜106一侧，即注入导电胶111一侧的开口径比贯通孔109的底部的开口径形成的大、贯通孔109的壁面倾斜。由此，导电胶111更容易充填。由图可以明白，贯通孔109形成的也贯通涂敷薄膜106。形成在电路基片113上的电极115是导电性金属层，一般是薄的铜层。为了防止铜的表面变质及提高与树脂的粘接力，在金属层的表面上通常存在由施加Cr、Zn、Ni等的被膜处理、有机防锈膜处理等的表面处理层116。表面处理层116的最表面是金属氧化被膜及树脂层。但是，表面处理层116妨碍在下面的工序中说明的填充贯通孔109的导电胶111(图2(d))内的导电性粒子与金属层的接触。因此，在贯通孔109的底层阻碍电气性的连接。就是说，表面处理层116从金属层电极115的表面变质和确保粘附性的观点看是必要的，但从贯通孔109底部电气连接的观点看是不希望的，存在这样一种需平衡折中的问题。
在本实施方式中，形成贯通孔109时除去表面处理层116。即使除去表面处理层116，在贯通孔109上填充导电胶后电极115也不产生表面变质等。由此，能够使导电胶内的导电性粒子与金属层可靠的接触。除去表面处理层116可以进行由药液、真空中的离子洗、干法刻蚀、还原气氛化下的氧化皮膜除去、氮气、氩气等惰性气氛下的喷沙(blast)加工等物理加工。这样，因为用溶融等方法除去表面处理层116，一方面能够确保电气的连接，另一方面没有必要像过去那样将表面处理层116尽可能的作薄，使制造变得容易。图3(b)是表示表面处理层116的、在贯通孔109内暴露部分的除去结果的图。由此，能够理解电极115暴露在贯通孔109内了。
此外，利用激光形成贯通孔109时，控制激光的能量、脉冲宽度、照射数等、在形成贯通孔109的同时也可以除去表面处理层116。还有，也可以用激光加工时产生的热使表面处理层116向金属层内部扩散，增加铜在贯通孔109底部露出的比例。采用这种方法，能够使导电胶和电极115可靠的电气连接。
如上所述，由除去存在于电极115表面的表面处理层，电路基片113上的布线、电极内，仅仅在电气连接部120(图1(b))、能够使电极115的金属层暴露出来。由此，能够解决上述的平衡折中问题。
在激光加工时，可以利用电极115位置的实测值决定激光照射的中间连接体107的位置。这是因为电极115形成的电路基片113由有机树脂组成，由于制造工艺过程中的热和压力容易产生尺寸变化，其结果，对于设计的电路基片113的图形尺寸产生了偏差。
电极115的实测值能够由从上面看电路基片113，测定电路基片113的基准点的位置得到。作为基准点，可以用预先设定在电路基片113上的位置检测用标记、也可以设定基准电极115、用它的边缘。这样将实测的基准点和电路基片113的设计的基准点的平面坐标上的变化量、反映在预先输入的设计加工位置数据上、补偿加工位置数据。基于补偿过的加工位置数据、由激光加工、在与电极115对应的中间连接体107的位置上高精度的形成贯通孔109。此外，在考虑没有位置偏差的情况下，也可以用设计值决定激光的照射位置。
进一步，同样的测定设在半导体元件101上的凸台105的位置，将它的位置数据反映在加工位置数据上进行补偿，能够形成更高精度的贯通孔109。由于由这种补偿，对应凸台105及电极115的位置，能够正确的形成贯通孔109，能够将位置对准时的对准容量设定的小些。因此，能够由电气连接部120(图1(b))，实现以狭窄的间距配置的半导体装置100(图1)。进一步，如果检测了电极115和凸台105两方的位置，即使是原来不能将凸台105与电极115对准的半导体元件101也能判别。由此，能够进一步提高成品率。进一步，由于这种判别是在半导体元件101封装到电路基片113前进行的，判定为不能封装的半导体元件101能够再利用做封装在别的电路基片113上的半导体元件。
接着，图2(d)示出填充导电胶111后的贯通孔109。导电胶111包含热硬化性树脂和导电性粒子。热硬化性树脂例如是苯酚、环氧树脂，起到黏合剂的功能。导电性粒子最好由金、银、铜、银钯、及这些的合金中至少1种组成、分散在热硬化树脂中。导电性粒子很少有在表面上的阻碍连接的氧化等变质层，能够实现高可靠性的电气连接。此外，涂敷薄膜106起到在胶填充工序中，防止导电胶111附着在中间连接体107的表面上的保护功能。
图2(e)是表示与半导体元件101对准后的电路基片113的图。由对准、能够将半导体元件101叠层在中间连接体107上构成。当对准时，涂敷薄膜106(图2(c))被剥离。当涂敷薄膜106剥离时导电胶111容易从中间连接体107的表面突出涂敷薄膜106厚度那样的量。这一突出的导电胶111，当将半导体元件101叠层在中间连接体107上时，有可能诱发相邻的电气连接部120间的短路。因此，突出部最好尽量的小，为此，在加工中在不断裂的限度内，最好采用尽可能薄的涂敷薄膜106。如果剥离了涂敷薄膜106，能够防止激光加工时的加工碎片附着在中间连接体107的表面上。
除减低涂敷薄膜106的厚度外，还将在导电胶111填充贯通孔109后，用橡胶等柔软的滑动辊梳理填充到涂敷薄膜106表面上的导电胶111，导电胶111最好是凹状填充、以使它不挂在涂敷薄膜106上。
由填充滑动辊印刷填充导电胶111时，导电胶从贯通孔的底面开始直到表面(开口部)致密的填充，然后，从贯通孔开口部梳理一定量的导电胶即可。在各工序中，由设定滑动辊硬度、滑动辊角度、滑动辊移动速度，能够使稳定的填充导电胶和梳理二者并存。
还有，也可以用分配法将导电胶111填充贯通孔109。所谓的「分配法」是从收容导电胶111的容器中，由空气压力等外压使得吐出希望数量的导电胶111的方法。使用分配法、能够在各贯通孔109内填充偏差小的导电胶111的同时，任意设定吐出时的压力、对微细贯通孔109设定高吐出压力、能够高密度的填充导电胶111。还有，如果将分配法和所述的由滑动辊的梳理工序并用、能够更进一步抑制填充量的偏差。
在贯通孔109内填充的导电胶111的分量，最好设定在大于贯通孔109的容积减去凸台105的体积，而且，小于贯通孔109的体积。填充在贯通孔109内的导电胶111的分量如果设定在这个范围内，在后面的工序中，当凸台105埋设(埋没)在导电胶111内时，能够抑制导电胶111从贯通孔109的溢出，能够将导电胶压缩、致密化。
图2(f)是表示叠层了半导体元件101的电路基片113的图。凸台105埋没在贯通孔109内的导电胶111上，使半导体元件101叠层在中间连接体107上。然后，由加热·加压，确保凸台105、导电胶111和电路基片113上的电极115之间的电气连接。
由于预先在贯通孔109的壁面上形成了倾斜，贯通孔109的壁面在叠层状态的加热·加压时，成为引导凸台105的导轨。由此，即使叠层位置多少有些偏离，其结果是凸台105并不从电路基片113上的电极115分离。还有，由于是在凸台105被埋设(埋没)在贯通孔109内部的状态下加热加压的、能够抑制加热·加压时半导体元件101和电路基片113的位置偏离。
这样，一旦将凸台105埋没在贯通孔109内的导电胶111内，凸台105与导电胶111的接触面积变大，能够更稳定的电气连接。进一步，即使应力集中在连接部分的情况下，最好也能成为凸台105和导电胶111的连接难于退化的结构。这特别是，与高度是1段的情况相比，具有更高的2段突起形状的凸台105的情况下是显著的。进一步，也可以由这时的加热·加压、在凸台105的导电胶111压缩、使导电胶111内的导电性粒子致密化。由此，凸台105、导电胶111和电路基片113上的电极115之间的电气连接更稳定、这是理想的。
在由加热·加压使导电胶111致密化的情况下、最好是包含在导电胶111内的导电性粒子不沿面方向流出，就是说，不沿半导体元件101扩展的方向流出的那样、一面封锁贯通孔的开口部一面进行致密化。就是说，为了因压缩力使导电胶111致密化，在中间连接体107和半导体元件101的界面或者在中间连接体107与电路基片113的界面上设置仅仅使包含在导电胶111内的树脂成分流出、导电性粒子不流出的间隙。
设在中间连接体107和半导体元件101界面上的间隙形成的使露出在中间连接体107表面的未硬化树脂表面粗化，能够形成的将表面粗糙度设定在包含在导电胶111内的导电性粒子直径以下。另一方面，设在中间连接体107和电路基片113界面上的间隙，由于预先将形成在电路基片113表面的电极115的表面粗化、在与中间连接体107的界面上设置希望的间隙是简便的。还有，作为中间连接体107使用内部含空孔的多孔质材料，即使在仅仅使导电胶111内含有的树脂成分流出到中间连接体107中的情况下，也能得到同样的效果。
在图2(b)所示的工序中，热硬化树脂没有完全硬化配置在电路基片113上的中间连接体107，在图2(f)的工序中，由将凸台105被埋设(埋没)在导电胶111内后的加热·加压工序，在厚度方向收缩使导电胶111更压缩的同时，完全硬化。由此，凸台105、导电胶111、和电路基片113上的电极115间的接合能够更强固。由此，半导体元件101和中间连接体107更强固的粘接、由这个强固的粘接力抑制半导体元件101从电路基片113的剥离。从图2(f)所示的在加热·加压工序下确保与半导体元件101的粘接力的观点看、在图2(b)所示的状态下、中间连接体107的热硬化性树脂的硬化率低于50％更好。硬化率可由温度和时间控制。
由以上说明的工序、能够得到实施方式1的半导体装置100(图1)。此外，在图2(a)中，说明过凸台105前端部的凸台直径比下端部的凸台直径小。但是，前端部的凸台直径也可以大于下段部的凸台直径。采用前端部凸台直径大的凸台、能够提高导电胶111和凸台105的拉桩效果。因此，即使在半导体元件101和电路基片113间施加垂直方向的张力、也能够维持凸台105和导电胶111间的接合。参照图4(a)～(e)说明形成这样的凸台的顺序。
图4(a)～(e)示出具有比下段部大的凸台直径的凸台105的形成顺序。这里说明与2段突起不同类型的凸台。图4(a)示出半导体元件101。首先，在半导体元件101上，形成为进行半导体元件101向外部电气连接的电极103。
图4(b)示出涂敷了光刻胶104的半导体元件101。光刻胶104涂敷在形成了电极103的半导体元件101的表面上。光刻胶104是正性胶、负性胶都可以。
图4(c)示出具有锥形曝光图形的光刻胶104。这样的图形用光掩膜板，将图形曝光在光刻胶104上、然后显影、得到能使电极103露出的图形。为得到锥形形状只要设定适当的曝光条件即可。例如，采用负性光刻胶104的情况下，设定曝光显影条件使之过曝光。这样，在光刻胶104上就能容易的形成锥形形状的图形。
其次，图4(d)示出由电镀形成的金属105。金属105是凸台的母材、也就是凸台105自身。金属105能够由电镀露出的电极103使之析出得到。析出要做到使金属析出材料104不从光刻胶104的表面突出、能使凸台105平坦化。从与导电胶111(图1)更稳定接合的观点看电镀的金属析出材料最好用金、银、铜、以及这些的合金。
最后、图4(e)示出具有前端部凸台直径大的凸台105的半导体元件101。在图4(d)的半导体元件101中，凸台105由除去光刻胶104得到。
此外，在图4(d)中，析出的金属材料即使突出在光刻胶104的表面上也可以。由于金属的析出使金属材料突出出来，凸台105成为蘑菇形状。图5是表示形成了蘑菇形状凸台105的半导体元件101的图。由于凸台105是蘑菇形状更能提高导电胶111和凸台105的拉桩效果，确保更良好的连接稳定性。
还有，中间连接体107也可以用在薄膜基材的两面上设置粘接剂层的3层结构。当将半导体元件101叠层到中间连接体107上的时候，成为中间连接体107芯子的薄膜基材能够维持它的形状。因此，贯通孔109的壁面抑制导电胶111的扩展，在导电胶111上施加压缩力，能够更强固凸台105、导电胶111和电极115间的接合。设在薄膜基材两面的粘接剂将中间连接体107和半导体元件101及电路基片113粘接。进一步，由将半导体元件101叠层到中间连接体107上时的加热加压、因为粘接剂层在厚度方向收缩、导电胶111能够更致密化。
在中间连接体107采用3层构造的薄膜基材的情况下，还存在别的优点。就是说，能够减薄中间连接体107的厚度。在以更窄的间距配置电气连接部120的情况下，贯通孔109有必要用更小的直径。这时，当仅仅使贯通孔109的直径尽量小时，贯通孔109的直径与深度的高宽比变大。另一方面，当将导电胶111填充到贯通孔109时，高宽比低好。这是因为能够稳定的填充导电胶111。由此，用薄膜基材形成中间连接体107的话，它的厚度能够减薄、能够抑制高宽比的增加。进一步，能够以窄的间距配置电气连接部120。具体的说，用薄膜基材形成中间连接体107，将贯通孔109小直径化时，薄膜基材的厚度成为50μm的极薄状态。
当厚度薄到这样的情况下，单独处理中间连接体107变的困难。例如，中间连接体107有一定程度的厚度的话，在图2(b)中，也可以预先将中间连接体107载置在电路基片113上。就是说，能够在中间连接体107上形成贯通孔，充填导电胶111后，将半导体元件101及电路基片113叠层粘接。但是，在中间连接体107非常薄的情况下，不能采用该工序。图6(a)示出在将半导体元件101及电路基片113粘接前、将导电胶111填充在贯通孔内的中间连接体107。由于中间连接体107薄、从设在中间连接体107上的贯通孔的两端导电胶111突出出来。当用这样的中间连接体107粘接半导体元件101和电路基片113时，在加热·加压工序中、突出的导电胶111就向面方向扩展。图6(b)示出半导体元件101和电路基片113粘接后的中间连接体107。在这种情况下，当贯通孔(连接部)间的间距狭小时，相邻的连接部就发生电气短路。
由此，如上所述，最好是预先将中间连接体107形成在电路基片113上的工序。采用该工序，必须抑制导电胶111突出的贯通孔的开口面是一方向的、在导电胶填充时的梳理工序中容易控制。图7(a)示出与电路基片113粘接后、与半导体元件101粘接前、导电胶111填充在贯通孔109内的中间连接体107。在填充导电胶111的工序中，由控制导电胶111的量，就能理解导电胶111不从中间连接体107的表面突出出来。由此，在加热·加压工序时，能够抑制在贯通孔的两端面上导电胶111的面方向扩展。图7(b)示出将电路基片113和半导体元件101粘接后的中间连接体107。由此，即使在连接部进一步变成狭窄间距的情况下，也能防止电气的短路。还有，由于贯通孔109的一方一侧(电路基片113侧)是关闭的、从那里胶不会脱落。由此，导电胶111填充时的梳理等的控制也是一次即可，制造工序能够简便化。
此外，在本实施方式中，已说明用全层IVH构造的树脂多层电路基片作为电路基片113。但是，电路基片113的结构不仅限于此。用玻璃环氧树脂基片、合成基片作为电路基片也能得到同样的效果。
其次，参照图8(a)～(f)、说明实施方式1的半导体装置100(图1)的第2种制造方法。此外，在与参照图2(a)～(f)已说明的重复的情况下，省略详细的说明。
图8(a)是示出半导体元件101的图，与图2(a)相同。在半导体元件101上形成电极103、进一步在电极103上形成2段突起形状的凸台105。
图8(b)示出将导电胶111复印在凸台105的前端上的导电胶111。由此可以明了，导电胶111不是象图2(d)那样，直接填充到中间连接体107的贯通孔109内。
接着，图8(c)示出在表面上粘贴了中间连接体107的电路基片113。当然，当粘贴中间连接体107时，与图2(b)一样，不使中间连接体107完全硬化。
图8(d)示出形成了多个贯通孔109的中间连接体107。这与图2(c)相同。此外，在图8(d)中，说明了在中间连接体107的表面上不形成涂敷薄膜106(图2的(b)、(c))的情况的例子。但是，在中间连接体107的表面上形成涂敷薄膜106，在贯通孔109的激光加工后剥离，能够防止激光加工时的加工碎片附着在中间连接体107的表面。
图8(e)示出与半导体元件101对准后的电路基片113。为了在中间连接体107上叠层配置半导体元件101，将设有导电胶111的凸台105与贯通孔109对准。
最后，图8(f)示出叠层了半导体元件101的电路基片113。将凸台105和导电胶111收容在贯通孔109内，通过加热·加压使导电胶111硬化。也可以利用该加热·加压，由凸台105压缩导电胶111，使导电胶111内的导电性粒子致密化。由此，在凸台105、导电胶111和电路基片113上的电极115之间电气连接更加稳定、更好。由以上的第2制造方法完成半导体装置100。
此外，在第2制造方法中也与第1制造方法同样，当将导电胶111密闭在贯通孔109内时，也可以形成使包含在导电胶111内的导电性粒子不流出，仅仅树脂成分流出的间隙。间隙可以形成在中间连接体107和半导体元件101的界面，或者形成在中间连接体107和电路基片113的界面上。由此，当加热·加压时，与使导电胶更致密化的同时，能够抑制与邻接的连接部的电气短路。
如以上说明的，实施方式1的半导体装置100(图1)在半导体元件101和电路基片113之间，设置了在与半导体元件101的电极105及电路基片113的电极115对应的位置上具有贯通孔109的中间连接体107。电极103和电极115的电气连接，通过将形成在电极103上的凸台105埋没在填充到贯通孔109内的导电胶111上进行。由于导电胶111密闭在贯通孔109的内部，能够防止导电胶111扩展到邻接的电气连接部120上，防止相邻的电气连接部120的短路。由此，能够以更窄的间距设置电气连接部120。
还有，贯通孔109是在将电路基片113上的电极115的位置的实测值和在半导体元件101上的凸台105的位置的实测值反映到加工用的设计加工数据上，校正加工数据后形成。因此，能够更高精度的形成贯通孔109，能够提高封装成品率。进一步，也能以更窄的间距配置电气连接部120。
进一步，由于凸台105被埋设(埋没)在贯通孔109内的导电胶111内，即使在半导体元件101和电路基片113之间施加水平方向(面方向)的剪断力的情况下，凸台105也不会从导电胶111离开，半导体装置100(图1)能够保持电气连接的稳定性。还有，采用实施方式1的第1及第2制造方法，能够成批的实施贯通孔109的加工，导电胶111的充填及加热·加压等加工。由此，能够在大张状的电路基片上成批封装多个半导体元件，生产率好。
(实施方式2)
图9(a)示出实施方式2的半导体装置900结构的剖面图。图9(b)是半导体装置900的部分放大图。在实施方式1中、在半导体元件101(图1(b)的电极103上设置凸台105。本实施方式的半导体装置900中，在电路基片113的电极115上设置凸台105。其他的结构，例如，半导体元件101上的电极103和电路基片113上的电极115通过凸台105和导电胶111电气连接以及贯通孔109的壁面抑制导电胶111的流出、防止相邻的电气连接部120间的短路不良等都与实施方式1相同。
参照图10(a)～(f)说明实施方式2的半导体装置900(图9(a))的制造工序。首先，图10(a)示出电路基片113。在电路基片113上形成与半导体元件101进行电气连接的电极115。进一步，在电极115上形成凸台105。在实施方式2中，凸台115用的是2段突起形状的凸台。与实施方式1一样，凸台105的形状并不限定于此。
其次，图10(b)示出粘接了中间连接体107的半导体元件101。在中间连接体107的表面上形成了涂敷薄膜106。在中间连接体107的粘接工序中，包含在中间连接体107内的热硬化树脂最好不完全硬化。
进一步，图10(c)示出形成了贯通孔109的中间连接体107。更正确的说，贯通孔109贯通涂敷薄膜106及中间连接体107。贯通孔109最好用激光加工形成。进行激光加工直到半导体元件101上的电极103露出为止。在用激光加工形成贯通孔109的时候，将设置在电路基片113上的凸台105的实测值和设置在半导体元件101上的电极103的实测值反映在设计时的加工数据上、校正加工数据。而且，最好在其之后加工贯通孔109。
图10(d)示出填充了导电胶111的贯通孔109。填充规定数量导电胶111的手法与实施方式1说明的一样。
接着，图10(e)示出与半导体元件101对准后的电路基片113。为了在中间连接体107上叠层配置半导体元件101，将设置了导电胶111的凸台105和贯通孔109对准。在该工序中，涂敷薄膜106从中间连接体107剥离。
图10(f)示出叠层了半导体元件101的电路基片113。由加热·加压将凸台105被埋设(埋没)在贯通孔109内的导电胶111内的同时、将中间连接体107粘接到电路基片113上。由此，能确保凸台105、导电胶111和半导体元件101的电极103间的电气连接。进一步，也可以通过加热·加压，用凸台105压缩导电胶111。由此，使导电胶111内的导电性粒子致密化，在凸台105、导电胶111和半导体元件101的电极103间能实现更稳定的电气连接。由以上制造方法完成半导体装置900。
本实施方式的半导体装置900(图9(a))、在凸台105形成在电路基片113的电极115上这一点上与实施方式1的半导体装置100(图1(a))不同。一般说，形成在电路基片113上的电极115多用金属层或者铜电镀形成、它的厚度是18μm～35μm。这与在半导体元件101一侧形成的电极103相比要厚。因此，在图10(f)所示的由加热·加压的叠层粘接工序中，当使电极115埋没在贯通孔109上那样将中间连接体107叠层配置在电路基片113上时，能够更进一步压缩、致密化导电胶111。
此外，在本实施方式中，仅仅在电路基片113一侧形成凸台105。如果在半导体元件101一侧也形成凸台105的话，能够得到可靠性更高的电气连接。
图11示出实施方式2变形例的半导体装置910全部结构的剖面图。半导体装置910形成更厚的电路基片113上的电极115，用来代替凸台105(图9(b))。将该电极115埋设(埋没)在贯通孔109内的导电胶111上，也能得到与迄今为止的半导体装置同样优点。采用这样的结构，能够省略凸台105形成工序、生产率好。
(实施方式3)
图12示出实施方式3的半导体装置1200全部结构的剖面图。半导体装置1200是将半导体装置100(图1(a))中的半导体元件101更换成半导体元件的封装结构体805构成的。
半导体装置1200由封装结构体805、中间连接体107、电路基片113和电气连接部130构成。由于中间连接体107和电路基片113与实施方式1、2相同，省略详细说明。
封装结构体805具有：电路基片802、设在电路基片上的半导体元件801、将电路基片802和半导体元件801电气连接的金属导线803和设在电路基片802表面上的能覆盖半导体元件801和金属导线803的模制树脂806。
这里，封装半导体元件801的封装结构体805用引线焊接法确保半导体元件801和电路基片802的电气连接。但是，并不仅限于这种结构，封装结构体805也可以用倒装法将半导体元件801和电路基片802电气连接。还有，封装结构体805也可以是用芯片尺寸封装(CSP：Chip SizePackage)、球栅阵列(BGA：Ball Grid Array)等被称为所谓半导体封装的结构。
电气连接部130是封装结构体805的外部电极。电气连接部130具有：与半导体元件801的电极的一部分电气连接的电极804、设在电极804上的凸台105、设在电路基片113上与各个电极804对应的电极115、连接凸台105和电极115的导电胶111。电极804和电极115通过由凸台105和导电胶111组成的中间电气连接部连接、将封装结构体805和电路基片113电气连接。
一般来说，封装结构体805是在电极804上形成焊料球，由焊料连接与电路基片113电气连接。但是，随着电极804窄间距化、相邻的焊料球之间有时发生短路不良。因此，实施方式3的半导体装置1200中，将封装结构体805封装到电路基片113上时，能够使相邻的电气连接部130之间不发生短路那样的狭窄的间距配置。
半导体装置1200在封装结构体805的电极804上形成凸台105、将凸台105埋没向填充在设在中间连接体107上的贯通孔109内的导电胶111上。由此，封装结构体805和电路基片113电气连接。进一步，将凸台105埋没向导电胶111时，凸台105压缩导电胶111，能够实现电路基片113和封装结构体805间的更稳定的电气连接。这样，由于在电路基片113和封装结构体805的电气连接中使用了导电胶111，实施方式1中说明的一样，能够缓和加在电路基片113和封装结构体805双方连接部分的应力，能实现对热冲击等引起的尺寸变化下的稳定的电气连接。还有，由于导电胶111被关闭在贯通孔109内，导电胶111不会溢出到相邻的电气连接部130上、不会引起相邻的电气连接部130的短路。由此，能够以更窄的间距配置电气连接部130。
此外，在本实施方式中，示出了在电极804一侧形成凸台105的结构。但是，也可以将凸台105形成在电路基片113的电极115一侧。进一步，也可以在电极804侧和电极115侧两方面上都形成凸台105。
就凸台105的形状来说，并不仅限于2段突起形状，也可以用实施方式1所示的其他的材料和形状。
通过狭窄间距的电气连接部130配置在电路基片113上的电子器件不仅限于半导体元件及半导体封装结构体。用在滤波器、微型组件等电子器件也能得到同样的效果。
发明的效果
采用本发明的半导体装置，在半导体部和电路基片间设置了中间连接体，在中间连接体上形成了贯通孔。由于在贯通孔内，封入了设在半导体部或者电路基片的至少一方上的凸台和导电胶，确保半导体部和电路基片的电气连接，导电胶不从贯通孔向外部扩展。由此，能够防止相邻的电气连接部的短路。由此，能够用导电胶将具有以狭窄的间距配置的电极的半导体元件及电路基片高可靠性的电气连接。
在半导体部和电路基片的电气连接上使用了导电胶。由此，能够缓和因二者的热膨胀系数差引起的加在二者上的应力。由此，在因热冲击引起尺寸变化的情况下，也能够实现稳定的电气连接。

Claims (17)

1.一种半导体装置的制造方法，是制造将半导体部和电路基片电气连接起来的半导体装置的制造方法，其特征在于：
它包含以下各工序：
在所述半导体部上形成多个半导体电极的工序，
在所述电路基片上形成多个基片电极的工序，
将所述半导体部及所述电路基片的一方粘接到由绝缘性材料组成的中间连接体上的第1粘接工序，
在所述中间连接体上形成多个与所述多个半导体电极的位置及所述多个基片电极的位置相对应的多个贯通孔的工序，
通过各贯通孔、将各半导体电极和各基片电极电气连接的工序，
将所述半导体部及所述电路基片的另一方粘接到所述中间连接体上的第2粘接工序。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于：
进行电气连接的所述工序包含以下各工序：
在所述多个半导体电极及所述多个基片电极的至少一方上、形成多个凸台的工序，
在所述各贯通孔内填充导电胶的工序，
将各凸台埋没在所述各贯通孔内的所述导电胶内、通过所述多个凸台及所述导电胶、将各半导体电极和各基片电极电气连接的工序。
3.根据权利要求1所述的半导体装置的制造方法，其特征在于：
形成多个贯通孔的所述工序包含以下各工序：
测定所述多个半导体电极的位置及所述多个基片电极的位置的至少一方、取得位置数据的工序，
基于已测定的所述位置数据、特定所述中间连接体上的多个位置的工序，
在特定的所述中间连接体上的各位置上形成所述各贯通孔的工序。
4.根据权利要求2所述的半导体装置的制造方法，其特征在于：
所述多个半导体电极及所述多个基片电极的每一个都是在表面上形成了含树脂被膜的金属层，
形成多个贯通孔的所述工序除去所述被膜、使所述金属层露出。
5.根据权利要求4所述的半导体装置的制造方法，其特征在于：
形成多个贯通孔的所述工序形成使壁面倾斜的所述各贯通孔。
6.根据权利要求2所述的半导体装置的制造方法，其特征在于：
填充导电胶的所述工序包含：
从所述各贯通孔的底部到开口部注入所述导电胶的工序和从所述开口部梳理规定量的所述导电胶的工序。
7.根据权利要求6所述的半导体装置制造方法，其特征在于：
注入导电胶的所述工序在导电胶上施加压力、使之吐出，从所述各贯通孔的底部到开口部注入。
8.根据权利要求1所述的半导体装置的制造方法，其特征在于：
所述第1粘接工序及所述第2粘接工序由加压使所述中间连接体与所述半导体部及所述电路基片粘附、封锁所述各贯通孔。
9.根据权利要求8所述的半导体装置的制造方法，其特征在于：
所述导电胶包含导电性粒子和非导电性的树脂，
封锁所述各贯通孔的工序包含以下各工序：
在所述中间连接体和所述半导体部及所述电路基片的至少一方的界面上设置仅仅使所述非导电性树脂流出的间隙的工序，
由加压使所述导电胶致密化、使所述非导电性树脂从各贯通孔流出的工序，
封锁残留了所述导电性粒子的所述各贯通孔的工序。
10.根据权利要求1所述的半导体装置的制造方法，其特征在于：
所述中间连接体进一步包含因加压收缩的材料，所述第1粘接工序及所述第2粘接工序因加压使所述中间连接体收缩、使所述导电胶致密化。
11.根据权利要求1所述的半导体装置的制造方法，其特征在于：
所述中间连接体进一步包含热硬化性树脂，所述第1粘接工序由加热使包含热硬化性树脂的所述中间连接体的一部分硬化，将所述半导体部及所述电路基片的一方粘接到所述中间连接体上。
12.根据权利要求11所述的半导体装置的制造方法，其特征在于：
所述第2粘接工序由加热使所述中间连接体硬化，将所述半导体部及所述电路基片和所述中间连接体粘接。
13.根据权利要求6所述的半导体装置的制造方法，其特征在于：
注入导电胶的所述工序是对导电胶施加压力、使之吐出分量大于从各贯通孔的容积减去被埋没的各凸台的容积、并且小于各贯通孔容量的所述导电胶。
14.一种半导体装置，是具有以下部分的半导体装置，其特征在于：
具有多个半导体电极的半导体部，
具有多个基片电极的电路基片，
是粘接在所述半导体部及所述电路基片的、被夹持的、由绝缘性材料组成的中间连接体，具有被导电胶填充的多个贯通孔，通过各贯通孔内的所述导电胶、将各半导体电极和各基片电极电气连接的中间连接体；
所述各半导体电极及所述各基片电极是在表面上形成包含树脂被膜的金属层，在所述各贯通孔内所述被膜被除去、与所述导电胶相连接。
15.根据权利要求14所述的半导体装置，其特征在于：
所述各贯通孔的壁面是倾斜的。
16.根据权利要求14所述的半导体装置，其特征在于：
在所述多个半导体电极及所述多个基片电极的至少一方上、形成多个凸台。
17.根据权利要求16所述的半导体装置，其特征在于：
所述多个凸台的每一个是2段突起形状。
CN02118367A 2001-04-25 2002-04-25 半导体装置的制造方法及半导体装置 Pending CN1383197A (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105188333A (zh) * 2014-06-19 2015-12-23 亚企睦自动设备有限公司 装配装置以及装配方法
CN106024743A (zh) * 2009-12-21 2016-10-12 英特尔公司 空腔互连技术中的焊料
CN107634043A (zh) * 2016-07-18 2018-01-26 南亚科技股份有限公司 半导体装置、半导体封装及其制造方法
CN112965308A (zh) * 2021-02-04 2021-06-15 豪威半导体（上海）有限责任公司 Lcos结构及其形成方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004265940A (ja) * 2003-02-19 2004-09-24 Sony Corp 半導体装置
US7902678B2 (en) * 2004-03-29 2011-03-08 Nec Corporation Semiconductor device and manufacturing method thereof
US7332821B2 (en) * 2004-08-20 2008-02-19 International Business Machines Corporation Compressible films surrounding solder connectors
JP4035733B2 (ja) * 2005-01-19 2008-01-23 セイコーエプソン株式会社 半導体装置の製造方法及び電気的接続部の処理方法
KR101247138B1 (ko) * 2005-09-14 2013-03-29 하테체 베타일리궁스 게엠베하 플립-칩 모듈 및 플립-칩 모듈의 제조 방법
JP5183893B2 (ja) * 2006-08-01 2013-04-17 新光電気工業株式会社 配線基板及びその製造方法、及び半導体装置
JP5014890B2 (ja) * 2007-06-20 2012-08-29 パナソニック株式会社 電極芯線の接合方法
FR2928032B1 (fr) * 2008-02-22 2011-06-17 Commissariat Energie Atomique Composant de connexion muni d'inserts avec cales compensatrices.
WO2010140469A1 (ja) * 2009-06-01 2010-12-09 住友電気工業株式会社 接続方法，接続構造および電子機器
US8507325B2 (en) * 2010-01-28 2013-08-13 International Business Machines Corporation Co-axial restraint for connectors within flip-chip packages
US8716867B2 (en) 2010-05-12 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Forming interconnect structures using pre-ink-printed sheets
EP2463809A1 (fr) * 2010-12-07 2012-06-13 NagraID S.A. Carte électronique à contact électrique comprenant une unité électronique et/ou une antenne
US20120286416A1 (en) * 2011-05-11 2012-11-15 Tessera Research Llc Semiconductor chip package assembly and method for making same
KR20130012470A (ko) * 2011-07-25 2013-02-04 삼성전기주식회사 범프 형성 방법, 및 상기 범프를 포함하는 기판
US8916979B2 (en) * 2012-12-28 2014-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Through-vias and methods of forming the same
JP5714631B2 (ja) * 2013-03-26 2015-05-07 富士フイルム株式会社 異方導電性シート及び導通接続方法
US9293438B2 (en) 2013-07-03 2016-03-22 Harris Corporation Method for making electronic device with cover layer with openings and related devices
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
JP7313315B2 (ja) * 2020-05-19 2023-07-24 三菱電機株式会社 半導体装置の製造方法及び電力制御回路の製造方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4661192A (en) * 1985-08-22 1987-04-28 Motorola, Inc. Low cost integrated circuit bonding process
JPH07112041B2 (ja) * 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
US5768109A (en) * 1991-06-26 1998-06-16 Hughes Electronics Multi-layer circuit board and semiconductor flip chip connection
JPH05251505A (ja) 1991-12-27 1993-09-28 Minnesota Mining & Mfg Co <3M> Ｉｃチップのエリアテープへの接続方法
JPH05198697A (ja) 1992-01-20 1993-08-06 Fujitsu Ltd シリコン基板金属ビア形成方法およびマルチチップモジュール製造方法
WO1993019487A1 (en) * 1992-03-24 1993-09-30 Unisys Corporation Integrated circuit module having microscopic self-alignment features
JP2826049B2 (ja) 1992-11-18 1998-11-18 松下電子工業株式会社 半導体装置およびその製造方法
JPH0786331A (ja) 1993-09-10 1995-03-31 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6074893A (en) * 1993-09-27 2000-06-13 Sumitomo Metal Industries, Ltd. Process for forming fine thick-film conductor patterns
JPH088511A (ja) 1994-06-22 1996-01-12 Oki Electric Ind Co Ltd Ｂｇａパッケージとその製造方法
US5808874A (en) * 1996-05-02 1998-09-15 Tessera, Inc. Microelectronic connections with liquid conductive elements
JP3610999B2 (ja) * 1996-06-07 2005-01-19 松下電器産業株式会社 半導体素子の実装方法
WO1998002919A1 (fr) 1996-07-12 1998-01-22 Fujitsu Limited Procede et moule de fabrication d'un dispositif a semiconducteur, dispositif a semiconducteur, et procede de montage du dispositif
JP2783259B2 (ja) * 1996-07-18 1998-08-06 日本電気株式会社 半導体パッケージとその製造方法
JP2952813B2 (ja) 1996-07-22 1999-09-27 本田技研工業株式会社 電子部品の実装方法
DE69738289D1 (de) 1996-07-22 2007-12-27 Honda Motor Co Ltd Verbindung zwischen leiterplatte und steckerelement
JP3961092B2 (ja) * 1997-06-03 2007-08-15 株式会社東芝 複合配線基板、フレキシブル基板、半導体装置、および複合配線基板の製造方法
JPH11204573A (ja) 1998-01-16 1999-07-30 Hitachi Ltd 半導体装置の製造方法および半導体装置
JP3563637B2 (ja) 1998-06-04 2004-09-08 松下電器産業株式会社 半導体装置とその製造方法
US6410364B1 (en) * 1998-09-30 2002-06-25 Seiko Epson Corporation Semiconductor device, method of connecting a semiconductor chip, circuit board, and electronic equipment
US6190940B1 (en) * 1999-01-21 2001-02-20 Lucent Technologies Inc. Flip chip assembly of semiconductor IC chips
JP3405259B2 (ja) * 1999-03-17 2003-05-12 カシオ計算機株式会社 突起電極の形成方法及び突起電極を備えたフィルム基板の製造方法並びに突起電極を備えた半導体装置の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106024743A (zh) * 2009-12-21 2016-10-12 英特尔公司 空腔互连技术中的焊料
CN105188333A (zh) * 2014-06-19 2015-12-23 亚企睦自动设备有限公司 装配装置以及装配方法
CN107634043A (zh) * 2016-07-18 2018-01-26 南亚科技股份有限公司 半导体装置、半导体封装及其制造方法
CN112965308A (zh) * 2021-02-04 2021-06-15 豪威半导体（上海）有限责任公司 Lcos结构及其形成方法
US11579501B2 (en) 2021-02-04 2023-02-14 Omnivision Semiconductor (Shanghai) Co., Ltd. LCOS structure and method of forming same

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