JP3610999B2 - 半導体素子の実装方法 - Google Patents

半導体素子の実装方法 Download PDF

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Publication number
JP3610999B2
JP3610999B2 JP14524196A JP14524196A JP3610999B2 JP 3610999 B2 JP3610999 B2 JP 3610999B2 JP 14524196 A JP14524196 A JP 14524196A JP 14524196 A JP14524196 A JP 14524196A JP 3610999 B2 JP3610999 B2 JP 3610999B2
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Japan
Prior art keywords
semiconductor element
circuit board
conductive paste
bump
external electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP14524196A
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English (en)
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JPH09326419A (ja
Inventor
法人 塚原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority to JP14524196A priority Critical patent/JP3610999B2/ja
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to PCT/JP1997/001971 priority patent/WO1997047031A1/ja
Priority to EP97925302A priority patent/EP0844657A4/en
Priority to KR10-1998-0700903A priority patent/KR100457609B1/ko
Priority to US09/011,603 priority patent/US6051093A/en
Priority to CN97190666A priority patent/CN1110078C/zh
Publication of JPH09326419A publication Critical patent/JPH09326419A/ja
Priority to US09/528,116 priority patent/US6531022B1/en
Application granted granted Critical
Publication of JP3610999B2 publication Critical patent/JP3610999B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子の回路基板に高信頼性、高密度でフリップチップ型半導体素子を実装する半導体素子の実装方法に関するものである。
【０００２】
【従来の技術】
従来の半導体素子の実装方法を図面に基づいて説明する。
（従来例１）
図16に従来例１における半導体素子を回路基板に実装した断面図を示す。
【０００３】
図16において、１は半導体素子であり、半導体素子１上に電極２が形成され、電極２上に、ワイヤボンディング法によって金、銅、アルミニウム、半田などからなる突起バンプ（金属ボールバンプ）15が形成されている。
【０００４】
また４は絶縁性基体からなる回路基板であり、この回路基板４上に配線となる銅箔５が形成され、また回路基板４上に銅メッキされた外部電極端子６が形成され、回路基板内の導通をとるため、回路基板４内に形成された孔部８に、導電性ペースト７が充填されている。
【０００５】
また22はフェノールやエポキシ系樹脂に銀、金、ニッケル、カーボンなどの導電粉末を均一分散した導電性ペースト（導電性接着剤）であり、回路基板４の外部電極端子６と半導体素子１の電極２を突起バンプ15を介して電気的に接続しており、また回路基板４上と半導体素子１間にはエポキシ系樹脂20が充填されている。
【０００６】
以上のように構成された半導体素子の実装方法を説明する。半導体素子１の各電極２上に形成された突起バンプ15に転写法により導電性ペースト22を転写した後、実装すべき回路基板４の外部電極端子６に合致されるように積載し、その後加熱し、導電性ペースト22を硬化し、半導体素子１の電極２と回路基板４の外部電極端子６とを電気的に接続している。そして、接続後に半導体素子１と回路基板４の間隔にエポキシ系樹脂20を充填し、その硬化収縮力を利用して、導電性ペースト22の導電粉末の連続的な接触が得られるようにし、電気的、機械的信頼性を確保している。
（従来例２）
図17に従来例２における半導体素子を回路基板に実装した断面図を示す。上記図16の構成と同一の構成には同一の符号を付して説明を省略する。
【０００７】
図17において、23は電極２上に電気メッキ法によって形成された金属バンプであり、金属バンプ23上に、たとえば銅メッキが施され、その上に上に金メッキ24が施されている。25は外部電極端子、16は半導体素子１のアクティブ面を保護するパシベーション膜である。
【０００８】
以上のように構成された半導体素子の実装方法を説明する。半導体素子１の各電極２上に形成された金属バンプ23に転写法により導電性ペースト22を転写した後、実装すべき回路基板４の外部電極端子25に合致されるように積載し、その後加熱し、導電性ペースト22を硬化し、半導体素子１の電極２と回路基板４の外部電極端子25とを電気的に接続している。そして、接続後に半導体素子１と回路基板４の間隔にエポキシ系樹脂20を充填し、その硬化収縮力を利用して、導電性ペースト22の導電粉末の連続的な接触が得られるようにし、電気的、機械的信頼性を確保している。
（従来例３）
図18に従来例３における半導体素子を回路基板に実装した断面図を示す。上記図16，図17の構成と同一の構成には同一の符号を付して説明を省略する。
【０００９】
図18において、３は電極２の上にメッキ法により形成された突起バンプ（突起電極）、26は絶縁性接着剤フィルムであり、絶縁性接着剤フィルム26内にはニッケル、半田、カーボンなどからなる導電粒子27が均一に分散されている。
【００１０】
以上のように構成された半導体素子の実装方法を説明する。
絶縁接着剤フィルム26を半導体素子１および回路基板４の外部電極端子25に挟んで位置合わせして、加熱、加圧を同時に行なう。これにより、接着剤フィルム26は溶融し電極25間のスペースに流動していき、導電粒子27は突起バンプ３と外部電極端子25により固定保持され導通する。一方、スペースでは導電粒子27が接着剤中に分散された状態を保つために絶縁性が確保される。接着剤フィルム26は冷却すると硬化し、半導体素子１と回路基板４を固定し、接続信頼性を確保する。
【００１１】
【発明が解決しようとする課題】
しかし、上記従来例１（または従来例２）の半導体素子の実装方法では、図19に示すように、転写法によって導電性ペースト膜28を突起バンプ15に転写し、バンプ15を回路基板４の外部電極６に接合する際に、転写導電性ペースト22の量のコントロールが困難であり、少しでも多いと電極２間が導電性ペースト22により接続されショート回路30が形成されてしまうという問題があった。また、回路基板４が少しでも反っていると、半導体素子１の電極２と回路基板４の外部電極端子６が導電性ペースト22を介して接触せず、電気的にオープン状態になるという問題があった。
【００１２】
また、図20に示すように、エポキシ系樹脂20を半導体素子１と回路基板４の隙間に充填する際に、シリンジ31に封入されたエポキシ系樹脂20を半導体素子１の周辺部より注入していくため、注入時間が約１０分以上かかり、半導体素子１の生産ラインのタクトタイムの短縮の障害になるという問題があった。
【００１３】
また上記従来例３の半導体素子の実装方法では、導電粒子27を半導体素子１の電極２と回路基板４の電極25間に固定保持することにより導通されるため、図21に示すように、回路基板４に少しでも反り・うねりＡがあれば、導電粒子27が接着剤26中に分散されたままの状態で半導体素子１の突起バンプ３と回路基板４の電極25に接触せず、電気的にオープン状態になるという問題点があった。なお、従来例３の実装方法は、反り・うねりの少ないガラス基板を対象として用いられており、樹脂基板には用いられていないのが現状である。
【００１４】
そこで本発明は、電極間でのショートやオープンといった不良は発生せず、電気的信頼性の高い実装が行え、封止工程の時間の大幅な削減ができ、半導体素子生産ラインのタクトタイムの短縮を可能とする半導体素子の実装方法を提供することを目的とする。
【００１５】
【課題を解決するための手段】
上記目的を達成するため本発明の半導体素子の実装方法は、回路基板の回路と半導体素子の電極を接続する前記回路基板の箇所に、貫通孔部を形成する工程と、前記貫通孔部に導電性ペーストを充填し前記回路基板の裏面側に外部電極端子を形成する工程と、前記半導体素子の電極に円錐形で尖った形状の突起バンプを形成する工程と、前記外部電極端子が形成された回路基板上、または前記半導体素子の突起バンプ上に、熱硬化系樹脂または熱可塑系樹脂または熱硬化と熱可塑の混合系樹脂を有する接着剤シートを配置する工程と、前記外部電極端子と前記半導体素子の前記電極に形成された前記突起バンプを位置決めする工程と、前記半導体素子を押圧し、前記接着剤シートを前記円錐形で尖った形状の突起バンプにより突き破り、前記貫通孔部内の前記導電性ペーストと前記突起バンプとを接触させ、前記半導体素子の前記電極と前記回路基板の前記外部電極端子とを電気的に接続する工程と、加熱ツールにより前記半導体素子を加熱し、前記接着剤シートを溶融し、硬化する工程とを有するものである。
【００１６】
上記半導体素子の実装方法により、回路基板の孔部内の充填された導電性ペーストに半導体素子の電極に形成した突起バンプを接触させ、前記半導体素子の電極と回路基板の外部電極端子とを電気的に接続することによって、電極間でのショートやオープンといった不良は発生せず、電気的信頼性の高い実装が行える。
【００２１】
【発明の実施の形態】
本発明の請求項１に記載の発明は、回路基板の回路と半導体素子の電極を接続する前記回路基板の箇所に、貫通孔部を形成する工程と、前記貫通孔部に導電性ペーストを充填し外部電極端子を形成する工程と、前記半導体素子の電極に円錐形で尖った形状の突起バンプを形成する工程と、前記外部電極端子が形成された回路基板上、または前記半導体素子の突起バンプ上に、熱硬化系樹脂または熱可塑系樹脂または熱硬化と熱可塑の混合系樹脂を有する接着剤シートを配置する工程と、前記外部電極端子と前記半導体素子の前記電極に形成された前記突起バンプを位置決めする工程と、前記半導体素子を押圧し、前記接着剤シートを前記円錐形で尖った形状の突起バンプにより突き破り、前記貫通孔部内の前記導電性ペーストと前記突起バンプとを接触させ、前記半導体素子の前記電極と前記回路基板の前記外部電極端子とを電気的に接続する工程と、加熱ツールにより前記半導体素子を加熱し、前記接着剤シートを溶融し、硬化する工程とを有することを特徴とする半導体素子の実装方法であり、接着剤シートが溶融・硬化後、半導体素子のアクティブ面および電極の表面を保護するため、より接続の信頼性が増すとともに、接着剤シートの場合、加圧・硬化に要する時間が約３０秒と、エポキシ系樹脂の硬化時間、約４時間に対して大幅に短いため、半導体素子の生産ラインのタクトタイム短縮につながるという作用を有する。
【００２２】
以下、本発明の実施の形態を図面に基づいて説明する。なお、従来例の図16〜図18の構成と同一の構成には同一の符号を付して説明を省略する。
（実施の形態１）
図１は本発明の実施の形態１における半導体素子を実装した回路基板の断面図である。
【００２３】
図示するように、半導体素子１の電極２上に形成された突起バンプ３は、回路基板４の孔部８に充填された導電性ペースト７に埋もれる形で、接触しており、回路基板４の外部電極端子６と半導体素子１の電極２が電気的に接続されている。図２の工程図にしたがって本発明の半導体素子の実装方法を説明する。
【００２４】
まず、回路基板４の外部電極端子６と半導体素子１の電極２を接続する、回路基板４の箇所に、孔部８を形成し、図２(a) に示すように、導電性ペースト７を、スキージ９を移動さすことにより前記回路基板４の孔部８に印刷・充填し、回路基板４の外部電極端子33を形成する。
【００２５】
次に、図２(b) に示すように、半導体素子１を吸着ノズル10に吸着させ、突起バンプ３と、孔部８に充填された導電性ペースト７により形成された回路基板４の外部電極端子33との位置合わせを行う。
次に、図２(c) に示すように、半導体素子１を吸着ノズル10により押圧し、図２(d) に示すように、突起バンプ３を回路基板４の孔部８に充填された導電性ペースト７に埋め込む。
【００２６】
その結果、半導体素子１の突起バンプ３が回路基板４の孔部内で導電性ペースト７と接触し、電気的に接続される。また、回路基板４は図３に示すように、インナービアホールにより、基板内層間の導通がとられた多層基板であっても、図４に示すようにスルーホールによって、層間の導通がとられた多層基板であっても良い。
【００２７】
この実施の形態１によれば、半導体素子１の電極２上に形成された突起バンプ３が、回路基板４の孔部８内で導電性ペースト７に埋もれて接触し、電気的に接続されるため、ショートが発生せず、また回路基板４の反り、うねりに対する許容範囲も広がり、オープンが発生せず、高い信頼性をもって半導体素子１と回路基板４を接合することができる。
（実施の形態２）
図５は本発明の実施の形態２におけるワイヤボンディング法を用いた、半導体素子の電極上の突起バンプの形成方法を示す工程図であり、図５を参照しながらワイヤボンディング法を説明する。
【００２８】
まず、図５(a) に示すように、金、銅、アルミニウム、半田などで製作された金属ワイヤ11をセラミックやルビーで作られたキャピラリー13に通し、通した金属ワイヤ11の先端とトーチと呼ばれる電極14との間で放電し、金属ボール12を形成する。
【００２９】
次に、図５(b) に示すように、予熱されている半導体素子１の電極２の上に前記金属ボール12を押圧し、超音波振動を加え、温度、圧力、超音波振動の作用によって、金属ボール12を電極２に接合する。
【００３０】
次に、図５(c) に示すように、キャピラリー13を鉛直方向に上昇させ、金属ワイヤ11を引きちぎって図６に示す、金属ボールによるバンプ15を形成する。そして図５(d) に示すように、キャピラリー13を上昇させた後、金属ワイヤ１１を引きちぎらず、キャピラリー13を横にずらせて下降させ、金属ワイヤ11を金属ボール12上に接触させ、温度、圧力、あるいは、温度、圧力、超音波振動の作用によって金属ワイヤ11を金属ボール12に接合する。
【００３１】
次に、図５(e) に示すように、キャピラリー13を上昇させ、金属ワイヤ11を引きちぎって、図５(f) および図７に示す、金属ボールによる２段突起形状バンプ15を形成する。
【００３２】
上記方法により半導体素子１の電極２上に金属ボールによる突起バンプ15を形成した後、図８に示す方法により、半導体素子１と回路基板４との接合を行う。図８の実装方法は上記実施の形態１で説明した方法と同様であり、説明を省略する。
【００３３】
この実施の形態２によれば、実施の形態１での効果に加えて、突起バンプを電気メッキ法により形成した場合、最大でも２５μｍ程度の高さの低いバンプしか形成できないのに対して、ワイヤボンディング法を使用することにより５０μｍ以上の高さの高いバンプを形成でき、よって図８(e) に示すように、回路基板４の孔部８の導電性ペースト７に埋もれるバンプ15の量が多くなり、回路基板４の反り、うねりに対する許容範囲が広くなり、より信頼性の高い実装を行うことができる。
（実施の形態３）
本発明の実施の形態３における半導体素子の実装方法を図９を参照にしながら説明する。
【００３４】
図９は、半導体素子１を吸着ノズル10に吸着し、突起バンプ15と孔部８に充填された導電性ペースト７により形成された回路基板４の外部電極端子と位置合わせを行なった後、押圧し、突起バンプ15が導電性ペースト７に埋め込まれた状態を示している。その際、吸着ノズル10は、内蔵されているヒータ17により加熱されており、押圧と同時に導電性ペースト７の硬化を行っている。
【００３５】
この実施の形態３によれば、上記実施の形態１，２での効果に加えて、導電性ペースト７を硬化することにより、半導体素子１と回路基板４との固定がより強固となり、より信頼性の高い接合が行えるとともに、従来、導電性ペースト７の硬化は、モジュールをオーブン炉に入れバッチ処理していたのに対して、接合と同時に同一設備で行えるため、半導体素子１の生産ラインのタクトタイム短縮を行うことができる。
（実施の形態４）
本発明の実施の形態４における半導体素子の実装方法を図10を参照にしながら説明する。
【００３６】
図10は、半導体素子１を吸着ノズル10に吸着し、突起バンプ15と孔部８に充填された導電性ペースト７により形成された回路基板４の外部電極端子33と位置合わせを行なった後、押圧し、突起バンプ15が導電性ペースト７に埋め込まれた状態を示している。その際、回路基板４を保持しているステージ18は、内蔵されているヒータ17により加熱されており、半導体素子１の押圧時に熱を加えることにより、押圧と同時に導電性ペースト７の硬化を行っている。
【００３７】
この実施の形態４によれば、上記実施の形態１，２での効果に加えて、導電性ペースト７を硬化することにより、半導体素子１と回路基板４との固定がより強固となり、より信頼性の高い接合が行えるとともに、従来、導電性ペースト７の硬化は、モジュールをオーブン炉に入れバッチ処理していたのに対して、接合と同時に同一設備で行えるため、半導体素子１の生産ラインのタクトタイム短縮を行うことができる。
（実施の形態５）
本発明の実施の形態５における半導体素子の実装方法を図11を参照にしながら説明する。
【００３８】
図11に示すように実施の形態５では、半導体素子１を押圧し、回路基板４の孔部８の導電性ペースト７と半導体素子１の電極２上の突起バンプ15を接触させた後、モジュール（回路基板４および半導体素子１）をコンベア32にのせ、移動させながらモジュール全体をヒータ 19によって加熱し、導電性ペースト７の硬化を行う。
【００３９】
この実施の形態５によれば、上記実施の形態１，２での効果に加えて、導電性ペースト７の硬化を、モジュール全体をコンベア32にのせ、移動させながら加熱するリフロー方式で行うため、実装と同一生産ライン上での硬化が可能となり、半導体素子１の生産ラインのタクトには影響を与えず、半導体素子１と回路基板４との固定をより強固にでき、より信頼性の高い接合を行うことができる。
（実施の形態６）
本発明の実施の形態６における半導体素子の実装方法を図12を参照しながら説明する。
【００４０】
図12に示すように実施の形態６では、上記実施の形態１〜５の実装の工程において、回路基板４に半導体素子１を実装した後に、半導体素子１と回路基板４との間隔にシリンジ31を用いて、エポキシ系樹脂20を充填する。
【００４１】
この実施の形態６によれば、上記実施の形態１〜５での効果に加えて、図13に示すように、エポキシ系樹脂20の充填により、半導体素子１のアクティブ面および電極２の表面が保護されるため、たとえば、モジュールが高温高湿などの環境にさらされても、電極２および突起バンプ３の腐食を防ぐことができ、より信頼性の高い接続を行うことができる。
（実施の形態７）
本発明の実施の形態７における半導体素子の実装方法を図14を参照にしながら説明する。
【００４２】
まず、図14(a) に示すように、回路基板４の孔部８に導電性ペースト７を充填し、外部電極端子33を形成した後、回路基板４上に熱硬化系、または熱可塑系、または熱硬化と熱可塑の混合系樹脂からなる接着剤シート21を配置する。
【００４３】
なお、接着剤シート21には、ニッケル、半田、カーボン、金めっきプラスチック粒子などを均一に分散させておいても良い。次に、図14(b) に示すように、半導体素子１を吸着ノズル10に吸着し、突起バンプ15と孔部８に充填された導電性ペースト７により形成された回路基板４の外部電極端子33と位置合わせを行なう。
【００４４】
次に、図14(c) に示すように、半導体素子１を押圧し、突起バンプ15により接着剤シート21を突き破り、導電性ペースト７に突起バンプ１５を埋め込む。その際、吸着ノズル10は、内蔵されているヒータ17により加熱されており、押圧と同時に接着剤シート21の溶融・硬化が行われる。
【００４５】
この実施の形態７によれば、上記実施の形態１，２での効果に加えて、図14(d) に示すように、接着剤シート21が溶融・硬化し、半導体素子１のアクティブ面および電極の２表面を保護するため、より接続の信頼性が増すとともに、接着剤シート21の場合、加圧・硬化に要する時間が約３０秒と、エポキシ系樹脂の硬化時間約４時間に対して大幅に短いため、半導体素子１の生産ラインのタクトタイム短縮が可能となる。
（実施の形態８）
本発明の実施の形態８における半導体素子の実装方法を図15を参照にしながら説明する。
【００４６】
まず、図15(a) に示すように、半導体素子１の電極２上に突起バンプ15を形成した後、予め突起バンプ15上に熱硬化系、または熱可塑系、または熱硬化と熱可塑の混合系樹脂からなる接着剤シート21を配置する。なお、接着剤シート21には、ニッケル、半田、カーボン、金めっきプラスチック粒子などを均一に分散させておいても良い。
【００４７】
その後、図15(b) に示すように、半導体素子１を吸着ノズル10に吸着し、突起バンプ15と孔部８に充填された導電性ペースト７により形成された回路基板４の外部電極端子33と位置合わせを行なった後、押圧し、突起バンプ15により接着剤シート21を突き破り、導電性ペースト７に突起バンプ15を埋め込む。その際、吸着ノズル10は、内蔵されているヒータ17により加熱されており、押圧と同時に接着剤シート21の溶融・硬化が行われる。
【００４８】
この実施の形態８によれば、上記実施の形態１，２での効果に加えて、実施の形態７と同様、接着剤シート21が溶融・硬化し、半導体素子１のアクティブ面および電極２の表面を保護するため、より接続の信頼性が増すとともに、接着剤シート21の場合、加圧・硬化に関する時間が約３０秒と、エポキシ系樹脂の硬化時間、約４時間に対して大幅に短いため、半導体素子１の生産ラインのタクトタイム短縮が可能となる。
【００４９】
【発明の効果】
以上のように本発明によれば、半導体素子の電極上に形成された突起バンプを、回路基板の孔部内の導電性ペーストに接触させ、半導体素子の電極と回路基板の外部電極端子とを電気的に接続することにより、電極間でのショートを回避でき、また回路基板の反り、うねりに対する許容範囲が広いことから電極間でのオープンを回避でき、電気的信頼性の高い実装を行うことができる。
【００５０】
また、接着剤シートを予め、回路基板上、もしくは半導体素子の突起バンプ上に配置しておき、実装の際に突起バンプを接着剤シートを突き破って回路基板孔部内の導電性ペーストに接触させ、電気的に接続するとともに、接着剤シートを溶融・硬化することにより、半導体素子のアクティブ面および電極の表面を接着剤シートにより保護することができ、より接続の信頼性が増すことができ、さらに接着剤シートの場合加圧・硬化に要する時間が約３０秒と、エポキシ系樹脂の硬化時間、約４時間に対して大幅に短いため、封止工程の時間を大幅に削減でき、半導体素子生産ラインのタクトタイムの短縮を実現できる。
【図面の簡単な説明】
【図１】本発明の実施の形態１における実装後の半導体素子と回路基板の接合断面図である。
【図２】本発明の実施の形態１における実装の工程を順に示す図である。
【図３】本発明の実施の形態１における実装後の半導体素子と回路基板の接合断面図である。
【図４】本発明の実施の形態１における実装後の半導体素子と回路基板の接合断面図である。
【図５】本発明の実施の形態２におけるワイヤボンディング法の工程を順に示す図である。
【図６】本発明の実施の形態２におけるワイヤボンディング法により形成された突起バンプの側面図である。
【図７】本発明の実施の形態２におけるワイヤボンディング法により形成された２段突起形状突起バンプの側面図である。
【図８】本発明の実施の形態２における実装の工程を順に示す図である。
【図９】本発明の実施の形態３における実装の工程を示す図である。
【図10】本発明の実施の形態４における実装の工程を示す図である。
【図11】本発明の実施の形態５における実装の工程を示す図である。
【図12】本発明の実施の形態６における実装の工程を示す図である。
【図13】本発明の実施の形態６における実装後の半導体素子と回路基板の接合断面図である。
【図14】本発明の実施の形態７における実装の工程を順に示す図である。
【図15】本発明の実施の形態８における実装の工程を順に示す図である。
【図16】従来の半導体素子の実装方法による実装後の半導体素子と回路基板の接合断面図である。
【図17】従来の半導体素子の実装方法による実装後の半導体素子と回路基板の接合断面図である。
【図18】従来の半導体素子の実装方法による実装後の半導体素子と回路基板の接合断面図である。
【図19】従来の実装の工程を順に示す図である。
【図20】従来の実装方法の課題を説明する図である。
【図21】従来の実装方法の課題を説明する図である。
【符号の説明】
１ 半導体素子
２ 電極
３ 突起バンプ（メッキ法による）
４ 回路基板
５ 銅箔
６ 外部電極端子
７ 導電性ペースト
８ 孔部
９ スキージ
10 吸着ノズル
11 金属ワイヤ
12 金属ボール
13 キャピラリー
14 電極
15 突起バンプ（ワイヤボンディング法による）
16 パシベーション膜
17，19 ヒータ
18 ステージ
20 エポキシ系樹脂
21 樹脂シート
31 シリンジ
32 コンベヤ
33 外部電極端子

Claims (1)

  1. 回路基板の回路と半導体素子の電極を接続する前記回路基板の箇所に、貫通孔部を形成する工程と、
    前記貫通孔部に導電性ペーストを充填し外部電極端子を形成する工程と、
    前記半導体素子の電極に円錐形で尖った形状の突起バンプを形成する工程と、
    前記外部電極端子が形成された回路基板上、または前記半導体素子の突起バンプ上に、熱硬化系樹脂または熱可塑系樹脂または熱硬化と熱可塑の混合系樹脂を有する接着剤シートを配置する工程と、
    前記外部電極端子と前記半導体素子の前記電極に形成された前記突起バンプを位置決めする工程と、
    前記半導体素子を押圧し、前記接着剤シートを前記円錐形で尖った形状の突起バンプにより突き破り、前記貫通孔部内の前記導電性ペーストと前記突起バンプとを接触させ、前記半導体素子の前記電極と前記回路基板の前記外部電極端子とを電気的に接続する工程と、
    加熱ツールにより前記半導体素子を加熱し、前記接着剤シートを溶融し、硬化する工程と
    を有することを特徴とする半導体素子の実装方法。
JP14524196A 1996-06-07 1996-06-07 半導体素子の実装方法 Expired - Fee Related JP3610999B2 (ja)

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JP14524196A JP3610999B2 (ja) 1996-06-07 1996-06-07 半導体素子の実装方法
EP97925302A EP0844657A4 (en) 1996-06-07 1997-06-06 METHOD FOR MOUNTING A SEMICONDUCTOR CHIP
KR10-1998-0700903A KR100457609B1 (ko) 1996-06-07 1997-06-06 반도체소자의실장방법
US09/011,603 US6051093A (en) 1996-06-07 1997-06-06 Mounting method of semiconductor element
PCT/JP1997/001971 WO1997047031A1 (en) 1996-06-07 1997-06-06 Method for mounting semiconductor chip
CN97190666A CN1110078C (zh) 1996-06-07 1997-06-06 半导体元件的安装方法
US09/528,116 US6531022B1 (en) 1996-06-07 2000-03-17 Mounting method of semiconductor element

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0383301A2 (en) 1989-02-15 1990-08-22 Hitachi, Ltd. Method and apparatus for forming a film
US10174165B2 (en) 2014-04-24 2019-01-08 Jfe Chemical Corporation Poly(amic acid) composition and polyimide composition

Families Citing this family (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3176307B2 (ja) * 1997-03-03 2001-06-18 日本電気株式会社 集積回路装置の実装構造およびその製造方法
JP2000068327A (ja) * 1998-08-20 2000-03-03 Matsushita Electric Ind Co Ltd 部品の実装方法と装置
SG82591A1 (en) * 1998-12-17 2001-08-21 Eriston Technologies Pte Ltd Bumpless flip chip assembly with solder via
US6541872B1 (en) 1999-01-11 2003-04-01 Micron Technology, Inc. Multi-layered adhesive for attaching a semiconductor die to a substrate
JP4036555B2 (ja) * 1999-01-14 2008-01-23 松下電器産業株式会社 実装構造体の製造方法および実装構造体
JP3539315B2 (ja) * 1999-06-22 2004-07-07 株式会社村田製作所 電子デバイス素子の実装方法、および弾性表面波装置の製造方法
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
US6537400B1 (en) 2000-03-06 2003-03-25 Micron Technology, Inc. Automated method of attaching flip chip devices to a substrate
JP2001257453A (ja) * 2000-03-09 2001-09-21 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びそれらの製造方法
JP2001339011A (ja) * 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
US6538898B1 (en) 2000-05-01 2003-03-25 Micron Technology, Inc. Method and apparatus of die attachment for BOC and F/C surface mount
JP4759791B2 (ja) * 2000-07-27 2011-08-31 日亜化学工業株式会社 光半導体素子とその製造方法
US6678952B2 (en) * 2000-08-03 2004-01-20 Tessera, Inc. Method of making a microelectronic package including a component having conductive elements on a top side and a bottom side thereof
US6862189B2 (en) * 2000-09-26 2005-03-01 Kabushiki Kaisha Toshiba Electronic component, circuit device, method for manufacturing the circuit device, and semiconductor device
US6437669B1 (en) 2000-09-29 2002-08-20 Applied Micro Circuits Corporation Microwave to millimeter wave frequency substrate interface
KR20020046754A (ko) * 2000-12-15 2002-06-21 밍 루 표면실장용 인쇄회로 기판과 부품 실장 방법
JP2002198395A (ja) * 2000-12-26 2002-07-12 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US6543674B2 (en) * 2001-02-06 2003-04-08 Fujitsu Limited Multilayer interconnection and method
JP2002313840A (ja) * 2001-04-17 2002-10-25 Matsushita Electric Ind Co Ltd 半導体素子実装基板及びその製造方法
JP4051893B2 (ja) * 2001-04-18 2008-02-27 株式会社日立製作所 電子機器
CN1383197A (zh) * 2001-04-25 2002-12-04 松下电器产业株式会社 半导体装置的制造方法及半导体装置
US6504111B2 (en) * 2001-05-29 2003-01-07 International Business Machines Corporation Solid via layer to layer interconnect
DE10126655A1 (de) * 2001-06-01 2002-12-05 Endress & Hauser Gmbh & Co Kg Leiterplatte mit mindestens einem elektronischen Bauteil
CN101370361B (zh) * 2001-06-13 2010-09-08 株式会社电装 埋有电子器件的印刷线路板的制造方法
MXPA02005829A (es) * 2001-06-13 2004-12-13 Denso Corp Tablero de cableados impresos con dispositivo electrico incrustado y metodo para la manufactura de tablero de cableados impresos con dispositivo electrico incrustado.
US6660945B2 (en) * 2001-10-16 2003-12-09 International Business Machines Corporation Interconnect structure and method of making same
JP3615727B2 (ja) * 2001-10-31 2005-02-02 新光電気工業株式会社 半導体装置用パッケージ
US20030150645A1 (en) * 2002-02-12 2003-08-14 Chia-Pin Chiu Method and apparatus for coupling a microelectronic device package to a circuit board
JP3770237B2 (ja) * 2002-03-22 2006-04-26 セイコーエプソン株式会社 電子デバイス製造装置および電子デバイスの製造方法
US7754976B2 (en) * 2002-04-15 2010-07-13 Hamilton Sundstrand Corporation Compact circuit carrier package
KR100873041B1 (ko) * 2002-06-12 2008-12-09 삼성테크윈 주식회사 반도체 팩키지의 범프와 동박 회로 패턴 사이의 접속 방법및,그를 위한 반도체 팩키지의 범프 구조
US6964881B2 (en) * 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP4056424B2 (ja) * 2003-05-16 2008-03-05 シャープ株式会社 半導体装置の製造方法
JP3933094B2 (ja) 2003-05-27 2007-06-20 セイコーエプソン株式会社 電子部品の実装方法
US7408258B2 (en) * 2003-08-20 2008-08-05 Salmon Technologies, Llc Interconnection circuit and electronic module utilizing same
US7135397B2 (en) * 2003-09-10 2006-11-14 Texas Instruments Incorporated Method and system for packaging ball grid arrays
TW200520123A (en) * 2003-10-07 2005-06-16 Matsushita Electric Ind Co Ltd Method for mounting semiconductor chip and semiconductor chip-mounted board
US20050104180A1 (en) * 2003-11-14 2005-05-19 Vassoudevane Lebonheur Electronic device with reduced entrapment of material between die and substrate electrical connections
US20050184376A1 (en) * 2004-02-19 2005-08-25 Salmon Peter C. System in package
US20060044771A1 (en) * 2004-08-24 2006-03-02 Yeo Chee K Electronic module with conductive polymer
US7331503B2 (en) * 2004-10-29 2008-02-19 Intel Corporation Solder printing process to reduce void formation in a microvia
US7427809B2 (en) * 2004-12-16 2008-09-23 Salmon Technologies, Llc Repairable three-dimensional semiconductor subsystem
US20070007983A1 (en) * 2005-01-06 2007-01-11 Salmon Peter C Semiconductor wafer tester
JP4291279B2 (ja) * 2005-01-26 2009-07-08 パナソニック株式会社 可撓性多層回路基板
US7687400B2 (en) * 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US7560813B2 (en) 2005-06-14 2009-07-14 John Trezza Chip-based thermo-stack
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US7781886B2 (en) 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US7767493B2 (en) * 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7989958B2 (en) * 2005-06-14 2011-08-02 Cufer Assett Ltd. L.L.C. Patterned contact
US7851348B2 (en) * 2005-06-14 2010-12-14 Abhay Misra Routingless chip architecture
US8456015B2 (en) * 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7838997B2 (en) * 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US20060281303A1 (en) * 2005-06-14 2006-12-14 John Trezza Tack & fuse chip bonding
US7586747B2 (en) * 2005-08-01 2009-09-08 Salmon Technologies, Llc. Scalable subsystem architecture having integrated cooling channels
US20070023904A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Electro-optic interconnection apparatus and method
US20070023889A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Copper substrate with feedthroughs and interconnection circuits
US20070023923A1 (en) * 2005-08-01 2007-02-01 Salmon Peter C Flip chip interface including a mixed array of heat bumps and signal bumps
FR2894070B1 (fr) * 2005-11-30 2008-04-11 3D Plus Sa Sa Module electronique 3d
CN100438008C (zh) * 2006-03-01 2008-11-26 南茂科技股份有限公司 高频集成电路封装构造及其制造方法
WO2007125791A1 (ja) * 2006-04-24 2007-11-08 Alps Electric Co., Ltd. 配線基板の製造方法
US20070281460A1 (en) * 2006-06-06 2007-12-06 Cubic Wafer, Inc. Front-end processed wafer having through-chip connections
US7687397B2 (en) * 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
CN101447443B (zh) * 2006-08-15 2010-06-02 南茂科技股份有限公司 高频集成电路封装构造的制造方法
KR101292634B1 (ko) * 2006-09-11 2013-08-16 파나소닉 주식회사 전자부품 탑재장치 및 전자부품 실장방법
JPWO2008047918A1 (ja) * 2006-10-20 2010-02-25 日本電気株式会社 電子機器のパッケージ構造及びパッケージ製造方法
US7670874B2 (en) * 2007-02-16 2010-03-02 John Trezza Plated pillar package formation
US20080206516A1 (en) * 2007-02-22 2008-08-28 Yoshihiko Matsushima Surface mount circuit board, method for manufacturing surface mount circuit board, and method for mounting surface mount electronic devices
US8210424B2 (en) * 2010-09-16 2012-07-03 Hewlett-Packard Development Company, L.P. Soldering entities to a monolithic metallic sheet
JP5183708B2 (ja) * 2010-09-21 2013-04-17 株式会社日立製作所 半導体装置およびその製造方法
EP2463809A1 (fr) * 2010-12-07 2012-06-13 NagraID S.A. Carte électronique à contact électrique comprenant une unité électronique et/ou une antenne
WO2012084291A1 (en) * 2010-12-21 2012-06-28 Microconnections Sas Method of manufacturing a surface mounted device and corresponding surface mounted device
JP5533914B2 (ja) * 2011-08-31 2014-06-25 株式会社デンソー 多層基板
KR101388739B1 (ko) * 2012-04-27 2014-04-25 삼성전기주식회사 반도체 패키지
JP2014192476A (ja) * 2013-03-28 2014-10-06 Fujitsu Ltd プリント基板の半田実装方法及び半田実装構造
WO2015039771A1 (en) * 2013-09-17 2015-03-26 Abb Technology Ag Method for ultrasonic welding with particles trapping
TWI509756B (zh) * 2013-09-30 2015-11-21 Chipmos Technologies Inc 薄膜覆晶封裝結構
CN103682043A (zh) * 2013-11-28 2014-03-26 天津金玛光电有限公司 一种水平式led芯片的固晶方法及采用该方法制备的led光源
DE102014008756A1 (de) * 2014-06-12 2015-12-17 Pfisterer Kontaktsysteme Gmbh Vorrichtung zum Kontaktieren eines elektrischen Leiters sowie Anschluss- oder Verbindungseinrichtung mit einer solchen Vorrichtung
JP6519714B2 (ja) * 2016-08-26 2019-05-29 株式会社村田製作所 樹脂多層基板、伝送線路、モジュールおよびモジュールの製造方法
JP2018064063A (ja) 2016-10-14 2018-04-19 イリソ電子工業株式会社 回路基板及び回路装置
WO2018098649A1 (zh) * 2016-11-30 2018-06-07 深圳修远电子科技有限公司 集成电路封装方法以及集成封装电路
CN110088884A (zh) * 2016-11-30 2019-08-02 深圳修远电子科技有限公司 集成电路多芯片层叠封装结构以及方法
CN106816417B (zh) * 2017-01-13 2019-02-12 南京大学 一种高密度封装及其制造方法
KR102432216B1 (ko) * 2017-07-11 2022-08-12 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 발광소자 패키지
CN107949166B (zh) * 2017-11-30 2020-04-14 广州兴森快捷电路科技有限公司 埋置元件电路板的制作方法及埋置元件电路板
JP7269347B2 (ja) 2018-08-22 2023-05-08 リキッド ワイヤ インコーポレイテッド 変形可能な導体を有する構造体
CN110324984B (zh) * 2019-07-26 2020-01-17 微智医疗器械有限公司 电子元件与电路板的连接方法、电路板组件及电子设备
CN111540722B (zh) * 2020-07-07 2021-05-14 甬矽电子(宁波)股份有限公司 芯片封装结构及封装方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5267394A (en) * 1975-03-31 1977-06-03 Hitachi Ltd Eluate programing device
JPS60126856A (ja) * 1983-12-13 1985-07-06 Sanyo Electric Co Ltd 半導体装置の組立方法
US5014111A (en) * 1987-12-08 1991-05-07 Matsushita Electric Industrial Co., Ltd. Electrical contact bump and a package provided with the same
JPH01198040A (ja) * 1988-02-03 1989-08-09 Omron Tateisi Electron Co 半導体素子の実装法
JP2833111B2 (ja) * 1989-03-09 1998-12-09 日立化成工業株式会社 回路の接続方法及びそれに用いる接着剤フィルム
JPH039278A (ja) * 1989-06-07 1991-01-17 Toshiba Corp 故障点標定装置用サージ受信装置
JP2786734B2 (ja) * 1990-09-28 1998-08-13 株式会社東芝 半導体装置
DE69118308T2 (de) * 1990-10-24 1996-08-08 Nec Corp Verfahren zur Herstellung einer elektrischen Verbindung für eine integrierte Schaltung
JP2940269B2 (ja) * 1990-12-26 1999-08-25 日本電気株式会社 集積回路素子の接続方法
JPH04267394A (ja) * 1991-02-22 1992-09-22 Tatsuta Electric Wire & Cable Co Ltd フレキシブルプリント板
JP3166251B2 (ja) * 1991-12-18 2001-05-14 株式会社村田製作所 セラミック多層電子部品の製造方法
JPH05267394A (ja) * 1992-03-19 1993-10-15 Sumitomo Electric Ind Ltd 半導体素子の実装方法
KR950012658B1 (ko) * 1992-07-24 1995-10-19 삼성전자주식회사 반도체 칩 실장방법 및 기판 구조체
JPH0669278A (ja) * 1992-08-18 1994-03-11 Toshiba Corp 半導体素子の接続方法
WO1996008037A1 (en) * 1994-09-06 1996-03-14 Sheldahl, Inc. Printed circuit substrate having unpackaged integrated circuit chips directly mounted thereto and method of manufacture
US5742100A (en) * 1995-03-27 1998-04-21 Motorola, Inc. Structure having flip-chip connected substrates
US5848466A (en) * 1996-11-19 1998-12-15 Motorola, Inc. Method for forming a microelectronic assembly
JPH1198040A (ja) * 1997-09-19 1999-04-09 Fujitsu General Ltd 発電機能付衛星受信アンテナ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0383301A2 (en) 1989-02-15 1990-08-22 Hitachi, Ltd. Method and apparatus for forming a film
US10174165B2 (en) 2014-04-24 2019-01-08 Jfe Chemical Corporation Poly(amic acid) composition and polyimide composition

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WO1997047031A1 (en) 1997-12-11
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