WO1997047031A1 - Method for mounting semiconductor chip - Google Patents
Method for mounting semiconductor chip Download PDFInfo
- Publication number
- WO1997047031A1 WO1997047031A1 PCT/JP1997/001971 JP9701971W WO9747031A1 WO 1997047031 A1 WO1997047031 A1 WO 1997047031A1 JP 9701971 W JP9701971 W JP 9701971W WO 9747031 A1 WO9747031 A1 WO 9747031A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- self
- circuit board
- electrode
- bump
- conductive paste
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 80
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000003825 pressing Methods 0.000 claims abstract description 9
- 239000003822 epoxy resin Substances 0.000 claims description 14
- 229920000647 polyepoxide Polymers 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000003795 chemical substances by application Substances 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000009940 knitting Methods 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 229920001169 thermoplastic Polymers 0.000 claims description 2
- 239000004416 thermosoftening plastic Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 17
- 230000000694 effects Effects 0.000 description 11
- 210000000689 upper leg Anatomy 0.000 description 11
- 239000000835 fiber Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 239000004033 plastic Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 239000011094 fiberboard Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 235000003642 hunger Nutrition 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000003134 recirculating effect Effects 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 239000010979 ruby Substances 0.000 description 1
- 229910001750 ruby Inorganic materials 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 230000037351 starvation Effects 0.000 description 1
- 238000004073 vulcanization Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
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- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
- Y10T156/1092—All laminae planar and face to face
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention relates to a semiconductor element mounting method for mounting a flip-chip type semiconductor element with high reliability and high density on a circuit board of the semiconductor element.
- FIG. 16 shows a cross-sectional view in which the semiconductor element of Conventional Example 1 is mounted on a circuit board.
- reference numeral 1 denotes a semiconductor element.
- An electrode 2 is formed on the semiconductor element 1, and a projection bump (metal ball bump) made of gold, copper, aluminum, solder, or the like is formed on the electrode 2 by a wire bonding method. Are formed.
- Reference numeral 4 denotes a circuit board made of an insulating substrate, on which a copper foil 5 serving as wiring is formed, and on the circuit board 4, copper-plated external electrode terminals 6 are formed. A hole 8 formed in the circuit board 4 is filled with a conductive paste 7 to conduct the inside.
- Reference numeral 22 denotes a conductive paste (conductive adhesive) in which conductive powder such as silver, gold, nickel, or carbon is uniformly dispersed in phenol or epoxy resin.
- the electrodes 2 are electrically connected via the bumps 15, and the epoxy resin 20 is filled between the circuit board 4 and the semiconductor element 1.
- the conductive paste 22 After transferring the conductive paste 22 to the projecting bumps 15 formed on the electrodes 2 of the semiconductor element 1 by a transfer method, the conductive paste 22 is mounted so as to match the external electrode terminals 6 of the circuit board 4 to be mounted.
- the conductive paste 22 is cured by heating, and the electrode 2 of the semiconductor element 1 and the external electrode terminal 6 of the circuit board 4 are electrically connected.
- the space between the semiconductor element 1 and the circuit board 4 is filled with an epoxy resin 20, and by utilizing the curing shrinkage force, continuous contact of the conductive powder of the conductive paste 22 is obtained. Electrical and mechanical reliability is ensured. (Conventional example 2)
- FIG. 17 is a drawing in which the ⁇ element in the conventional example 2 is mounted at the time ⁇ ".
- the same components as those in the above-described FIG. 16 are denoted by the same ⁇ -, and description thereof is omitted.
- reference numeral 23 denotes a metal bump formed on the metal bump 2 by a plating method.
- the gold bump 23 is formed on the metal bump 23, for example, a copper plating metal.
- 25 is an external element
- 16 is a passivation film for protecting the active surface of the element 1.
- the circuit After transferring the conductive paste 22 to the pot bumps 23 formed on each 2 of the element 1 by rolling, the circuit is mounted so as to be connected to the external SW 25 of the circuit ⁇ ⁇ 4 to be mounted, and is heated and heated. Hardens the conductive paste 22 and removes
- the epoxy resin 20 is applied to the space between the ⁇ element 1 and the circuit ⁇ 4, and the rigidity and force of the epoxy resin 20 are used so that the conductive paste 22 can be applied to the conductive paste 22 in mm. Ensure the target and the target.
- FIG. 18 a diagram in which the elements in FIG. 3 are mounted on a circuit board is shown as "".
- the same components as those in FIGS. 16 and 17 are denoted by the same shuttle and the description is omitted.
- 3 is a Wei bump formed on the view 2 by the plating method
- 26 is a ⁇ coating film
- the ⁇ 27 film is a conductor made of nickel, solder, carbon, or the like. The following is an explanation of the method of realizing the ⁇ * element-element constructed as described above.
- the thigh-attachment adhesive film 26 is positioned between the ⁇ element 1 and the outer! As a result, the agent film 26 melts and leaks into the space between the holes 25, and the deflector 27 is fixed and held by the bump 3 and the outer arm 25. On the other hand, in the space, the teacher is kept in order to keep the chin dispersed in the agent.
- the crane film 2G cures when ⁇ 3 ⁇ 4 ⁇ ⁇ ⁇ , fixing the element 1 and the recirculating layer 4 to ensure the properties.
- the conductive paste film 28 is transferred to the wei bump 15 by the transfer method as shown in FIG.
- the epoxy shelf 20 when the epoxy shelf 20 is placed in the gap between the ⁇ 1 element and the circuit board 4, the epoxy resin 20 encapsulated in the syringe 31 is used as the ⁇ element.
- the present invention does not cause a defect such as short circuit or open between the components, can provide a mounting with high electrical clarity, can achieve a significant time equivalent to the sealing time, and can reduce the tact time of the element line.
- the purpose of this method is to implement the ⁇ method of ⁇ elements in which is a possible factor.
- the method for mounting a semiconductor device according to the present invention includes the steps of:
- FIG. 1 is a joint iff diagram of a mounted ⁇ element and an assemblage plate in embodiment 1 of the present invention.
- FIG. 2 is a diagram showing the order of mounting steps in the difficult embodiment 1 of the present invention in order.
- FIG. 3 is a diagram showing the connection between the ⁇ element and the assemblage plate after mounting according to the first embodiment of the present invention. ® Drawing.
- FIG. 4 is a cross-sectional view of the junction between the ⁇ -element and the circuit board after mounting in Embodiment 1 of the present invention.
- FIG. 5 shows the steps of the wire bonding method according to the second embodiment of the present invention in order.
- FIG. 6 is a plan view of a pump formed by a wire bonding method according to the second embodiment of the present invention.
- FIG. 7 is an elevation view of a two-step bump formed by a wire bonding method in Difficulty Mode 2 of the present invention.
- FIG. 8 is a sequence chart of a mounting process according to the second embodiment of the present invention.
- FIG. 9 is a diagram showing a mounting process according to the third embodiment of the present invention.
- FIG. 10 is a diagram showing a mounting process according to the fourth embodiment of the present invention.
- Fig. 11 is a T diagram showing difficult steps in starvation mode 5 of the present invention.
- Fig. 12 is a T diagram showing mounting steps in embodiment 6 of the present invention.
- FIG. 13 is a diagram of the ⁇ element and the thigh plate after mounting in Difficult Mode 6 of the present invention.
- FIG. 14 is a diagram of the mounting steps in the form 7 of the embodiment of the present invention in the order of ⁇ T.
- FIG. 15 is a diagram sequentially illustrating a mounting process in Embodiment 8 of the present invention.
- FIG. 16 is a diagram of the element and the thigh plate after mounting according to the conventional method of the ⁇ element.
- FIG. 17 is a diagram of a conventional device and a thigh plate after mounting by a real method of the present invention.
- FIG. 18 is a cross-sectional view of the joint between the element and the thigh plate after mounting according to the conventional method of mounting the ⁇ * element.
- FIG. 19 is a diagram illustrating the steps of the conventional mounting in order.
- FIG. 20 is a diagram for explaining a problem of a conventional mounting method.
- FIG. 21 is a diagram for explaining a conventional method.
- the invention of fllfe described in claim 1 of the present invention is a process of forming a hole in a side of a self-thigh plate for fiber winding a circuit and an element of a circuit, and a step of applying a conductive paste to the self-hole of the knitting and externally forming the hole.
- This is a practical method of a special element that has a process and a process of forming a bump. It has the effect of being sick.
- the invention of claim 2 is the method of claim 1, wherein the wei bumps formed on the shoe element are pot ball bumps formed by a wire bonding method.
- This method is a real method of a ⁇ element, and the Wei bump is formed by the observing method, but only a bump with a height as small as 25 m can be formed by using the wire bonding method. Since a bump with a height of 0 / m or more can be formed, the amount of bump buried in the conductive base in the hole of the thigh plate increases, and the effect of mounting a more flexible mounting can be obtained. Have.
- the invention according to claim 3 is a method for realizing an element of claim 1 or 2, wherein the element is pressed, and the conductive paste of the circuit board hole and the ⁇ element m After contacting the projecting bumps, the heating tool heats at least one of the element and the circuit board, and performs a step of curing the conductive paste.
- the heating tool heats at least one of the element and the circuit board, and performs a step of curing the conductive paste.
- the solidification of the element and the circuit becomes stronger and a more reliable connection can be made.
- the same equipment can be used at the same time, which has the effect of leading to the takt time of the production line of the element.
- the invention according to claim 4 is the mounting method of the ⁇ element according to any one of claims 1 to 3, wherein an electrode of the ⁇ element is connected to an external electrode of the circuit. After that, the epoxy resin is filled in the gap between the self-device and the carrier plate, and the sealing process is performed. Since the surface and the surface of the view are protected by the epoxy-based resin, it has a more positive effect.
- the invention of claim 5 is a step of forming a hole in a portion of the circuit board that connects the circuit of the circuit board and the ⁇ element, and a step of forming a conductive paste on the reading hole part by applying a conductive paste to the external element.
- It is a fiber that has a process that dislikes ⁇ ⁇ in mm and a process of heating the iui self ⁇ ⁇ element with a heating tool to melt and cure the medicament sheet ⁇ ⁇
- the crane agent sheet is melted and hardened, it protects the active surface of the ⁇ element and the surface of 3 ⁇ 4 ⁇ . It takes about 30 seconds for the epoxy resin Since the curing time is significantly shorter than about 4 hours, it has the effect of leading to the tact of the device sales line.
- FIG. 1 is a cross-sectional view of a circuit board on which a semiconductor device according to Embodiment 1 of the present invention is mounted.
- the bumps 3 formed on the element 2 of the element 1 are thighs buried in the conductive paste 7 formed in the holes 8 of the circuit fiber 4, and the thigh plate 4
- the external element 6 of the present invention is easily connected to the element 2 of the ⁇ element 1.
- the actual method of the ⁇ element of the present invention will be described with reference to the process chart of Fig. 2.
- a hole 8 is formed at the location of the circuit fiber 4 that connects the external element 6 of the circuit board 4 and the electrode 2 of the semiconductor element 1, and a conductive material is formed as shown in FIG.
- the paste 7 is printed in the hole 8 of the Tsurumi crotch board 4 by moving the squeegee 9 to form the outer element 33 of the circuit board 4.
- the ⁇ element 1 is caused to pass through the nozzle 10 as indicated by ⁇ "T, and the pump 3 formed by the release pad 3 and the conductive paste 7 formed in the hole 8 is formed. ⁇ Align with the external electrode 33 of 4.
- the element 1 is pressed by the nozzle 10, as shown in FIG. 2 (c), and the bump 3 is formed in the hole 8 of the circuit board 4 as shown in FIG. 2 (d). Embedded in the conductive base 7.
- the electrode 3 of the element 1 becomes the conductive paste 7 in the hole of the circuit board 4, and is formed.
- circuit 4 is a multilayer substrate in which conduction between the inner layers of the substrate is achieved by inner via holes as shown by ⁇ T in FIG. 3, but conduction between layers is achieved by through holes as shown in FIG. It may be a multilayer substrate taken.
- the solder bump formed on the job 2 of the element 1 the force 3 was difficult to be buried in the conductive paste 7 in the hole 8 of the thigh plate 4, and the connection was like a crane.
- short-circuit power is not generated, and reversal of 1 ⁇ 23 ⁇ 43 ⁇ 44 warp and swell 5 T
- the range of capability is expanded, the open power is not generated, and the ⁇ 1 element 1 and the circuit board 4 can be connected with high visibility.
- FIG. 5 is a process diagram of the fiS ⁇ method of the semi-element m's ⁇ bump using the wire bonding method in the SS form 2 of the present invention.
- the wire bonding method will be described with reference to FIG. I do.
- a wire 11 made of gold, copper, aluminum, solder, etc. is passed through a capillary 13 made of ceramic ruby, and the pot wire 11 passed through is called a torch.
- the fi ⁇ ball 12 is pressed on the «®2> of the pre-heated element 1 and ultrasonic vibration is applied, and the temperature, pressure, The metal ball 12 is joined to the electrode 2 by the action of the sonic vibration.
- the capillary 13 is raised in the vertical direction, and the wire 11 is torn off to form a bump 15 made of a metal ball as shown in FIG. Then, as shown in Fig. 5 (d), after raising the capillary 13, the metal wire 1
- the capillary 13 Without tearing 1, the capillary 13 is moved sideways, and the wire 11 is put on the ball 12, and the metal wire 11 is turned into the metal ball 12 by the action of, pressure, or ⁇ supersonic «fj.
- the ⁇ element 1 and the circuit board 4 are formed by the ⁇ 1 " ⁇ method in Fig. 8.
- the real ⁇ method in FIG. 8 is the same as the method described in Embodiment 1 of s3 ⁇ 4m above, and description thereof will be omitted.
- Form 2 of Jong in addition to the effect of Form 1 of Wei, when bumps are formed by an electric plating method, only bumps as low as 25 / m can be formed, even if they are silent. 50 / m by wire bonding method As shown in FIG. 8 (e), the bumps 15 buried in the conductive base 7 in the holes 8 of the thigh plate 4 are increased in the amount of the bumps 15. The tolerance for warpage and swell is widened, and more sophisticated mounting can be performed.
- FIG. 9 shows that ⁇ element 1 was used as! Nozzle 10 and was aligned with the outer element of ⁇ ⁇ board 4 formed by ⁇ bump 3 and conductive paste 7 filled in hole 8. After that, it is pressed and embedded in the Wei Bump 3 force paste 7. At this time, the i3 ⁇ 43 ⁇ 4 nozzle 10 is heated by the built-in heater 17, so that the conductive paste 7 is hardened simultaneously with the pressing.
- the conductive paste 7 is hardened so that the fixation of the ⁇ element 1 and the ⁇ ⁇ plate 4 can be further strengthened.
- the conductive paste 7 can be cured with the same equipment as the conventional one, whereas the module can be cured in the oven furnace. The takt time of the production line can be shortened.
- FIG. 10 shows that the ⁇ element 1 is connected to the chip 10 and is aligned with the external element 33 of the ⁇ plate 4 formed by the conductive paste 7 filled in the bumps 3 and the holes 8. After performing, it is pressed and shows the pillow state embedded in the Wei Bump 3 power conductive paste 7. At this time, the stage 18 holding the circuit 4 is heated by the built-in heater 17, and by applying heat when the element 1 is pressed, the conductive paste 7 is cured at the same time as the element 1 is pressed. ing.
- the conductive paste 7 is hardened, so that the fixing of the ⁇ element 1 and the circuit board 4 is stronger.
- a module for example G by entering Tutsi oven furnace, and for enabling the same equipment at the same time, half ⁇ element It can reduce the takt time of the production line.
- the ⁇ ⁇ element 1 is pressed, and the conductive paste 7 in the hole 8 of the thigh plate 4 and the wei bump 15 on the ⁇ element 1 are released.
- the module (circular plate 4 and ⁇ element 1) is placed on the conveyor 32, and the entire module is urged by the heater 19 while moving, so that the conductive paste 7 is cured.
- the hardening of the conductive paste 7 is carried out by placing the entire module on the conveyor 32 and reflowing by heating while moving; It is possible to cure on the same production line as mounting,
- the active surface of the element 1 and the surface force of the easy2 are reduced by the epoxy resin 20 as shown in FIG. Therefore, for example, even if the module is exposed to occupation such as high temperature and high humidity, it can prevent the corrosion of No. 2 and Wei bump 3, and can perform more highly resistant L and ⁇ .
- the conductive paste 7 is woven into the hole 8 of the thigh plate 4 to form an external fiber 33, and then a vulcanization system or heat is applied on the tread plate 4.
- a crane sheet 21 made of a plastic-based resin or a mixed resin composed of a plastic and a thermoplastic resin is distributed.
- the crane sheet 21 has nickel, solder, carbon, gold-plated plastic particles, and the like uniformly dispersed therein.
- the ⁇ element 1 is adsorbed to the adsorption nozzle 10 and the circuit board 4 formed by the conductive paste 7 formed in the hole 8 and the hole 8 is sucked by the suction nozzle 10. Align with the external ®M 33.
- the ⁇ element 1 is pressed, the crane agent sheet 21 is pierced by the Wei bump 15, and the Wei bump 15 is embedded in the conductive paste 7.
- the suction nozzle 10 is heated by the heater 17 is built, the pressing at the same time ⁇ 3 ⁇ 4 Zaishiichito 21 om ⁇ curing Ca ⁇ 1 over.
- the agent sheet 21 melts and hardens, and the surface of the element 1 is protected and the surface of the element 1 is protected.
- the time required for curing is 30 seconds, which is much shorter than the curing time of the epoxy resin of about 4 hours, so the tact time of the ⁇ 1 element 1 line can be reduced.
- a wei bump is formed on the noise 2 of the ⁇ element 1, and then a ⁇ ⁇ ⁇ h3 ⁇ 4 or thermoplastic resin is formed on the wei bump 15 in advance.
- Dispersion sheet 21 made of the mixed resin is distributed.
- the crane sheet 21 may be made by uniformly dispersing nickel, solder, carbon, gold-plated plastic particles, and the like.
- ⁇ element 1 is adsorbed to adsorption nozzle 10 and Circuit formed by the conductive paste 7 formed in the bumps 15 and the holes 8.
- the crane sheet 21 is pierced by the weft bump 15, and the difficult bump 15 is embedded in the conductive paste 7.
- the IW nozzle 10 is heated by a built-in heater 17, and is melted and hardened at the same time as the pressing is performed.
- the ⁇ agent sheet 21 is melted and hardened.
- the pressure * time for curing is 13 ⁇ 430 seconds, and the curing time of the epoxy resin is about 4 hours. L is significantly shorter, so the tact time of the 1 line of element 1 is 51 g.
- the Wei bumps formed in the mil of the ⁇ element can be formed by a number of times!
- a short circuit between m3 ⁇ 4 can be avoided, and the circuit board can be warped or undulated. Since the range is wide, it is possible to avoid an open between 3 ⁇ 4 and ⁇ , and it is possible to implement with high m-specificity.
- the ⁇ agent sheet is placed in advance on the circuit board ⁇ h or on the projecting bump of the ⁇ ⁇ element, and at this time, the ⁇ bump is pierced through the agent sheet and rotated * & ⁇
- the conductive paste in the plate hole By melting and curing the agent sheet, the active surface of the ⁇ element and the surface of the ⁇ element can be spun with the agent sheet, and the H In the case of a crane sheet, the time required for pressing and curing is 30 seconds, which is much shorter than the curing time of epoxy resin, about 4 hours. Significant reduction can be achieved, and the tact time of ⁇ # ⁇ * element ⁇ line can be reduced to ⁇ m.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97925302A EP0844657A4 (en) | 1996-06-07 | 1997-06-06 | METHOD FOR MOUNTING A SEMICONDUCTOR CHIP |
US09/011,603 US6051093A (en) | 1996-06-07 | 1997-06-06 | Mounting method of semiconductor element |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14524196A JP3610999B2 (ja) | 1996-06-07 | 1996-06-07 | 半導体素子の実装方法 |
JP8/145241 | 1996-06-07 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/528,116 Continuation US6531022B1 (en) | 1996-06-07 | 2000-03-17 | Mounting method of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997047031A1 true WO1997047031A1 (en) | 1997-12-11 |
Family
ID=15380594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1997/001971 WO1997047031A1 (en) | 1996-06-07 | 1997-06-06 | Method for mounting semiconductor chip |
Country Status (6)
Country | Link |
---|---|
US (2) | US6051093A (ja) |
EP (1) | EP0844657A4 (ja) |
JP (1) | JP3610999B2 (ja) |
KR (1) | KR100457609B1 (ja) |
CN (1) | CN1110078C (ja) |
WO (1) | WO1997047031A1 (ja) |
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Also Published As
Publication number | Publication date |
---|---|
EP0844657A4 (en) | 1999-04-14 |
CN1110078C (zh) | 2003-05-28 |
KR19990036235A (ko) | 1999-05-25 |
JPH09326419A (ja) | 1997-12-16 |
JP3610999B2 (ja) | 2005-01-19 |
US6531022B1 (en) | 2003-03-11 |
CN1195422A (zh) | 1998-10-07 |
EP0844657A1 (en) | 1998-05-27 |
US6051093A (en) | 2000-04-18 |
KR100457609B1 (ko) | 2005-01-15 |
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