CN110088884A - 集成电路多芯片层叠封装结构以及方法 - Google Patents
集成电路多芯片层叠封装结构以及方法 Download PDFInfo
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- CN110088884A CN110088884A CN201680090817.XA CN201680090817A CN110088884A CN 110088884 A CN110088884 A CN 110088884A CN 201680090817 A CN201680090817 A CN 201680090817A CN 110088884 A CN110088884 A CN 110088884A
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- 238000010030 laminating Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 252
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 18
- 230000009471 action Effects 0.000 claims abstract description 5
- 239000011799 hole material Substances 0.000 claims description 123
- 230000003014 reinforcing effect Effects 0.000 claims description 29
- 238000005538 encapsulation Methods 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 238000004806 packaging method and process Methods 0.000 claims description 24
- 239000004020 conductor Substances 0.000 claims description 17
- 238000004891 communication Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 300
- 239000000463 material Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 14
- 239000011241 protective layer Substances 0.000 description 13
- 238000007747 plating Methods 0.000 description 12
- 230000004224 protection Effects 0.000 description 6
- 238000007740 vapor deposition Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 230000002708 enhancing effect Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 208000027418 Wounds and injury Diseases 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- BCAARMUWIRURQS-UHFFFAOYSA-N dicalcium;oxocalcium;silicate Chemical compound [Ca+2].[Ca+2].[Ca]=O.[O-][Si]([O-])([O-])[O-] BCAARMUWIRURQS-UHFFFAOYSA-N 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004100 electronic packaging Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- 210000001503 joint Anatomy 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000003032 molecular docking Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- -1 101 Substances 0.000 description 1
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011536 re-plating Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000000930 thermomechanical effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
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- H01L2924/351—Thermal stress
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Abstract
本发明涉及提供一种集成电路多芯片层叠封装结构以及方法,其中,集成电路多芯片层叠封装结构包括:第一芯片的底面设有第一引脚;第二芯片的顶面设有第二引脚;基板的顶面设有电路层、或/和基板的底面设有电路层、或/和基板内设有电路层;第一芯片设于基板的顶面,第二芯片设于第一芯片的顶面;第一引脚至少与其中一个电路层电连接:电路层设有电路引脚,基板设有连接通孔,连接通孔与电路引脚对接,连接通孔的第一开口与第一引脚对接,连接通孔的第二开口为操作窗口,连接通孔内设有导电层,导电层将第一引脚和电路引脚电连接;第二引脚至少与其中一个电路层电连接:第二引脚与电路层通过导电引线电连接。芯片与电路层连接的密度高,体积小。
Description
PCT国内申请,说明书已公开。
Claims (13)
- PCT国内申请,权利要求书已公开。
Applications Claiming Priority (1)
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PCT/CN2016/107831 WO2018098647A1 (zh) | 2016-11-30 | 2016-11-30 | 集成电路多芯片层叠封装结构以及方法 |
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Country Status (3)
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WO2018098649A1 (zh) * | 2016-11-30 | 2018-06-07 | 深圳修远电子科技有限公司 | 集成电路封装方法以及集成封装电路 |
US20210358883A1 (en) * | 2018-10-11 | 2021-11-18 | Shenzhen Xiuyi Investment Development Partnership (Limited Partnership) | Fan-out packaging method employing combined process |
USD920266S1 (en) * | 2019-09-29 | 2021-05-25 | China Chippacking Technology Co., Ltd. | Integrated circuit package |
USD920265S1 (en) * | 2019-09-29 | 2021-05-25 | China Chippacking Technology Co., Ltd. | Integrated circuit package |
CN115064488B (zh) * | 2022-08-18 | 2022-11-01 | 成都复锦功率半导体技术发展有限公司 | 一种芯片互连封装结构及其制备方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5870289A (en) * | 1994-12-15 | 1999-02-09 | Hitachi, Ltd. | Chip connection structure having diret through-hole connections through adhesive film and wiring substrate |
CN1484308A (zh) * | 2002-09-17 | 2004-03-24 | ���˻�˹�����̩�˹ɷ�����˾ | 开口式多芯片堆叠封装体 |
CN2805094Y (zh) * | 2004-12-30 | 2006-08-09 | 威宇科技测试封装有限公司 | 一种无垫层的多芯片堆叠封装结构 |
US20130049179A1 (en) * | 2011-08-24 | 2013-02-28 | Tessera, Inc. | Low cost hybrid high density package |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3610999B2 (ja) * | 1996-06-07 | 2005-01-19 | 松下電器産業株式会社 | 半導体素子の実装方法 |
JP3349058B2 (ja) * | 1997-03-21 | 2002-11-20 | ローム株式会社 | 複数のicチップを備えた半導体装置の構造 |
US6175158B1 (en) | 1998-09-08 | 2001-01-16 | Lucent Technologies Inc. | Interposer for recessed flip-chip package |
SG93191A1 (en) | 1999-01-28 | 2002-12-17 | United Microelectronics Corp | Multi-chip chip-scale integrated circuit package |
KR100533673B1 (ko) * | 1999-09-03 | 2005-12-05 | 세이코 엡슨 가부시키가이샤 | 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기 |
US6497943B1 (en) * | 2000-02-14 | 2002-12-24 | International Business Machines Corporation | Surface metal balancing to reduce chip carrier flexing |
JP4512545B2 (ja) * | 2005-10-27 | 2010-07-28 | パナソニック株式会社 | 積層型半導体モジュール |
US7663216B2 (en) * | 2005-11-02 | 2010-02-16 | Sandisk Corporation | High density three dimensional semiconductor die package |
US7323774B2 (en) * | 2006-01-11 | 2008-01-29 | Stats Chippac Ltd. | Integrated circuit package system with pedestal structure |
US7719122B2 (en) * | 2007-01-11 | 2010-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | System-in-package packaging for minimizing bond wire contamination and yield loss |
US7960827B1 (en) * | 2009-04-09 | 2011-06-14 | Amkor Technology, Inc. | Thermal via heat spreader package and method |
US20100327419A1 (en) * | 2009-06-26 | 2010-12-30 | Sriram Muthukumar | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
US8841765B2 (en) * | 2011-04-22 | 2014-09-23 | Tessera, Inc. | Multi-chip module with stacked face-down connected dies |
US9953907B2 (en) * | 2013-01-29 | 2018-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | PoP device |
US10103128B2 (en) * | 2013-10-04 | 2018-10-16 | Mediatek Inc. | Semiconductor package incorporating redistribution layer interposer |
US10074628B2 (en) * | 2013-10-04 | 2018-09-11 | Mediatek Inc. | System-in-package and fabrication method thereof |
JP2016192447A (ja) * | 2015-03-30 | 2016-11-10 | 株式会社東芝 | 半導体装置 |
-
2016
- 2016-11-30 CN CN201680090817.XA patent/CN110088884A/zh active Pending
- 2016-11-30 WO PCT/CN2016/107831 patent/WO2018098647A1/zh active Application Filing
- 2016-11-30 US US16/465,229 patent/US10615151B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5870289A (en) * | 1994-12-15 | 1999-02-09 | Hitachi, Ltd. | Chip connection structure having diret through-hole connections through adhesive film and wiring substrate |
CN1484308A (zh) * | 2002-09-17 | 2004-03-24 | ���˻�˹�����̩�˹ɷ�����˾ | 开口式多芯片堆叠封装体 |
CN2805094Y (zh) * | 2004-12-30 | 2006-08-09 | 威宇科技测试封装有限公司 | 一种无垫层的多芯片堆叠封装结构 |
US20130049179A1 (en) * | 2011-08-24 | 2013-02-28 | Tessera, Inc. | Low cost hybrid high density package |
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US20190326261A1 (en) | 2019-10-24 |
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