CN110088884A - 集成电路多芯片层叠封装结构以及方法 - Google Patents

集成电路多芯片层叠封装结构以及方法 Download PDF

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Publication number
CN110088884A
CN110088884A CN201680090817.XA CN201680090817A CN110088884A CN 110088884 A CN110088884 A CN 110088884A CN 201680090817 A CN201680090817 A CN 201680090817A CN 110088884 A CN110088884 A CN 110088884A
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China
Prior art keywords
chip
substrate
pin
layer
circuit
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Inventor
胡川
刘俊军
郭跃进
爱德华·鲁道夫·普莱克
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Shenzhen Xiuyuan Electronic Technology Co ltd
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Shenzhen Xiuyuan Electronic Technology Co ltd
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Abstract

本发明涉及提供一种集成电路多芯片层叠封装结构以及方法，其中，集成电路多芯片层叠封装结构包括：第一芯片的底面设有第一引脚；第二芯片的顶面设有第二引脚；基板的顶面设有电路层、或/和基板的底面设有电路层、或/和基板内设有电路层；第一芯片设于基板的顶面，第二芯片设于第一芯片的顶面；第一引脚至少与其中一个电路层电连接：电路层设有电路引脚，基板设有连接通孔，连接通孔与电路引脚对接，连接通孔的第一开口与第一引脚对接，连接通孔的第二开口为操作窗口，连接通孔内设有导电层，导电层将第一引脚和电路引脚电连接；第二引脚至少与其中一个电路层电连接：第二引脚与电路层通过导电引线电连接。芯片与电路层连接的密度高，体积小。

Description

PCT国内申请，说明书已公开。

Claims (13)

  1. PCT国内申请，权利要求书已公开。
CN201680090817.XA 2016-11-30 2016-11-30 集成电路多芯片层叠封装结构以及方法 Pending CN110088884A (zh)

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