WO2018098650A1 - 集成电路封装结构及方法 - Google Patents

集成电路封装结构及方法 Download PDF

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Publication number
WO2018098650A1
WO2018098650A1 PCT/CN2016/107834 CN2016107834W WO2018098650A1 WO 2018098650 A1 WO2018098650 A1 WO 2018098650A1 CN 2016107834 W CN2016107834 W CN 2016107834W WO 2018098650 A1 WO2018098650 A1 WO 2018098650A1
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WIPO (PCT)
Prior art keywords
chip
fine
substrate
pin
additional
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PCT/CN2016/107834
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English (en)
French (fr)
Inventor
胡川
刘俊军
郭跃进
普莱克爱德华⋅鲁道夫
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深圳修远电子科技有限公司
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Application filed by 深圳修远电子科技有限公司 filed Critical 深圳修远电子科技有限公司
Priority to PCT/CN2016/107834 priority Critical patent/WO2018098650A1/zh
Priority to CN201680090828.8A priority patent/CN110024113B/zh
Priority to US16/464,896 priority patent/US11183458B2/en
Publication of WO2018098650A1 publication Critical patent/WO2018098650A1/zh

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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/115—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the invention belongs to the field of electronics, and in particular relates to an integrated circuit package structure and method.
  • a chip In a conventional integrated circuit system, a chip is separately packaged and then mounted on a circuit board together with other electronic components. Data communication between chips, chips, and other electronic components requires the passage of circuitry inside the board. There must be enough space between the chips, between the chip and other electronic components, and the geometry of the entire system is constrained and cannot be fully miniaturized, because each chip must be individually packaged and often need to be bonded or inverted.
  • the mounting method is connected to the circuit port of the substrate, and then connected to the circuit board.
  • the materials are used in a large amount, the process is complicated, and the production cost is high; and the use of a large number of materials with different characteristics is also easy to induce at the interface of each material. The problem of thermomechanical stress. Moreover, subject to the manufacturing process, the communication speed between the chips is limited, which seriously restricts the overall performance of the integrated circuit.
  • the present invention overcomes the deficiencies of the prior art and provides an integrated circuit package structure and method for improving data transmission bandwidth and speed between chips and improving system performance.
  • An integrated circuit package structure comprising: a substrate provided with a circuit layer and fine wiring; a chip, the chip is provided with fine pins, and chip pins; and the substrate is provided with at least two of the chips
  • the chip pins of the at least one chip are electrically connected to the circuit layer, the circuit layer is provided with an insulating patch, and the insulating patch is provided with a fine connection, and the fine pins and the chip of the chip are The fine wire electrical connection, at least two of the chips are directly electrically connected by the fine wire.
  • connection medium is disposed between the chip pin and the fine pin, the connection medium includes an insulating medium, and at least one fine conductive path distributed in the insulating medium, A fine pin is electrically connected to the fine pin through the fine conductive path.
  • the fine lines have a width of from 0.1 micron to 2 microns, or from 1 micron to 5 microns.
  • a heat sink is disposed on the chip.
  • an encapsulation layer is further included, the chip, the fine wiring, and the insulating patch are located between the encapsulation layer and the substrate, and the encapsulation layer is the chip and the The insulating patch is packaged with the substrate.
  • the substrate is a flexible circuit board, or the substrate comprises at least two layers of flexible circuit boards stacked.
  • the chip is located on a top surface of the substrate, the additional circuit layer is disposed on the bottom surface of the substrate or/and the substrate, and the additional circuit layer is provided with an additional pin.
  • the substrate is provided with an additional through hole, the additional through hole is mated with the additional pin, and the first opening of the additional through hole is butted with the chip pin, and the second opening of the additional through hole is an operation window
  • An additional conductive layer is disposed in the additional via, and the additional conductive layer electrically connects the chip pin and the additional pin.
  • the chip pins are at least two, the conductive layer is at least two corresponding to the chip pins, and the bottom surface of the substrate is provided with an external port, and the external port is at least One of the conductive layers is electrically connected.
  • the substrate is provided with a connection via
  • the connection via is docked with the circuit pin
  • the first opening of the connection via is docked with the chip pin
  • the connection The second opening of the through hole is an operation window
  • the connection through hole is provided with a conductive layer, and the conductive layer electrically connects the chip pin and the circuit pin.
  • the area occupied by the insulating patch is smaller than the area occupied by the circuit layer.
  • An integrated circuit packaging method includes: the substrate is provided with a circuit layer, an insulating patch is disposed on the substrate, a fine connection is formed on the insulating patch, and at least two of the chips are disposed on the substrate, The chip is provided with a fine pin and a chip pin, and the chip pin is electrically connected to the circuit layer, and the fine pin is electrically connected to the fine wire, so that at least two of the chips pass The fine lines are directly connected.
  • the circuit layer is provided with a circuit pin
  • the substrate is provided with a connection via
  • the connection via is docked with the circuit pin
  • the chip is placed on the top of the substrate a surface of the chip to be mated with the first opening of the connection via
  • a conductive layer is formed in the connection via through the second opening of the connection via, so that the conductive layer is
  • the chip pin is electrically connected to the circuit pin; or the circuit layer is provided with a circuit pin, and the chip is placed on a top surface of the substrate, so that the chip pin of the chip faces the substrate a connection via is formed on the substrate, the connection via is docked with the circuit pin, and a first opening of the connection via is docked with the chip pin, and the through hole is connected through the connection
  • the second opening forms a conductive layer in the connection via, such that the conductive layer electrically connects the chip pin to the circuit pin.
  • the method includes: providing the additional circuit layer in the bottom surface of the substrate or/and the substrate, the additional circuit layer is provided with an additional pin, and the substrate is provided with an additional through hole, An additional via is docked with the additional pin; a chip is placed on a top surface of the substrate such that a chip pin of the chip interfaces with a first opening of the additional via; a pass through the additional via Forming an additional conductive layer in the additional via, the additional conductive layer electrically connecting the chip pin to the additional pin; or the additional circuit layer is provided with an additional pin
  • the chip is placed on the top surface of the substrate such that the chip pins of the chip face the substrate, and additional via holes are formed on the substrate, so that the additional vias are docked with the additional pins, and a first opening of the additional via is docked with the chip pin, and a conductive layer is formed in the additional via through the second opening of the additional via, so that the conductive layer places the chip pin
  • the circuit pins are electrically connected.
  • the method further includes: providing an encapsulation layer on the substrate, the chip, the insulating patch, and the fine pin being located between the encapsulation layer and the substrate, the encapsulation layer The chip, the insulating patch, and the fine pin package package.
  • a conductor layer is disposed on the substrate, the insulating patch is disposed on the conductor layer, and a conductor film is disposed on the insulating patch, the conductor layer having a thickness greater than that of the conductor film a thickness, a resist is disposed on the conductor layer and the conductor film, the resist is provided with a wiring pattern, and the conductor layer is etched into the circuit layer according to the wiring pattern by a chemical etching method, The conductor film is etched into the fine wiring.
  • the circuit layer is disposed on the substrate, the insulating patch is disposed on the circuit layer, and a photoresist is disposed on the insulating patch, and the photoresist is formed on the photoresist
  • the wire slot grows the fine wire in the wire groove by crystal growth.
  • an insulating patch is formed on the carrier, the fine wiring is formed on the insulating patch, and the insulating patch is transferred to the substrate along with the fine wiring, and the fine wiring is Fixed to the substrate.
  • a connection medium is disposed between the chip and the fine pin, the connection medium includes an insulating medium, and at least one fine conductive particle distributed in the insulating medium; the chip pin The pitch between the fine pins is less than or equal to the height of the fine conductive particles, the chip is placed on the substrate, and one end of the fine conductive particles is electrically connected to the fine pin, and the other end is a fine wiring electrical connection; a spacing between the chip pins and the fine wiring is greater than a height of the fine conductive particles, and the chip pins and the fine wiring cannot be electrically connected through the conductive particles .
  • the integrated circuit package structure comprises: a substrate, the substrate is provided with a circuit layer and a fine connection; the chip, the chip is provided with fine pins and chip pins; the substrate is provided with at least two chips, at least one chip of the chip pins and The circuit layer is electrically connected, the circuit layer is provided with an insulating patch, the insulating patch is provided with a fine connection, the fine pin of the chip is electrically connected with the fine connection, and at least two chips are directly electrically connected through the fine connection.
  • the chip is electrically connected to the circuit layer, and the chip can communicate or exchange energy with other electronic components connected on the circuit layer, and the chip and the chip are directly connected by fine wires to reduce interference of other electronic components connected on the circuit layer.
  • the fine connection is small, and a larger number of connections can be formed in the same space, which can provide higher bandwidth data communication capability, and more data channels can be obtained between the chips, and the transmission speed is fast and the bandwidth is large.
  • the insulation patch separates the fine wiring from the circuit layer to prevent the circuit layer from interfering with the fine wiring. For the communication between two chips requiring high speed and bandwidth, the fine connection method is adopted to improve the transmission performance between the chips, and the communication or chip between the two chips that do not require high speed and wide bandwidth is required.
  • a circuit layer is formed on the substrate in a predetermined position by using an insulating patch.
  • Several processes, such as setting insulation patches and fine wiring, can be used for batch flow and reduce production costs.
  • connection medium is disposed between the fine pin and the fine connection.
  • the connection medium comprises an insulating medium and at least one fine conductive path distributed in the insulating medium, and the insulating medium separates the chip from the fine pin, only in fine detail The position of the pin and the fine wire will be placed to avoid interference, and the fine pin is electrically connected to the fine pin through the fine conductive path.
  • the form of the fine conductive channel includes, but is not limited to, providing conductive particles or solder bumps in the insulating medium to form a fine conductive path; the insulating medium is provided with fine conductive holes, and a conductive material layer is disposed in the fine conductive holes to form a fine conductive path; Conductive bumps are formed on the fine wires on the fine pins or /insulation patches, and the conductive bumps constitute fine conductive paths.
  • the width of the fine wiring is from 0.1 micrometer to 2 micrometers, or from 1 micrometer to 5 micrometers.
  • the width of the fine wire connection refers to the side length of the fine wire cross section on the insulating patch.
  • the width of the fine wire connection is smaller than the width of the wire of the circuit layer. The smaller the width of the fine wire connection, the achievable wire density. The larger the number of communication lines in the same size space, the better the data transmission speed and bandwidth.
  • a heat sink is arranged on the chip. Since the communication between the chips uses a high-bandwidth and high-speed fine connection, the chip has a high calculation rate and a large heat generation, and a heat sink is added to the chip to facilitate heat dissipation of the chip and ensure work performance.
  • the insulation patch may not exist (such as the material with high thermal conductivity), which will increase the difficulty of heat dissipation from the chip to the substrate, increase the thermal impedance, and add heat on the chip (one side of the back-phase substrate).
  • the device facilitates the heat dissipation of the chip from the back side, not only relying on the heat dissipation channel from the substrate, so that the chip can work normally at a higher computing speed.
  • This structural design improves the data communication bandwidth and speed between the chips, on the one hand, ensures that the chip can work normally at a higher computing speed, and can greatly improve the overall computing performance of the system.
  • the integrated circuit package structure further includes an encapsulation layer, the chip, the fine wiring, and the insulating patch are located between the encapsulation layer and the substrate, and the encapsulation layer encapsulates the chip and the insulating patch on the substrate.
  • the encapsulation layer can protect the chip, the insulation patch, and the fine connection without being damaged, and reduce the influence and interference of external environmental factors on the performance of the chip, and ensure the working performance of the chip.
  • the cured encapsulation layer also provides a flat surface and mechanical support properties, enabling the subsequent fabrication process to be performed on the substrate after flipping the system as a whole.
  • the substrate is a flexible circuit board, or the substrate comprises at least two layers of flexible circuit boards stacked.
  • Make The use of a multi-layer circuit board and its embedded multi-layer circuit layer can provide more wiring possibilities, improve the performance of the chip, use a flexible and thin circuit board, reduce the overall weight of the system, reduce the volume and thickness of the size, by adopting
  • the integrated circuit package structure and method of the present invention can make the system as a whole still have sufficient flexibility after package integration, and can be used for a wearable product.
  • the thickness of the fine wiring itself is small, and the insulating patch can be insulated as long as it satisfies the fine wiring and the circuit layer, and does not require a very thick thickness, so that the flexible circuit board is still thin after the integrated chip Flexible.
  • the thickness of the fine wiring means that the cross section of the fine wiring is perpendicular to the side length of the insulating patch, and the thickness of the insulating patch means that the cross section of the insulating patch is perpendicular to the side length of the substrate.
  • the chip is located on the top surface of the substrate, and an additional circuit layer is disposed on the bottom surface of the substrate or/and the substrate.
  • the additional circuit layer is provided with additional pins
  • the substrate is provided with additional through holes
  • the additional through holes are connected with the additional pins
  • the additional contacts are provided.
  • the first opening of the hole is docked with the chip pin
  • the second opening of the additional via is an operation window
  • the additional via is provided with an additional conductive layer
  • the additional conductive layer electrically connects the chip pin and the additional pin.
  • the additional circuit layer has an additional pin, and an additional circuit layer can be formed on the substrate in advance, or an additional circuit layer can be formed on the substrate when the integrated circuit is packaged, and the additional pin can be a connection portion directly led out by the additional circuit layer. It may also be an extension pin electrically connected to the connection portion, as long as it can be electrically connected to an additional circuit layer by an additional pin.
  • the chip is placed on the substrate, and the chip may be fixed on the substrate or may not be fixed.
  • the chip is disposed opposite to the substrate, and the chip has a chip pin facing one side of the substrate, and the chip pins of the chip include, but are not limited to, a connection portion drawn inside the chip, and an extension pin electrically connected to the connection portion, as long as the chip pin is passed through the chip.
  • the additional via is docked with the chip pin, and the additional pin is at least partially located near the first opening of the additional via or deep into the additional via, so that the additional conductive layer can be electrically connected to the chip pin; additional pins and additional The through hole is butted, the additional pin is at least partially located near the first opening of the additional through hole, or The vicinity of the second opening, or the vicinity of the inner wall of the additional via, allows the additional conductive layer to be electrically connected to the additional pins;
  • the chip can be a chip or electronic component (including but not limited to resistors, capacitors) or other electronic devices (including but not limited to antennas ).
  • the chip may be attached to the substrate by additional vias, additional conductive layers, or the chip may be secured to the substrate by other means including, but not limited to, pasting, molding plastic encapsulation.
  • the cost of the integrated circuit package can be reduced, and the packaging time can be saved.
  • multiple chips can be simultaneously mounted on a large panel with a large area, and the batch processing on the large panel further reduces the cost and saves the packaging time.
  • the thickness of the whole system of the substrate and the chip can be reduced, and even no gap is required between the substrate and the chip (in principle, no gap is reserved, but other materials can be disposed on the substrate and the chip as needed); conductive additional through holes
  • the fabrication process can choose to use a process that does not require heat welding, thus avoiding damage to the mechanism and performance of ultra-thin chips and flexible circuit boards by various thermo-mechanical stress distributions during high-temperature thermal cycling. This is very helpful for packaging processes that use ultra-thin, flexible boards.
  • a wire is used to realize electrical connection between the chip and the circuit layer on the substrate, and the wires are to be avoided from each other, so that the space is large, and the present invention opens an additional pass on the substrate.
  • the hole way realizes the electrical connection between the chip and the additional circuit layer, and the additional conductive layer is disposed in the additional through hole, which does not occupy extra space, and can reduce the overall volume after the package, in particular, the ultra-thin circuit board can be kept thin and thin. The characteristics of the flexible circuit board, it can maintain its flexibility.
  • the method includes the following two methods:
  • an additional circuit layer is provided on the bottom surface of the substrate or/and the substrate, the additional circuit layer is provided with additional pins, the substrate is provided with additional through holes, and the additional through holes are butted with the additional pins; the chip is placed on the top surface of the substrate, Interfacing the chip pins of the chip with the first opening of the additional via; making an additional conductive layer in the additional via through the second opening of the additional via, causing the additional conductive layer to electrically connect the chip pins to the additional pins;
  • the additional circuit layer is provided with additional pins
  • the chip is placed on the top surface of the substrate, the chip pins of the chip are directed toward the substrate, and additional via holes are formed on the substrate, so that the additional via holes are connected with the additional pins
  • the first opening of the additional via is docked with the chip pin, and the conductive layer is formed in the additional via through the second opening of the additional via, so that the conductive layer electrically connects the chip pin to the circuit pin.
  • the chip pins are at least two, and the conductive layer is at least two corresponding to the chip pins, and the substrate is The bottom surface is provided with an external port, and the external port is electrically connected to at least one conductive layer.
  • the external port can be connected to another electronic component to extend the function of the entire integrated circuit. It can also be used to connect the power supply, and the power supply is directly supplied by the power supply.
  • the substrate is provided with a connection through hole, the connection through hole is docked with the circuit pin, and the first opening of the connection through hole is docked with the chip pin, the second opening of the connection through hole is an operation window, and the connection through hole is provided with conductive
  • the layer, the conductive layer electrically connects the chip pins and the circuit pins.
  • the circuit layer has a circuit pin, and the circuit layer can be fabricated on the substrate in advance, or the circuit layer can be formed on the substrate when the integrated circuit is packaged.
  • the circuit pin can be a connection portion directly led out by the circuit layer, or can be The extension pin electrically connected to the connection portion can be electrically connected to the circuit layer through a circuit pin.
  • the chip is placed on the substrate, and the chip may be fixed on the substrate or may not be fixed.
  • the chip is disposed opposite to the substrate, and the chip has a chip pin facing one side of the substrate, and the chip pins of the chip include, but are not limited to, a connection portion drawn inside the chip, and an extension pin electrically connected to the connection portion, as long as the chip pin is passed through the chip. Can be electrically connected to the chip.
  • connection via hole on the substrate, the chip pin is docked with the first opening of the connection via hole, and a conductive layer is formed in the connection via hole through the second opening of the connection via hole.
  • the conductive layer electrically connects the chip pin to the circuit pin; the chip pin is located on a top surface of the substrate, and the second opening of the through hole is connected to electrically connect the chip to the circuit layer from the bottom surface of the substrate, thereby avoiding The chip blocks the chip pins;
  • connection via is docked with the chip pin, and the circuit pin is at least partially located near the first opening of the connection via or deep into the via, so that the conductive layer can be electrically connected to the chip pin;
  • the circuit pin and the connection are The hole is butted, the circuit pin is at least partially located near the first opening of the connection through hole, or near the second opening, or in the vicinity of the inner wall of the connection through hole, so that the conductive layer can be electrically connected to the circuit pin;
  • the chip can be a chip or an electronic component (including but not limited to resistors, capacitors) or other electronic devices (including but not limited to antennas).
  • the chip may be fixed to the substrate through a connection via, a conductive layer, or the chip may be fixed to the substrate by other means including, but not limited to, pasting, molding a plastic package.
  • the cost of the integrated circuit package can be reduced, and the packaging time can be saved. Further, multiple chips can be simultaneously mounted on a large panel with a large area, and the batch processing on the large panel further reduces the cost and saves the packaging time. Also, reduce the overall thickness of the substrate and chip, even the substrate and chip There is no need to reserve gaps (in principle, no gaps need to be reserved, but other materials can be placed on the substrate and chip as needed); no heating and soldering steps are required, especially for ultra-thin substrates and flexible circuit boards. The substrate warps and degrades performance at high temperatures.
  • the conventional electronic package uses a wire to realize electrical connection between the chip and the substrate circuit layer, and the wire occupies a large space.
  • the present invention realizes electrical connection between the chip and the circuit layer by opening a connection via hole on the substrate, and the conductive layer is provided.
  • connection through-hole it does not occupy extra space, and the overall volume can be small after packaging.
  • the thin and light characteristics can be well maintained, and the flexible circuit board can maintain its flexibility well.
  • the method includes the following two methods:
  • the circuit layer is provided with a circuit pin, the substrate is provided with a connection through hole, and the connection through hole is connected with the circuit pin; the chip is placed on the top surface of the substrate, so that the chip pin of the chip and the first opening of the connection through hole are Docking; forming a conductive layer in the connection via hole through the second opening connecting the through holes, so that the conductive layer electrically connects the chip pins with the circuit pins;
  • the circuit layer is provided with circuit pins
  • the chip is placed on the top surface of the substrate, so that the chip pins of the chip face the substrate, and the connection through holes are formed on the substrate, so that the connection through holes are connected with the circuit pins
  • the first opening of the connection via is docked with the chip pin, and a conductive layer is formed in the connection via through the second opening of the connection via, so that the conductive layer electrically connects the chip pin to the circuit pin.
  • the area occupied by the insulation patch is smaller than the area occupied by the circuit layer.
  • the insulating patch and the fine wiring thereon constitute a fine connection area, and one or two fine connection areas may be disposed between the two chips as needed, or one chip may pass two or more fine connection areas simultaneously It is electrically connected to two or more chips; and the fine connection area does not need to be modified to the original circuit layer, and the fine connection area is flexible and can be set as needed to reduce the cost.
  • the integrated circuit packaging method further comprises: providing a conductor layer on the substrate, providing an insulating patch on the conductor layer, and providing a conductor film on the insulating patch, the thickness of the conductor layer being greater than the thickness of the conductor film, on the conductor layer and the conductor film A resist is provided, and the resist is provided with a wiring pattern, and the conductive layer is etched into a circuit layer according to a wiring pattern, and the conductor film is etched into a fine wiring by a chemical etching method.
  • the thickness of the conductor film is equivalent to the thickness of the fine wiring
  • the thickness of the conductor layer is equivalent to the thickness of the circuit layer, for example, when the thickness of the fine wiring is smaller than the thickness of the circuit layer, the thickness of the conductor film is smaller than the thickness of the conductor layer.
  • the circuit layer is disposed on the substrate, the insulating patch is disposed on the circuit layer, a photoresist is disposed on the insulating patch, and a connection groove is formed in the photoresist, and a crystal is used.
  • a conductor film is formed in the wiring trench and on the surface of the photoresist, and the photoresist is stripped to form the fine wiring in the wiring trench.
  • the crystal growth method can be used to obtain finer fine wiring and obtain more connection points, further improving the chip function.
  • the way of crystal growth refers to the manner in which the conductive material is attached to the wire groove to form a fine wire, including but not limited to: electroplating, sputtering, and evaporation.
  • the method of separately manufacturing the insulating patch and then transferring and pasting it to the substrate does not require modification of the original circuit layer, and is convenient for upgrading and upgrading the old integrated circuit.
  • the fine wire may be directly fixed to the substrate; or the fine wire may be fixed to the insulating patch, the insulating patch may be fixed to the substrate, and the fine wire may be fixed to the substrate through the insulating patch.
  • a connection medium is disposed between the chip and the fine pin, the connection medium includes an insulating medium, and at least one fine conductive particle distributed in the insulating medium; a spacing between the fine wire and the fine pin is less than or equal to the fine conductive particle.
  • the height of the chip when the chip is placed on the substrate, one end of the fine conductive particles is electrically connected to the fine pin, and the other end is electrically connected to the fine wire.
  • the fine pins and the fine wires are electrically connected through the fine conductive particles; the chip pins are connected with the fine wires.
  • the spacing between the lines is greater than the height of the fine conductive particles, and the chip leads and the fine wiring cannot be electrically connected by the conductive particles.
  • the insulating medium When encapsulating, the insulating medium is placed between the chip and the fine pin, and the chip is extruded toward the insulating patch.
  • the fine conductive particles are squeezed, one end is electrically connected to the fine pins, and the other end is electrically connected to the fine wires.
  • the fine pins and the fine wires are electrically connected; the distance between the chip pins and the fine wires is larger than the height of the fine conductive particles, and the fine conductive particles between the chip pins and the fine wires cannot simultaneously contact the chip pins Fine wiring, so fine conductive particles can not electrically connect the chip pins and fine wiring.
  • connection medium between the fine pin and the fine wire. It also includes the following cases: except for the area where the fine pin is located, the connection medium, chip pin and circuit layer are also provided between other parts of the chip and the fine wire.
  • the spacing between the electrodes is greater than the height of the fine conductive particles, and the fine conductive particles between the chip pins and the circuit layer cannot simultaneously contact the chip pins and the fine wires, so the fine conductive particles cannot electrically connect the chip pins and the fine wires. .
  • connection medium has a pasting property
  • the chip can be pasted on the substrate.
  • the insulating medium is disposed between the chip and the fine pin, and the chip is squeezed to the insulating patch to reach a preset position, and the chip is pasted on the substrate.
  • the electrical connection of the fine pin and the fine wire connection is simple in production process and high in efficiency.
  • FIG. 1 is a first schematic diagram of an integrated circuit package structure and method according to an embodiment of the present invention
  • FIG. 2 is a second schematic diagram of an integrated circuit package structure and method according to an embodiment of the present invention.
  • FIG. 3 is a third schematic diagram of an integrated circuit package structure and method according to an embodiment of the present invention.
  • FIG. 4 is a fourth schematic diagram of an integrated circuit package structure and method according to an embodiment of the present invention.
  • FIG. 5 is a fifth schematic diagram of an integrated circuit package structure and method according to an embodiment of the present invention.
  • FIG. 6 is a first schematic diagram of an integrated circuit package structure according to an embodiment of the present invention.
  • FIG. 7 is a second schematic diagram of an integrated circuit package structure according to an embodiment of the present invention.
  • the integrated circuit package structure includes: a substrate 100 provided with a circuit layer 110 and a fine connection 210; a chip 400 having a fine pin 420 and a chip lead
  • the substrate 100 is provided with at least two chips 400.
  • the chip pins 410 of the at least one chip 400 are electrically connected to the circuit layer 110.
  • the circuit layer 110 is provided with an insulating patch 200, and the insulating patch 200 is provided with a fine connection 210.
  • the fine pins 420 of the chip 400 are electrically connected to the fine wiring 210, and at least two chips 400 are directly electrically connected through the fine wiring 210.
  • the chip 400 is electrically connected to the circuit layer 110.
  • the chip 400 can communicate or exchange energy with other electronic components connected to the circuit layer 110.
  • the chip 400 and the chip 400 are directly connected through the fine connection 210, and are not interfered by the circuit layer 110. It is not interfered by other electronic components connected on the circuit layer 110, and the fine wiring 210 is small, and more data transmission channels can be obtained between the chips 400, and the transmission speed is fast and the bandwidth is large.
  • the insulating patch 200 insulates the fine wiring 210 from the circuit layer 110 to prevent the circuit layer 110 from interfering with the fine wiring 210.
  • the method of fine connection 210 is adopted to improve the transmission performance between the chips 400, and between the two chips 400 which do not require high speed and bandwidth.
  • Communication can be connected through the circuit layer 110 to reduce the manufacturing cost.
  • the circuit layer 110 can be uniformly formed, and the insulating patch 200 and the fine wiring 210 can be uniformly disposed at predetermined positions, and the batch flow can be performed to reduce the production cost.
  • the fine pin 420 is disposed near the edge of the chip 400, and the insulating patch 200 and the fine wiring 210 are spanned between the two chips 400.
  • the area occupied by the insulating patch 200 is smaller than the area occupied by the circuit layer 110.
  • the insulating patch 200 and the fine wiring 210 thereon constitute a fine connection region, and one or two fine connection regions may be disposed between the two chips 400 as needed, or one chip 400 may pass two or more
  • the fine connection area is electrically connected to the other two or more chips 400 at the same time; and the fine connection area is not required to be changed to the original circuit layer 110. Dynamic and fine connection areas are flexible and can be set on demand to reduce costs.
  • the area occupied by the insulating patch 200 can refer to the area occupied by the insulating patch 200 on the substrate 100 and the area occupied by the circuit layer 110 on the substrate 100 when viewed from above in the top view.
  • the width of the fine wiring 210 refers to the side length of the cross section of the fine wiring 210 on the insulating patch 200.
  • the width of the fine wiring 210 is smaller than the width of the wiring of the circuit layer 110, and the width of the fine wiring 210 is smaller. The more connection points that can be obtained in the same space, the better the data transmission speed and bandwidth.
  • the width of the fine wiring 210 is 0.1 micrometer to 2 micrometers, or 1 micrometer to 5 micrometers, and can be selected as needed.
  • the width of the fine wiring 210 may be selected to be 0.1 ⁇ m, 0.2 ⁇ m, 0.5 ⁇ m, 0.7 ⁇ m, 1 ⁇ m, 1.2 ⁇ m, 1.5 ⁇ m, 1.7 ⁇ m, 2 ⁇ m, 2.5 ⁇ m, 3 ⁇ m, 3.5 ⁇ m, 4 ⁇ m. , 4.5 microns, or 5 microns.
  • connection medium is disposed between the chip pin 410 and the fine pin 420.
  • the connection medium includes an insulating medium 620 and at least one fine conductive path distributed in the insulating medium 620.
  • the insulating medium 620 causes the chip 400 to
  • the fine pins 420 are insulated from each other to avoid interference, and the fine pins 420 are electrically connected to the fine pins 420 through the fine conductive paths.
  • the form of the fine conductive path includes, but is not limited to, providing conductive particles or solder bumps in the insulating medium 620 to form a fine conductive path; the insulating medium 620 is provided with a fine conductive hole, and a conductive material layer is disposed on the inner wall of the fine conductive hole to form a fine conductive path
  • conductive material layer is disposed on the inner wall of the fine conductive hole to form a fine conductive path
  • through-silicon vias conductive bumps are provided on the fine leads 420 or/and the fine wiring 210, and the conductive, conductive bumps constitute fine conductive vias.
  • the integrated circuit package structure further includes an encapsulation layer, the package layer is not shown in the figure, the chip 400, the fine connection 210, and the insulation patch 200 are located between the encapsulation layer and the substrate 100, and the encapsulation layer encapsulates the chip 400 and the insulation patch 200. With the substrate 100.
  • the encapsulation layer can protect the chip 400, the insulation patch 200, and the fine connection 210 from being damaged, reduce the influence and interference of external environmental factors on the performance of the chip, and ensure the performance of the chip 400.
  • a heat sink is disposed on the chip 400.
  • the use of an insulating patch may increase the difficulty of heat dissipation of the chip 400 toward the substrate, the thermal impedance increases, and the communication between the chips 400 uses a high-speed, high-speed fine connection, and the chip 400 has a high calculation rate and heat generation.
  • the heat sink is installed on the 400 (the side facing away from the substrate), which is beneficial to the heat dissipation of the chip 400 from the heat sink of the back surface, not only relying on the substrate The heat dissipation channel in the 100 direction, so that the chip 400 can work normally at a higher calculation speed.
  • the heat sink is also encapsulated on the substrate 100 by an encapsulation layer, and the top surface of the heat sink may be exposed to heat from the package layer or may not be exposed.
  • the substrate 100 is provided with a connection via 130, the connection via 130 is docked with the circuit pin, and the first opening of the connection via 130 is docked with the chip pin 410, and the second opening of the connection via 130 is In the operation window, a conductive layer 500 is disposed in the connection via 130, and the conductive layer 500 electrically connects the chip pin 410 and the circuit pin.
  • the circuit layer 110 has a circuit pin, and the circuit layer 110 can be formed on the substrate 100 in advance.
  • the circuit layer 110 can be formed on the substrate 100 during the integrated circuit package.
  • the circuit pin can be a connection portion directly led out by the circuit layer 110.
  • the chip 400 is placed on the substrate 100, and the chip 400 may be fixed to the substrate 100 or may not be fixed.
  • the chip 400 is disposed opposite to the substrate 100.
  • the chip 400 has a chip pin 410 facing the substrate 100.
  • the chip pin 410 of the chip 400 includes, but is not limited to, a connection portion drawn inside the chip 400 and an extension pin electrically connected to the connection portion, as long as Both the chip pins 410 can be electrically connected to the chip 400.
  • a connection via 130 is formed on the substrate 100, the chip lead 410 is docked with the first opening of the connection via 130, and a conductive layer 500 is formed in the connection via 130 through the second opening of the connection via 130.
  • the conductive layer 500 The chip pin 410 is electrically connected to the circuit pin; the chip pin 410 is located on the top surface of the substrate 100.
  • the chip pin 410 is blocked; wherein the connection via 130 is docked with the chip pin 410, and the circuit pin is at least partially located near the first opening of the connection via 130 or deep into the via 130, so that the conductive layer 500 can Electrically connected to the chip pin 410; the circuit pin is connected to the connection via 130, and the circuit pin is at least partially located near the first opening of the connection via 130, or near the second opening, or near the inner wall of the connection via 130, such that Conductive layer 500 can be electrically coupled to circuit pins; chip 400 can be chip 400 or electronic components (including but not limited to resistors, capacitors) or other electronic devices (including but not limited to antennas). The chip 400 can be fixed to the substrate 100 through the connection via 130 and the conductive layer 500.
  • the chip 400 is secured to the substrate 100 by other means including, but not limited to, pasting, molding a plastic encapsulation. In this way, the cost of the integrated circuit package can be reduced, and the packaging time can be saved. Further, the plurality of chips 400 can be simultaneously mounted on a large panel of a large area, and the batch processing on the large panel further reduces the cost and saves the packaging time.
  • connection via 130 can be fabricated using a process that does not require heat welding, thereby avoiding damage to the mechanism and performance of the ultra-thin chip and the flexible circuit board by various thermo-mechanical stress distributions during high-temperature thermal cycling. This is very helpful for packaging processes that use ultra-thin, flexible boards.
  • the wires are used to realize the electrical connection between the chip 400 and the circuit on the substrate 100, and the wires are to be avoided from each other, so that the space is large, and the present invention is opened on the substrate 100.
  • the electrical connection between the chip and the additional circuit layer 120 is realized by connecting the through hole 130.
  • the conductive layer 500 is disposed in the connection through hole 130 without occupying extra space, and can reduce the overall volume after the package, in particular, for the ultra-thin circuit board. Very good to maintain the thin and light characteristics, for the flexible circuit board, it can maintain its flexibility.
  • the method includes the following two methods:
  • the circuit layer 110 is provided with a circuit pin
  • the substrate 100 is provided with a connection via 130
  • the connection via 130 is docked with the circuit pin
  • the chip 400 is placed on the top surface of the substrate 100, so that the chip pin 410 of the chip 400 Interfacing with the first opening of the connection via 130; forming a conductive layer 500 in the connection via 130 through the second opening of the connection via 130, so that the conductive layer 500 electrically connects the chip pin 410 to the circuit pin;
  • the circuit layer 110 is provided with circuit pins
  • the chip 400 is placed on the top surface of the substrate 100
  • the chip pins 410 of the chip 400 are directed toward the substrate 100
  • the connection vias 130 are formed on the substrate 100 to make the connection
  • the hole 130 is docked with the circuit pin
  • the first opening of the connection via 130 is docked with the chip pin 410.
  • the conductive layer 500 is formed in the connection via 130 through the second opening of the connection via 130, so that the conductive layer 500 turns the chip.
  • Pin 410 is electrically coupled to the circuit pins.
  • connection via 130 is also an additional via, and a separate circuit layer 120 is disposed on the bottom surface of the substrate 100 and the substrate 100, and the additional circuit layer 120 is provided with an additional pin.
  • the through hole (connection via 130) is butted to the additional pin, and the first opening of the additional via (connection via 130) is butted to the chip pin 410, and the second opening of the additional via (connection via 130) is
  • an additional conductive layer 500 is disposed in the additional via (connection via 130), and the additional conductive layer 500 electrically connects the chip pin 410 and the additional pin.
  • an external port 140 is disposed on a bottom surface of the substrate 100 to electrically connect the external port 140 to at least one of the conductive layers 500.
  • the external port 140 can be connected to another electronic component to expand the function of the entire integrated circuit, and can also be used to connect the power supply, and the power supply is directly supplied to the chip 400 by the power supply.
  • the substrate 100 may be a normal circuit board or a flexible circuit board, or the substrate 100 may include at least two layers of flexible circuit boards.
  • the use of a multi-layer circuit board and its embedded multi-layer circuit can provide more wiring possibilities and improve the performance of the chip 400; using a flexible and thin circuit board, reducing the overall weight of the system, reducing the size and thickness of the size, With proper system design and choice of encapsulation material, the system as a whole can still be flexible enough after package integration to be used in wearable products.
  • the thickness of the fine wiring 210 itself is small, and the insulating patch 200 can satisfy the insulation of the fine wiring 210 and other regions of the substrate 100, and does not require a thick thickness, which contributes to The system as a whole remains flexible and thin.
  • the thickness of the fine wiring 210 means that the cross section of the fine wiring 210 is perpendicular to the side length of the insulating patch 200, and the thickness of the insulating patch 200 means that the cross section of the insulating patch 200 is perpendicular to the side length of the substrate 100.
  • the thickness of the fine wiring 210 means that the cross section of the fine wiring 210 is perpendicular to the side length of the insulating patch 200, and the thickness of the insulating patch 200 means that the cross section of the insulating patch 200 is perpendicular to the side length of the substrate 100.
  • the integrated circuit packaging method mainly includes: the substrate 100 is pre-equipped with the circuit layer 110, the insulating patch 200 is disposed on the substrate 100, the fine wiring 210 is formed on the insulating patch 200, and at least two chips 400 are disposed on the substrate 100.
  • the chip 400 is provided with a fine pin 420 and a chip pin 410.
  • the chip pin 410 is electrically connected to the circuit layer 110, and the fine pin 420 is electrically connected to the fine wire 210, so that at least two chips 400 pass through the fine connection. Line 210 is directly connected.
  • the method further includes the steps of: the circuit layer 110 is pre-arranged with a circuit pin, the substrate 100 is pre-set with a connection via 130, and the connection via 130 is docked with the circuit pin; the chip 400 is placed On the top surface of the substrate 100, the chip pins 410 and the connection vias 130 of the chip 400 are The first opening is butted; the conductive layer 500 is formed in the connection via 130 through the second opening of the connection via 130, so that the conductive layer 500 electrically connects the chip pin 410 and the circuit pin; or the circuit layer 110 is pre-configured The circuit pins are placed on the top surface of the substrate 100, the chip pins 410 of the chip 400 are directed toward the substrate 100, and the connection vias 130 are formed on the substrate 100, so that the connection vias 130 are connected to the circuit pins and connected. The first opening of the via 130 is in contact with the chip lead 410. The conductive layer 500 is formed in the connection via 130 through the second opening of the connection via 130, so
  • the method further includes the steps of: providing an additional circuit layer 120 on the bottom surface of the substrate 100 or/and the substrate 100, the additional circuit layer 120 is pre-arranged with an additional pin, and the substrate 100 is pre-configured with an additional pass.
  • the additional through hole is docked with the additional pin; the chip 400 is placed on the top surface of the substrate 100 such that the chip pin 410 of the chip 400 is docked with the first opening of the additional through hole; the second opening through the additional through hole is attached
  • An additional conductive layer 500 is formed in the via hole, so that the additional conductive layer 500 electrically connects the chip pin 410 to the additional pin; or the additional circuit layer 120 is pre-positioned with an additional pin to place the chip 400 on the top surface of the substrate 100.
  • the chip pins 410 of the chip 400 are oriented toward the substrate 100, additional via holes are formed on the substrate 100, the additional via holes are mated with the additional pins, and the first openings of the additional via holes are docked with the chip pins 410 through the additional via holes.
  • the second opening creates a conductive layer 500 in the additional via, causing the conductive layer 500 to electrically connect the chip leads 410 to the circuit pins.
  • the integrated circuit packaging method further includes packaging the chip 400: an encapsulation layer is disposed on the substrate 100, the chip 400, the insulating patch 200, and the fine wiring 210 are located between the encapsulation layer and the substrate 100, the encapsulation layer is the chip 400, the insulating patch 200, and The fine connection 210 wraps the package. After the package, the whole system of the substrate 100, the chip 400, the encapsulation layer, the insulating patch 200, the fine connection 210, and the like is cut, and is cut into a plurality of small system units according to preset functions, sizes, and the like, so as to be unified on the substrate. The chip 400 is mounted on the 100 and packaged, and then cut into a suitable size system unit, which can greatly improve production efficiency and reduce cost.
  • the circuit layer 110 is not preset on the substrate 100, and the circuit layer 110 is simultaneously formed when the fine wiring 210 is formed.
  • the manufacturing method is as follows: the conductor layer 101 and the additional conductor layer are disposed on the substrate 100. 102.
  • An insulating patch 200 is disposed on the conductor layer 101, and a conductor film 201 is disposed on the insulating patch 200.
  • the thickness of the conductor layer 101 is much larger than the thickness of the conductor film 201, and is disposed on the conductor layer 101, the additional conductor layer 102, and the conductor film 201.
  • the resist 300 is provided with a wiring pattern in the resist 300, and the conductor layer 101 is etched into the circuit layer 110 in a wiring pattern by a chemical etching method, and the conductor film 201 is etched into the fine wiring 210. After the resist 300 is uniformly disposed on the conductor layer 101, the additional conductor layer 102, and the conductor film 201, chemical etching is uniformly performed, and the circuit layer 110, the additional circuit layer 120, and the fine wiring 210 are uniformly formed in accordance with the wiring pattern.
  • the steps are saved, the efficiency is improved, the production cost is reduced, and all the circuit layers 110, the additional conductor layer 102, and the conductor film 201 on the multi-substrate 100 can be simultaneously performed, which is advantageous for mass production and further reduces the cost.
  • the thickness of the conductor film 201 is equivalent to the thickness of the fine wiring 210
  • the thickness of the conductor layer 101 is equivalent to the thickness of the circuit layer 110, for example, when the thickness of the fine wiring 210 is much smaller than the thickness of the circuit layer 110, the conductor film 201 The thickness needs to be much smaller than the thickness of the conductor layer 101.
  • the insulating patch 200 and the fine wiring 210 are prepared by presetting a circuit layer 110 on the substrate 100, providing an insulating patch 200 on the circuit layer 110, and providing a photoresist on the insulating patch 200. a wire slot, a conductor film is grown in the wire groove and on the surface of the photoresist, and the photoresist is stripped to form the fine wire 210 in the wire groove.
  • the insulating patch 200 and the fine wiring 210 are prepared by fabricating a peelable layer and an insulating patch 200 on the carrier, forming a fine wiring 210 on the insulating patch 200, and transferring the insulating patch 200 together with the fine wiring 210 to the substrate 100.
  • the fine wiring 210 is fixed to the substrate 100.
  • insulation can be added Ding 200, the fine wire 210 is flipped over to another carrier, and the other carrier will flip the insulating patch 200 and the fine wire 210 to the substrate again, so that the fine wire 210 faces upward, and the fine wire 210 and the lower portion thereof
  • the insulating patches 200 are fixed to the substrate 100 together.
  • the method of electrically connecting the fine pins 420 and the fine wires 210 is as follows: a connection medium is disposed between the chip 400 and the fine pins 420 , and the connection medium includes an insulating medium 620 and is distributed on the insulating medium 620 .
  • At least one fine conductive particle 610 the fine conductive particles 610 are insulated from each other by the insulating medium 620, and a pitch between the chip pin 410 and the fine pin 420 is less than or equal to the height of the fine conductive particles 610, the chip 400
  • the spacing between the upper fine pins 420 and the fine wiring 210 on the insulating patch 200 is small, the fine conductive particles 610 are distributed at a high density, the chip 400 is placed on the substrate 100, and one end of the fine conductive particles 610 is electrically connected to the fine pins 420.
  • the other end is electrically connected to the fine connection 210 to form at least one conductive path formed by the fine conductive particles 610; the distance between the chip pin 410 and the circuit layer 110 is greater than the height of the fine conductive particles 610, and the chip pin 410
  • the spacing between the circuit layer 110 and the circuit layer 110 is large, the distribution density of the fine conductive particles 610 is low, and the chip pins 410 and the circuit layer 110 cannot be electrically connected through the conductive particles, and cannot be formed.
  • the conductive via formed by the fine conductive particles 610 maintains electrical isolation between the chip leads 410 and the circuit layer 110.
  • the insulating medium 620 is disposed between the chip 400 and the fine pin 420, and the chip 400 is extruded toward the insulating patch 200 to a preset position, because the spacing between the chip pin 410 and the fine pin 420 is less than or equal to the fine conductive particles 610.
  • the height, the fine conductive particles 610 are squeezed, one end is electrically connected to the fine pin 420, and the other end is electrically connected to the fine wire 210, thereby electrically connecting the fine pin 420 and the fine wire 210; the chip pin 410 and the circuit
  • the spacing between the layers 110 is greater than the height of the fine conductive particles 610, and the fine conductive particles 610 between the chip leads 410 and the circuit layer 110 cannot simultaneously contact the chip pins 410 and the fine wiring 210, so the fine conductive particles 610 cannot The chip pins 410 and the fine wires 210 are electrically connected. In this connection manner, the process of placing the chip 400 on the insulating patch 200 realizes the electrical connection of the fine pin 420 and the fine wire 210, and the process is simple and efficient.

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Abstract

一种集成电路封装结构及方法，其中集成电路封装结构包括：基板（100），所述基板（100）设有电路层（110）以及精细连线（210）；芯片（400），所述芯片（400）设有精细引脚（420）、以及芯片引脚（410）；所述基板（100）设有至少两个所述芯片（400），至少一个所述芯片（400）的所述芯片引脚（410）与所述电路层（110）电连接，所述电路层（110）上设有绝缘补丁（200），所述绝缘补丁（200）上设有精细连线（210），所述芯片（400）的精细引脚（420）与所述精细连线（210）电连接、至少两个所述芯片（400）通过所述精细连线（210）直接电连接。传输速度快、提高芯片性能。

Description

集成电路封装结构及方法 技术领域
本发明属于电子领域，具体涉及一种集成电路封装结构及方法。
背景技术
传统的集成电路系统，需要将芯片单独封装后，再与其它电子元件等一起安装于电路板上。芯片之间、芯片和其它电子元件之间的数据通讯需要通过电路板内部的电路。芯片之间、芯片和其它电子元件之间必须留有足够空间，整个系统的几何尺寸也因而受到约束，不能充分小型化，因为每个芯片都要单独封装以后，经常需要通过以键合或者倒装的方式连接到基板的电路端口上，再接入到电路板上，各种材料使用量大，工艺复杂，生产成本高；而且使用大量特性各异的材料，也容易在各材料界面诱发多种热机械应力的问题。并且，受制于制作工艺，芯片之间的通讯速度受限，严重制约集成电路的整体性能。
发明内容
基于此，本发明在于克服现有技术的缺陷，提供一种集成电路封装结构及方法，以提高芯片间数据传输带宽和速度、提高系统性能。
其技术方案如下：
一种集成电路封装结构，包括：基板，所述基板设有电路层以及精细连线；芯片，所述芯片设有精细引脚、以及芯片引脚；所述基板设有至少两个所述芯片，至少一个所述芯片的所述芯片引脚与所述电路层电连接，所述电路层上设有绝缘补丁，所述绝缘补丁上设有精细连线，所述芯片的精细引脚与所述精细连线电连接、至少两个所述芯片通过所述精细连线直接电连接。
在其中一个实施例中，所述芯片引脚与所述精细引脚之间设有连接介质，所述连接介质包括绝缘介质、以及分布于所述绝缘介质内的至少一个精细导电通道，所述精细引脚通过所述精细导电通道与所述精细引脚电连接。
在其中一个实施例中，所述精细连线的宽度为0.1微米至2微米、或1微米至5微米。
在其中一个实施例中，在所述芯片的上设有散热装置。
在其中一个实施例中，还包括有封装层，所述芯片、所述精细连线、以及所述绝缘补丁位于所述封装层与所述基板之间，所述封装层将所述芯片以及所述绝缘补丁封装与所述基板。
在其中一个实施例中，所述基板为柔性电路板，或所述基板包括至少两层层叠设置的柔性电路板。
在其中一个实施例中，所述芯片位于所述基板的顶面，所述基板底面或/和所述基板内设有所述附加电路层，所述附加电路层设有附加引脚，所述基板设有附加通孔，所述附加通孔与所述附加引脚对接、并且所述附加通孔的第一开口与所述芯片引脚对接，所述附加通孔的第二开口为操作窗口，所述附加通孔内设有附加导电层，所述附加导电层将所述芯片引脚和所述附加引脚电连接。
在其中一个实施例中，所述芯片引脚为至少两个，所述导电层为与所述芯片引脚相应的至少两个，所述基板的底面设有外接端口，所述外接端口与至少一个所述导电层电连接。
在其中一个实施例中，所述基板设有连接通孔，所述连接通孔与所述电路引脚对接、并且所述连接通孔的第一开口与所述芯片引脚对接，所述连接通孔的第二开口为操作窗口，所述连接通孔内设有导电层，所述导电层将所述芯片引脚和所述电路引脚电连接。
在其中一个实施例中，所述绝缘补丁所占区域的面积小于所述电路层所占区域的面积。
一种集成电路封装方法，包括：所述基板设有电路层，在所述基板设置绝缘补丁，在所述绝缘补丁上制作精细连线，将至少两个所述芯片设置于所述基板，所述芯片设有精细引脚、以及芯片引脚，将所述芯片引脚与所述电路层电连接，将所述精细引脚与所述精细连线电连接，使至少两个所述芯片通过所述精细连线直接连接。
在其中一个实施例中，包括：所述电路层设有电路引脚，所述基板设有连接通孔，所述连接通孔与所述电路引脚对接；将芯片安放于所述基板的顶面，使所述芯片的芯片引脚与所述连接通孔的第一开口对接；通过所述连接通孔的第二开口在所述连接通孔内制作导电层，使所述导电层将所述芯片引脚与所述电路引脚电连接；或者，所述电路层设有电路引脚，将所述芯片安放于所述基板的顶面，使所述芯片的芯片引脚朝向所述基板，在所述基板上制作连接通孔，使所述连接通孔与所述电路引脚对接、并且所述连接通孔的第一开口与所述芯片引脚对接，通过所述连接通孔的第二开口在所述连接通孔内制作导电层，使所述导电层将所述芯片引脚与所述电路引脚电连接。
在其中一个实施例中，包括：所述基板底面或/和所述基板内设有所述附加电路层，所述附加电路层设有附加引脚，所述基板设有附加通孔，所述附加通孔与所述附加引脚对接；将芯片安放于所述基板的顶面，使所述芯片的芯片引脚与所述附加通孔的第一开口对接；通过所述附加通孔的第二开口在所述附加通孔内制作附加导电层，使所述附加导电层将所述芯片引脚与所述附加引脚电连接；或者，所述附加电路层设有附加引脚，将所述芯片安放于所述基板的顶面，使所述芯片的芯片引脚朝向所述基板，在所述基板上制作附加通孔，使所述附加通孔与所述附加引脚对接、并且所述附加通孔的第一开口与所述芯片引脚对接，通过所述附加通孔的第二开口在所述附加通孔内制作导电层，使所述导电层将所述芯片引脚与所述电路引脚电连接。
在其中一个实施例中，还包括：在所述基板设置封装层，所述芯片、所述绝缘补丁、以及所述精细引脚位于所述封装层与所述基板之间，所述封装层将所述芯片、所述绝缘补丁、以及所述精细引脚包裹封装。
在其中一个实施例中，在所述基板上设置导体层，在所述导体层上设置所述绝缘补丁，在所述绝缘补丁上设置导体膜，所述导体层的厚度大于所述导体膜的厚度，在所述导体层和导体膜上设置抗蚀剂，所述抗蚀剂设有连线图案，采用化学蚀刻方法，按照所述连线图案将所述导体层蚀刻成所述电路层、将所述导体膜蚀刻成所述精细连线。
在其中一个实施例中，在所述基板上设有所述电路层，在所述电路层上设置所述绝缘补丁，在所述绝缘补丁上设置光刻胶，在所述光刻胶制作连线槽，采用晶体生长的方式在所述连线槽内生长出所述精细连线。
在其中一个实施例中，在载体上制作绝缘补丁，在所述绝缘补丁上制作所述精细连线，将所述绝缘补丁连同所述精细连线转移至所述基板，将所述精细连线固定于所述基板。
在其中一个实施例中，所述芯片与所述精细引脚之间设置连接介质，所述连接介质包括绝缘介质、以及分布于所述绝缘介质内的至少一个精细导电颗粒；所述芯片引脚与所述精细引脚之间的间距小于或等于所述精细导电颗粒的高度，所述芯片安放于所述基板，所述精细导电颗粒的一端与所述精细引脚电连接、另一端与所述精细连线电连接；所述芯片引脚与所述精细连线之间的间距大于所述精细导电颗粒的高度，所述芯片引脚和所述精细连线不能通过所述导电颗粒电连接。
本发明的有益效果在于：
1、集成电路封装结构包括：基板，基板设有电路层以及精细连线；芯片，芯片设有精细引脚、以及芯片引脚；基板设有至少两个芯片，至少一个芯片的芯片引脚与电路层电连接，电路层上设有绝缘补丁，绝缘补丁上设有精细连线，芯片的精细引脚与精细连线电连接、至少两个芯片通过精细连线直接电连接。
芯片与电路层电连接，芯片可以与电路层上连接的其他电子元器件进行通讯或能量交换，芯片与芯片之间通过精细连线直接连接，减少受电路层上连接的其他电子元件的干扰，并且精细连线细小，在同样空间内可形成更多数量的连线，可以提供更高带宽的数据通讯能力，芯片之间可以获得更多的数据通道，传输速度快、带宽大。绝缘补丁将精细连线与电路层绝缘隔开，避免电路层对精细连线产生干扰。对要求高速度、款带宽的两个芯片之间的通讯，采用精细连线的方式，提高芯片之间的传输性能，对不要求高速度、宽带宽的两个芯片之间的通讯或者芯片与其他元器件之间的通讯可以通过电路层连接，降低制作成本。另一方面，采用设置绝缘补丁的方式，在基板上制作电路层、在预定位 置设置绝缘补丁和精细连线等几项工艺可以批量流水作业，降低生产成本。
2、精细引脚与精细连线之间设有连接介质，连接介质包括绝缘介质、以及分布于绝缘介质内的至少一个精细导电通道，绝缘介质将芯片与精细引脚隔开，只在精细引脚与精细连线的位置将，避免干扰，精细引脚通过精细导电通道与精细引脚电连接。精细导电通道的形式包括但不限于：在绝缘介质中设置导电颗粒或焊块构成精细导电通道；绝缘介质设有精细导电孔，在精细导电孔内设置导电材料层构成精细导电通道；在芯片上的精细引脚或/绝缘补丁上的精细连线上设置导电性的凸点，导电性凸点构成精细导电通道。
3、精细连线的宽度为0.1微米至2微米、或1微米至5微米。精细连线的宽度，指的是精细连线横截面在绝缘补丁上的边长，精细连线的宽度小于电路层的连线的宽度，精细连线的宽度越小，可实现的连线密度越大，在同样大小的空间里可以设有越多的通讯连线数量，利于提高数据传输速度和带宽。
4、在芯片的上设有散热装置。由于芯片之间的通讯采用高带宽高速度的精细连线，芯片运算速率高、发热也增大，在芯片上加装散热装置，有利于芯片散热，保障工作性能。另一方面，绝缘补丁可能(如采用导热率高的材料则不存在此问题)会增加芯片向基板方向散热的难度，热阻抗增大，而且在芯片上(背相基板的一面)加装散热装置，有利于芯片从背面散热，不只依靠从基板的散热通道，这样，芯片就可以在更高的运算速度下正常工作。这种结构上的设计，一方面提高芯片之间的数据通讯带宽和速度、一方面保证芯片可以在更高的运算速度下正常工作，可以大幅提高系统整体的运算性能。
5、集成电路封装结构还包括有封装层，芯片、精细连线、以及绝缘补丁位于封装层与基板之间，封装层将芯片以及绝缘补丁封装于基板。封装层可以保护芯片、绝缘补丁、精细连线不被损坏，减少外部环境因素对芯片性能的影响和干扰，保障芯片的工作性能。在有更多后续工序的情况下，固化后的封装层也提供了平整的表面和机械支撑性能，能够翻转系统整体后在基板上进行后续制成工艺。
6、基板为柔性电路板，或基板包括至少两层层叠设置的柔性电路板。使 用多层电路板及其内含的多层电路层，可以提供更多布线的可能，提高芯片的性能，使用柔性轻薄的电路板，降低系统整体的重量、减小体积和厚度尺寸，通过采用本发明的集成电路封装结构和方法，可以使系统整体在封装集成之后仍然具有足够的柔性，可以用于可穿戴产品。并且，采用绝缘补丁的方式，精细连线本身的厚度很小，绝缘补丁只要满足将精细连线与电路层绝缘就可以，不需要很厚的厚度，使得柔性电路板在集成芯片后仍然很薄、具备柔性。精细连线的厚度是指精细连线的横截面垂直于绝缘补丁的边长，绝缘补丁的厚度是指绝缘补丁的横截面垂直于基板的边长。
7、芯片位于基板的顶面，基板底面或/和基板内设有附加电路层，附加电路层设有附加引脚，基板设有附加通孔，附加通孔与附加引脚对接、并且附加通孔的第一开口与芯片引脚对接，附加通孔的第二开口为操作窗口，附加通孔内设有附加导电层，附加导电层将芯片引脚和附加引脚电连接。
所述附加电路层具有附加引脚，可以预先在基板制作好附加电路层，也可以在集成电路封装时再在基板上制作附加电路层，附加引脚可以是附加电路层直接引出的连接部，也可以是和所述连接部电连接的扩展引脚，只要通过附加引脚能够和附加电路层电连接均可。将芯片安放于所述基板，可以将芯片固定于基板上，也可以不固定。芯片与基板相对设置，所述芯片朝向所述基板的一面具有芯片引脚，芯片的芯片引脚包括但不限于芯片内部引出的连接部、与连接部电连接的扩展脚，只要通过芯片引脚能够和芯片电连接均可。在所述基板上制作附加通孔，使所述芯片引脚与所述附加通孔的第一开口对接，通过所述附加通孔的第二开口在所述附加通孔内制作附加导电层，所述附加导电层将所述芯片引脚与所述附加引脚电连接；芯片引脚位于基板的顶面，通过附加通孔的第二开口，可以从基板的底面将芯片与附加电路层电连接，以避免芯片从上方将芯片引脚遮挡；
其中，附加通孔与芯片引脚对接，附加引脚至少部分位于附加通孔的第一开口附近、或深入附加通孔内，使得附加导电层可以与芯片引脚电连接；附加引脚和附加通孔对接，附加引脚至少部分位于附加通孔的第一开口附近、或第 二开口附近、或附加通孔内壁的附近，使得附加导电层可以与附加引脚电连接；芯片可以是芯片或者电子元件(包括但不限于电阻、电容)或者其他电子器件(包括但不限于天线)。芯片可以通过附加通孔、附加导电层固定于所述基板，也可以是，芯片通过其他方式(包括但不限于粘贴、模压塑料包封)固定于基板。
如此，可以降低集成电路封装的成本、节约封装时间，进一步的，可以在很大面积的大面板上同时安装多个芯片，大面板上的批量处理进一步减低成本、节约封装时间。并且，可以降低基板和芯片构成的系统整体的厚度，甚至基板和芯片之间不需要预留间隙(原则上无需预留间隙，但是根据需要可以在基板与芯片设置其他材料)；导电附加通孔的制作可以选择使用不需要加热焊接的工艺流程，因此可以避免高温热循环时各种热机械应力分布对超薄芯片和柔性电路板的机构和性能的损伤。这对使用超薄、柔性的电路板的封装工艺很有帮助。另一方面，在传统的引线键合封装技术中，采用导线来实现芯片与基板上电路层的电连接，而导线要相互避开，于是占用空间较大，本发明通过在基板上开设附加通孔的方式实现芯片与附加电路层的电连接，附加导电层设于附加通孔内，不占用额外空间，可以缩小封装后整体的体积，特别是，对于超薄电路板能很好的保持轻薄的特性，对于柔性电路板，能很好保持其柔性。
优选的，包括但不限于下述两种制作方法：
(1)基板底面或/和基板内设有附加电路层，附加电路层设有附加引脚，基板设有附加通孔，附加通孔与附加引脚对接；将芯片安放于基板的顶面，使芯片的芯片引脚与附加通孔的第一开口对接；通过附加通孔的第二开口在附加通孔内制作附加导电层，使附加导电层将芯片引脚与附加引脚电连接；
或者(2)，附加电路层设有附加引脚，将芯片安放于基板的顶面，使芯片的芯片引脚朝向基板，在基板上制作附加通孔，使附加通孔与附加引脚对接、并且附加通孔的第一开口与芯片引脚对接，通过附加通孔的第二开口在附加通孔内制作导电层，使导电层将芯片引脚与电路引脚电连接。
8、芯片引脚为至少两个，导电层为与芯片引脚相应的至少两个，基板的 底面设有外接端口，外接端口与至少一个导电层电连接。外接端口可以与另外的电子元件进行连接，扩展整个集成电路的功能，也可以用于连接电源，由电源直接对芯片供电。
9、基板设有连接通孔，连接通孔与电路引脚对接、并且连接通孔的第一开口与芯片引脚对接，连接通孔的第二开口为操作窗口，连接通孔内设有导电层，导电层将芯片引脚和电路引脚电连接。
所述电路层具有电路引脚，可以预先在基板制作好电路层，也可以在集成电路封装时再在基板上制作电路层，电路引脚可以是电路层直接引出的连接部，也可以是和所述连接部电连接的扩展引脚，只要通过电路引脚能够和电路层电连接均可。将芯片安放于所述基板，可以将芯片固定于基板上，也可以不固定。芯片与基板相对设置，所述芯片朝向所述基板的一面具有芯片引脚，芯片的芯片引脚包括但不限于芯片内部引出的连接部、与连接部电连接的扩展脚，只要通过芯片引脚能够和芯片电连接均可。在所述基板上制作连接通孔，使所述芯片引脚与所述连接通孔的第一开口对接，通过所述连接通孔的第二开口在所述连接通孔内制作导电层，所述导电层将所述芯片引脚与所述电路引脚电连接；芯片引脚位于基板的顶面，通过连接通孔的第二开口，可以从基板的底面将芯片与电路层电连接，避免芯片将芯片引脚挡住；
其中，连接通孔与芯片引脚对接，电路引脚至少部分位于连接通孔的第一开口附近、或深入连接通孔内，使得导电层可以与芯片引脚电连接；电路引脚和连接通孔对接，电路引脚至少部分位于连接通孔的第一开口附近、或第二开口附近、或连接通孔内壁的附近，使得导电层可以与电路引脚电连接；芯片可以是芯片或者电子元件(包括但不限于电阻、电容)或者其他电子器件(包括但不限于天线)。芯片可以通过连接通孔、导电层固定于所述基板，也可以是，芯片通过其他方式(包括但不限于粘贴、模压塑料包封)固定于基板。
如此，可以降低集成电路封装的成本、节约封装时间，进一步的，可以在很大面积的大面板上同时安装多个芯片，大面板上的批量处理进一步减低成本、节约封装时间。并且，降低基板和芯片构成的整体的厚度，甚至基板和芯片之 间不需要预留间隙(原则上无需预留间隙，但是根据需要可以在基板与芯片设置其他材料)；不需要进行加热焊接的步骤，特别是针对超薄的基板、柔性电路板的封装，避免高温下基板发生翘曲、降低性能。另一方面，传统的电子封装采用导线实现芯片与基板电路层的电连接，而导线占用巨大空间，本发明通过在基板上开设连接通孔的方式实现芯片与电路层的电连接，导电层设于连接通孔内，不占用额外空间，可以小封装后整体的体积，特别是，对于超薄电路板能很好的保持轻薄的特性，对于柔性电路板，能很好保持其柔性。
优选的，包括但不限于下述两种制作方法：
(1)电路层设有电路引脚，基板设有连接通孔，连接通孔与电路引脚对接；将芯片安放于基板的顶面，使芯片的芯片引脚与连接通孔的第一开口对接；通过连接通孔的第二开口在连接通孔内制作导电层，使导电层将芯片引脚与电路引脚电连接；
或者(2)，电路层设有电路引脚，将芯片安放于基板的顶面，使芯片的芯片引脚朝向基板，在基板上制作连接通孔，使连接通孔与电路引脚对接、并且连接通孔的第一开口与芯片引脚对接，通过连接通孔的第二开口在连接通孔内制作导电层，使导电层将芯片引脚与电路引脚电连接。
10、绝缘补丁所占区域的面积小于电路层所占区域的面积。绝缘补丁、以及其上的精细连线构成一个精细连接区域，根据需要，可以在两个芯片之间设置一个或两个以上的精细连接区域，也可以一个芯片通过两个以上的精细连接区域同时与另外两个以上的芯片电连接；并且，设置精细连接区域不需要对原有电路层做出改动，精细连接区域运用灵活，按需设置，降低成本。
11、集成电路封装方法，还包括：在基板上设置导体层，在导体层上设置绝缘补丁，在绝缘补丁上设置导体膜，导体层的厚度大于导体膜的厚度，在导体层和导体膜上设置抗蚀剂，抗蚀剂设有连线图案，采用化学蚀刻方法，按照连线图案将导体层蚀刻成电路层、将导体膜蚀刻成精细连线。可以统一在导体层和导体膜上都设置好抗蚀剂后，统一进行化学蚀刻，按照连线图案将电路层和精细连线统一成型，节约步骤、提高效率、降低生产成本，并且可以对多基 板上的所有电路层、导体膜同时进行，利于批量生产，进一步降低成本。此外，导体膜的厚度与精细连线的厚度相当，导体层的厚度于电路层的厚度相当，例如当精细连线的厚度小于电路层的厚度时，导体膜的厚度小于导体层的厚度。
16、在所述基板上设有所述电路层，在所述电路层上设置所述绝缘补丁，在所述绝缘补丁上设置光刻胶，在所述光刻胶制作连线槽，采用晶体生长的方式在在所述连线槽内和光刻胶表面制作导体膜，剥离光刻胶，在所述连线槽内形成所述精细连线。采用晶体生长的方式可以获得更精细的精细连线、获得更多的连接点，进一步提高芯片功能。晶体生长的方式是指将导电材料附着于连线槽内形成精细连线的方式，包括但不限于：电镀、溅镀、蒸镀。
17、在载体上制作绝缘补丁，在绝缘补丁上制作精细连线，将绝缘补丁连同精细连线转移至基板，将精细连线固定于基板。这种制作方式，可以完全分离精细连线和一般连线的制作工艺，可以回避不同线宽线距的连线混合制作时的各种困难，譬如，为达到不同的成线精度，可能需要不同的抗蚀膜材料和厚度；因为需要在一次光刻和蚀刻过程中同时实现较宽的一般连线和较细的精细连线，需要在不同高度上同时成像光刻不同精度的图案，可能因此一般连线的制作也须使用更昂贵的光刻设备，也可能影响产能效率。此外，采用单独制作绝缘补丁后再转移粘贴至基板的方式，不需要对原有的电路层做改动，便于对旧的集成电路进行改造升级。可以直接将精细连线固定于基板；也可以是，将精细连线固定于绝缘补丁，将绝缘补丁固定于基板，通过绝缘补丁将精细连线固定于基板。
18、在芯片与精细引脚之间设置连接介质，连接介质包括绝缘介质、以及分布于绝缘介质内的至少一个精细导电颗粒；精细连线与精细引脚之间的间距小于或等于精细导电颗粒的高度，芯片安放于基板时，精细导电颗粒的一端与精细引脚电连接、另一端与精细连线电连接，精细引脚和精细连线通过精细导电颗粒电连接；芯片引脚与精细连线之间的间距大于精细导电颗粒的高度，芯片引脚和精细连线不能通过导电颗粒电连接。
封装时，将绝缘介质设置在芯片与精细引脚之间，将芯片挤向绝缘补丁达 到预设位置，由于精细引脚与精细连线之间的间距小于或等于精细导电颗粒的高度，精细导电颗粒受挤压，一端与精细引脚电连接、另一端与精细连线电连接，从而将精细引脚和精细连线电连接；芯片引脚与精细连线之间的间距大于精细导电颗粒的高度，在芯片引脚与精细连线之间的精细导电颗粒不能同时接触芯片引脚和精细连线，所以精细导电颗粒不能将芯片引脚和精细连线电连接。
精细引脚与精细连线之间设有连接介质，还包括以下情况：除了精细引脚所处区域附近，芯片的其他部分与精细连线之间也设有连接介质，芯片引脚与电路层之间的间距大于精细导电颗粒的高度，在芯片引脚与电路层之间的精细导电颗粒不能同时接触芯片引脚和精细连线，所以精细导电颗粒不能将芯片引脚和精细连线电连接。
还可以是，连接介质具有粘贴属性，可以将芯片粘贴于基板上，封装时，将绝缘介质设置在芯片与精细引脚之间，将芯片挤向绝缘补丁达到预设位置，芯片给粘贴于基板、同时精细引脚和精细连线的电连接，制作工艺简单、效率高。
附图说明
图1为本发明实施例集成电路封装结构及方法示意图一；
图2为本发明实施例集成电路封装结构及方法示意图二；
图3为本发明实施例集成电路封装结构及方法示意图三；
图4为本发明实施例集成电路封装结构及方法示意图四；
图5为本发明实施例集成电路封装结构及方法示意图五；
图6为本发明实施例集成电路封装结构示意图一；
图7为本发明实施例集成电路封装结构示意图二。
附图标记说明：
100、基板，101、导体层，102、附加导体层，110、电路层，120、附加电路层，130、连接通孔，140、外接端口，200、绝缘补丁，201、导体膜，210、精细连线，300、抗蚀剂，400、芯片，410、芯片引脚，420、精细引脚， 500、导电层，610、精细导电颗粒，620、绝缘介质。
具体实施方式
下面对本发明作进一步详细说明，但本发明的实施方式不限于此。
实施例一
如图5所示，并参照图1至4，集成电路封装结构包括：基板100，基板100设有电路层110以及精细连线210；芯片400，芯片400设有精细引脚420、以及芯片引脚410；基板100设有至少两个芯片400，至少一个芯片400的芯片引脚410与电路层110电连接，电路层110上设有绝缘补丁200，绝缘补丁200上设有精细连线210，芯片400的精细引脚420与精细连线210电连接、至少两个芯片400通过精细连线210直接电连接。芯片400与电路层110电连接，芯片400可以与电路层110上连接的其他电子元器件进行通讯或能量交换，芯片400与芯片400通过精细连线210直接连接，不受电路层110的干扰、不受电路层110上连接的其他电子元件的干扰，并且精细连线210细小，芯片400之间可以获得跟多的数据传输通道，传输速度快、带宽大。绝缘补丁200将精细连线210与电路层110绝缘隔开，避免电路层110对精细连线210产生干扰。对要求高速度、款带宽的两个芯片400之间的通讯，采用精细连线210的方式，提高芯片400之间的传输性能，对不要求高速度、款带宽的两个芯片400之间的通讯，可以通过电路层110连接，降低制作成本。另一方面，采用设置绝缘补丁200的方式，可以统一制作电路层110，统一在预定位置设置绝缘补丁200和精细连线210，可以批量流水作业，降低生产成本。
如图5所示，精细引脚420设于芯片400的边沿附近，绝缘补丁200、精细连线210横跨两个芯片400之间。绝缘补丁200所占区域的面积小于电路层110所占区域的面积。绝缘补丁200、以及其上的精细连线210构成一个精细连接区域，根据需要，可以在两个芯片400之间设置一个或两个以上的精细连接区域，也可以一个芯片400通过两个以上的精细连接区域同时与另外两个以上的芯片400电连接；并且，设置精细连接区域不需要对原有电路层110做出改 动，精细连接区域运用灵活，按需设置，降低成本。绝缘补丁200所占区域的面积可以参照图5所示从上往下俯视时，绝缘补丁200在基板100上占据的面积、电路层110在基板100上占据的面积。
精细连线210的宽度，指的是精细连线210横截面在绝缘补丁200上的边长，精细连线210的宽度小于电路层110的连线的宽度，精细连线210的宽度越小，在同样的空间可以获得越多的连接点，有利于提高数据传输速度和带宽。本实施例中，精细连线210的宽度为0.1微米至2微米、或1微米至5微米，可以根据需要选择。优选的，精细连线210的宽度可以选择为0.1微米、0.2微米、0.5微米、0.7微米、1微米、1.2微米、1.5微米、1.7微米、2微米、2.5微米、3微米、3.5微米、4微米、4.5微米、或5微米。
如图5所示，芯片引脚410与精细引脚420之间设有连接介质，连接介质包括绝缘介质620、以及分布于绝缘介质620内的至少一个精细导电通道，绝缘介质620使芯片400与精细引脚420绝缘地隔开，避免干扰，精细引脚420通过精细导电通道与精细引脚420电连接。精细导电通道的形式包括但不限于：在绝缘介质620中设置导电颗粒或焊块构成精细导电通道；绝缘介质620设有精细导电孔，在精细导电孔的内壁上设置导电材料层构成精细导电通道，例如硅通孔；在精细引脚420或/和精细连线210上设置导电性的凸点，导电性，导电性的凸点构成精细导电通道。
集成电路封装结构还包括有封装层，封装层未在图中示出，芯片400、精细连线210、以及绝缘补丁200位于封装层与基板100之间，封装层将芯片400以及绝缘补丁200封装与基板100。封装层可以保护芯片400、绝缘补丁200、精细连线210不被损坏，减少外部环境因素对芯片性能的影响和干扰，保障芯片400的工作性能。
芯片400上设有散热装置。使用绝缘补丁可能会增加芯片400向基板方向散热的难度，热阻抗增大，而且芯片400之间的通讯采用高带宽高速度的精细连线，芯片400运算速率高、发热也增大，在芯片400上(背向基板的一面)加装散热装置，有利于芯片400从背面的散热装置方向散热，不只依靠从基板 100方向的散热通道，这样，芯片400就可以在更高的运算速度下正常工作。这种结构上的设计，一方面提高芯片400之间的数据通讯带宽和速度、一方面保证芯片400可以在更高的运算速度下正常工作，从而大幅提高系统整体的运算性能。散热装置也被封装层封装于基板100上，散热装置的顶面可以从封装层中露出散热，也可以不露出。
如图7所示，基板100设有连接通孔130，连接通孔130与电路引脚对接、并且连接通孔130的第一开口与芯片引脚410对接，连接通孔130的第二开口为操作窗口，连接通孔130内设有导电层500，导电层500将芯片引脚410和电路引脚电连接。电路层110具有电路引脚，可以预先在基板100制作好电路层110，也可以在集成电路封装时再在基板100上制作电路层110，电路引脚可以是电路层110直接引出的连接部，也可以是和连接部电连接的扩展引脚，只要通过电路引脚能够和电路层110电连接均可。将芯片400安放于基板100，可以将芯片400固定于基板100上，也可以不固定。芯片400与基板100相对设置，芯片400朝向基板100的一面具有芯片引脚410，芯片400的芯片引脚410包括但不限于芯片400内部引出的连接部、与连接部电连接的扩展脚，只要通过芯片引脚410能够和芯片400电连接均可。在基板100上制作连接通孔130，使芯片引脚410与连接通孔130的第一开口对接，通过连接通孔130的第二开口在连接通孔130内制作导电层500，导电层500将芯片引脚410与电路引脚电连接；芯片引脚410位于基板100的顶面，通过连接通孔130的第二开口，可以从基板100的底面将芯片400与电路层110电连接，避免芯片400将芯片引脚410挡住；其中，连接通孔130与芯片引脚410对接，电路引脚至少部分位于连接通孔130的第一开口附近、或深入连接通孔130内，使得导电层500可以与芯片引脚410电连接；电路引脚和连接通孔130对接，电路引脚至少部分位于连接通孔130的第一开口附近、或第二开口附近、或连接通孔130内壁的附近，使得导电层500可以与电路引脚电连接；芯片400可以是芯片400或者电子元件(包括但不限于电阻、电容)或者其他电子器件(包括但不限于天线)。芯片400可以通过连接通孔130、导电层500固定于基板100，也 可以是，芯片400通过其他方式(包括但不限于粘贴、模压塑料包封)固定于基板100。如此，可以降低集成电路封装的成本、节约封装时间，进一步地，可以在很大面积的大面板上同时安装多个芯片400，大面板上的批量处理进一步减低成本、节约封装时间。并且，降低基板100和芯片400构成的整体的厚度，甚至基板100和芯片400之间不需要预留间隙(原则上无需预留间隙，但是根据需要可以在基板100与芯片400设置其他材料)；连接通孔130的制作可以选择使用不需要加热焊接的工艺流程，因此可以避免高温热循环时各种热机械应力分布对超薄芯片和柔性电路板的机构和性能的损伤。这对使用超薄、柔性的电路板的封装工艺很有帮助。另一方面，在传统的引线键合封装技术中，采用导线来实现芯片400与基板100上电路的电连接，而导线要相互避开，于是占用空间较大，本发明通过在基板100上开设连接通孔130的方式实现芯片与附加电路层120的电连接，导电层500设于连接通孔130内，不占用额外空间，可以缩小封装后整体的体积，特别是，对于超薄电路板能很好的保持轻薄的特性，对于柔性电路板，能很好保持其柔性。
优选的，包括但不限于下述两种制作方法：
(1)电路层110设有电路引脚，基板100设有连接通孔130，连接通孔130与电路引脚对接；将芯片400安放于基板100的顶面，使芯片400的芯片引脚410与连接通孔130的第一开口对接；通过连接通孔130的第二开口在连接通孔130内制作导电层500，使导电层500将芯片引脚410与电路引脚电连接；
或者(2)，电路层110设有电路引脚，将芯片400安放于基板100的顶面，使芯片400的芯片引脚410朝向基板100，在基板100上制作连接通孔130，使连接通孔130与电路引脚对接、并且连接通孔130的第一开口与芯片引脚410对接，通过连接通孔130的第二开口在连接通孔130内制作导电层500，使导电层500将芯片引脚410与电路引脚电连接。
本实施例中，如图7所示，连接通孔130同时也是附加通孔，基板100底面和基板100内设有分别附加电路层120，附加电路层120设有附加引脚，附 加通孔(连接通孔130)与附加引脚对接、并且附加通孔(连接通孔130)的第一开口与芯片引脚410对接，附加通孔(连接通孔130)的第二开口为操作窗口，附加通孔(连接通孔130)内设有附加导电层500，附加导电层500将芯片引脚410和附加引脚电连接。并且，在所述基板100的底面设置外接端口140，使所述外接端口140与至少一个所述导电层500电连接。外接端口140可以与另外的电子元件进行连接，扩展整个集成电路的功能，也可以用于连接电源，由电源直接对芯片400供电。
基板100可以是普通线路板、也可以是柔性电路板，还可以是基板100包括至少两层层叠设置的柔性电路板。使用多层电路板及其内含的多层电路，可以提供更多布线的可能，提高芯片400的使用性能；使用柔性轻薄的电路板，降低系统整体的重量、减小体积和厚度尺寸，在适当的系统设计和封装层材料的选择下，可以使系统整体在封装集成之后仍然具有足够的柔性，可以用于可穿戴产品。并且，采用绝缘补丁200的方式，精细连线210本身的厚度很小，绝缘补丁200只要满足将精细连线210与基板100其它区域绝缘就可以，也不需要很厚的厚度，这有助于系统整体保持柔性和薄度。精细连线210的厚度是指精细连线210的横截面垂直于绝缘补丁200的边长，绝缘补丁200的厚度是指绝缘补丁200的横截面垂直于基板100的边长。精细连线210的厚度是指精细连线210的横截面垂直于绝缘补丁200的边长，绝缘补丁200的厚度是指绝缘补丁200的横截面垂直于基板100的边长。
本实施例中，集成电路封装方法主要包括：基板100预设有电路层110，在基板100设置绝缘补丁200，在绝缘补丁200上制作精细连线210，将至少两个芯片400设置于基板100，芯片400设有精细引脚420、以及芯片引脚410，将芯片引脚410与电路层110电连接，将精细引脚420与精细连线210电连接，使至少两个芯片400通过精细连线210直接连接。
当通过连接通孔130的方式进行连接时，还包括步骤：电路层110预设有电路引脚，基板100预设有连接通孔130，连接通孔130与电路引脚对接；将芯片400安放于基板100的顶面，使芯片400的芯片引脚410与连接通孔130 的第一开口对接；通过连接通孔130的第二开口在连接通孔130内制作导电层500，使导电层500将芯片引脚410与电路引脚电连接；或者，电路层110预设有电路引脚，将芯片400安放于基板100的顶面，使芯片400的芯片引脚410朝向基板100，在基板100上制作连接通孔130，使连接通孔130与电路引脚对接、并且连接通孔130的第一开口与芯片引脚410对接，通过连接通孔130的第二开口在连接通孔130内制作导电层500，使导电层500将芯片引脚410与电路引脚电连接。
当通过附加通孔的方式进行连接时，还包括步骤：基板100底面或/和基板100内预设有附加电路层120，附加电路层120预设有附加引脚，基板100预设有附加通孔，附加通孔与附加引脚对接；将芯片400安放于基板100的顶面，使芯片400的芯片引脚410与附加通孔的第一开口对接；通过附加通孔的第二开口在附加通孔内制作附加导电层500，使附加导电层500将芯片引脚410与附加引脚电连接；或者，附加电路层120预设有附加引脚，将芯片400安放于基板100的顶面，使芯片400的芯片引脚410朝向基板100，在基板100上制作附加通孔，使附加通孔与附加引脚对接、并且附加通孔的第一开口与芯片引脚410对接，通过附加通孔的第二开口在附加通孔内制作导电层500，使导电层500将芯片引脚410与电路引脚电连接。
集成电路封装方法还包括将芯片400封装：在基板100设置封装层，芯片400、绝缘补丁200、以及精细连线210位于封装层与基板100之间，封装层将芯片400、绝缘补丁200、以及精细连线210包裹封装。封装后，将基板100、芯片400、封装层、绝缘补丁200、精细连线210等组成的系统整体进行裁剪，根据预设的功能、大小等参数裁剪为若干小的系统单元，这样统一在基板100上安装芯片400并封装好，之后再裁剪为合适大小的系统单元，可以大幅提高生产效率，降低成本。
实施例二
实施例二与实施例一的区别在于：
如图1至5所示，在基板100上不预设电路层110，而在制作精细连线210时同时制作电路层110，具体制作方法为：在基板100上设置导体层101、附加导体层102，在导体层101上设置绝缘补丁200，在绝缘补丁200上设置导体膜201，导体层101的厚度远大于导体膜201的厚度，在导体层101、附加导体层102和导体膜201上设置抗蚀剂300，在抗蚀剂300中设置连线图案，采用化学蚀刻方法，按照连线图案将导体层101蚀刻成电路层110、将导体膜201蚀刻成精细连线210。可以统一在导体层101、附加导体层102和导体膜201上都设置好抗蚀剂300后，统一进行化学蚀刻，按照连线图案将电路层110、附加电路层120和精细连线210统一成型，节约步骤、提高效率、降低生产成本，并且可以对多基板100上的所有电路层110、附加导体层102、以及导体膜201同时进行，利于批量生产，进一步降低成本。此外，导体膜201的厚度与精细连线210的厚度相当，导体层101的厚度与电路层110的厚度相当，例如当精细连线210的厚度远小于电路层110的厚度时，导体膜201的厚度需要远小于导体层101的厚度。
实施例三
实施例三与实施例一的区别在于：
绝缘补丁200、精细连线210的制作方法为：基板100上预设电路层110，在电路层110上设置绝缘补丁200，在绝缘补丁200上设置光刻胶，在所述光刻胶制作连线槽，在所述连线槽内和光刻胶表面生长导体膜，剥离光刻胶，就在所述连线槽内形成所述精细连线210。
实施例四
实施例四与实施例一的区别在于：
绝缘补丁200、精细连线210的制作方法为：在载体上制作可剥离层、绝缘补丁200，在绝缘补丁200上制作精细连线210，将绝缘补丁200连同精细连线210转移至基板100，将精细连线210固定于基板100。例如，可以将绝缘补 丁200、精细连线210翻转至另一个载体上，另一载体将将绝缘补丁200、精细连线210再次翻转至基板上，使精细连线210朝上，将精细连线210和其下的绝缘补丁200一起固定于基板100。
实施例五
实施例五与实施例一的区别在于：
如图6所示，实现将精细引脚420和精细连线210电连接的方法为：在芯片400与精细引脚420之间设置连接介质，连接介质包括绝缘介质620、以及分布于绝缘介质620内的至少一个精细导电颗粒610，精细导电颗粒610相互之间被绝缘介质620保持绝缘，芯片引脚410与精细引脚420之间的间距小于或等于精细导电颗粒610的高度，所述芯片400上精细引脚420与所述绝缘补丁200上的精细连线210之间间距小，精细导电颗粒610分布密度高，芯片400安放于基板100，精细导电颗粒610的一端与精细引脚420电连接、另一端与精细连线210电连接，形成至少一条由精细导电颗粒610构成的导电通道；芯片引脚410与电路层110之间的间距大于精细导电颗粒610的高度，所述芯片引脚410与电路层110之间的间距大，精细导电颗粒610分布密度低，芯片引脚410和电路层110不能通过导电颗粒电连接，不能形成任何由所述精细导电颗粒610构成的导电通道，所述芯片引脚410和所述电路层110之间保持电绝缘。将绝缘介质620设置在芯片400与精细引脚420之间，将芯片400挤向绝缘补丁200达到预设位置，由于芯片引脚410与精细引脚420之间的间距小于或等于精细导电颗粒610的高度，精细导电颗粒610受挤压，一端与精细引脚420电连接、另一端与精细连线210电连接，从而将精细引脚420和精细连线210电连接；芯片引脚410与电路层110之间的间距大于精细导电颗粒610的高度，在芯片引脚410与电路层110之间的精细导电颗粒610不能同时接触芯片引脚410和精细连线210，所以精细导电颗粒610不能将芯片引脚410和精细连线210电连接。这种连接方式，将芯片400安放于绝缘补丁200的过程就实现了精细引脚420和精细连线210的电连接，工艺简单、效率高。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种集成电路封装结构，其特征在于，包括：
    基板，所述基板设有电路层以及精细连线；
    芯片，所述芯片设有精细引脚、以及芯片引脚；
    所述基板设有至少两个所述芯片，至少一个所述芯片的所述芯片引脚与所述电路层电连接，所述电路层上设有绝缘补丁，所述绝缘补丁上设有精细连线，所述芯片的精细引脚与所述精细连线电连接、至少两个所述芯片通过所述精细连线直接电连接。
  2. 根据权利要求1所述的集成电路封装结构，其特征在于，所述芯片引脚与所述精细连线之间设有连接介质，所述连接介质包括绝缘介质、以及分布于所述绝缘介质内的至少一个精细导电通道，所述精细引脚通过所述精细导电通道与所述精细连线电连接。
  3. 根据权利要求1所述的集成电路封装结构，其特征在于，所述精细连线的宽度为0.1微米至2微米、或1微米至5微米。
  4. 根据权利要求1所述的集成电路封装结构，其特征在于，在所述芯片的上设有散热装置。
  5. 根据权利要求1所述的集成电路封装结构，其特征在于，还包括有封装层，所述芯片、所述精细连线、以及所述绝缘补丁位于所述封装层与所述基板之间，所述封装层将所述芯片以及所述绝缘补丁封装与所述基板。
  6. 根据权利要求1所述的集成电路封装结构，其特征在于，所述基板为柔性电路板，或所述基板包括至少两层层叠设置的柔性电路板。
  7. 根据权利要求1至6任一项所述的集成电路封装结构，其特征在于，所述芯片位于所述基板的顶面，所述基板底面或/和所述基板内设有附加电路层，所述附加电路层设有附加引脚，所述基板设有附加通孔，所述附加通孔与所述附加引脚对接、并且所述附加通孔的第一开口与所述芯片引脚对接，所述附加通孔的第二开口为操作窗口，所述附加通孔内设有附加导电层，所述附加导电层将所述芯片引脚和所述附加引脚电连接。
  8. 根据权利要求7所述的集成电路封装结构，其特征在于，所述芯片引 脚为至少两个，所述附加导电层为与所述芯片引脚相应的至少两个，所述基板的底面设有外接端口，所述外接端口与至少一个所述附加导电层电连接。
  9. 根据权利要求1至6任一项所述的集成电路封装结构，其特征在于，所述基板设有连接通孔，所述连接通孔与所述电路引脚对接、并且所述连接通孔的第一开口与所述芯片引脚对接，所述连接通孔的第二开口为操作窗口，所述连接通孔内设有导电层，所述导电层将所述芯片引脚和所述电路引脚电连接。
  10. 根据权利要求1至6任一项所述的集成电路封装结构，其特征在于，所述绝缘补丁所占区域的面积小于所述电路层所占区域的面积。
  11. 一种集成电路封装方法，其特征在于，包括：
    所述基板设有电路层，在所述基板设置绝缘补丁，在所述绝缘补丁上制作精细连线，将至少两个所述芯片设置于所述基板，所述芯片设有精细引脚、以及芯片引脚，将所述芯片引脚与所述电路层电连接，将所述精细引脚与所述精细连线电连接，使至少两个所述芯片通过所述精细连线直接连接。
  12. 根据权利要求11所述的集成电路封装方法，其特征在于，包括：
    所述电路层设有电路引脚，所述基板设有连接通孔，所述连接通孔与所述电路引脚对接；将芯片安放于所述基板的顶面，使所述芯片的芯片引脚与所述连接通孔的第一开口对接；通过所述连接通孔的第二开口在所述连接通孔内制作导电层，使所述导电层将所述芯片引脚与所述电路引脚电连接；
    或者，所述电路层设有电路引脚，将所述芯片安放于所述基板的顶面，使所述芯片的芯片引脚朝向所述基板，在所述基板上制作连接通孔，使所述连接通孔与所述电路引脚对接、并且所述连接通孔的第一开口与所述芯片引脚对接，通过所述连接通孔的第二开口在所述连接通孔内制作导电层，使所述导电层将所述芯片引脚与所述电路引脚电连接。
  13. 根据权利要求11所述的集成电路芯片封装方法，其特征在于，包括：
    所述基板底面或/和所述基板内设有所述附加电路层，所述附加电路层设有附加引脚，所述基板设有附加通孔，所述附加通孔与所述附加引脚对接；将芯片安放于所述基板的顶面，使所述芯片的芯片引脚与所述附加通孔的第一开口 对接；通过所述附加通孔的第二开口在所述附加通孔内制作附加导电层，使所述附加导电层将所述芯片引脚与所述附加引脚电连接；
    或者，所述附加电路层设有附加引脚，将所述芯片安放于所述基板的顶面，使所述芯片的芯片引脚朝向所述基板，在所述基板上制作附加通孔，使所述附加通孔与所述附加引脚对接、并且所述附加通孔的第一开口与所述芯片引脚对接，通过所述附加通孔的第二开口在所述附加通孔内制作导电层，使所述导电层将所述芯片引脚与所述电路引脚电连接。
  14. 根据权利要求11所述的集成电路芯片封装方法，其特征在于，还包括：在所述基板设置封装层，所述芯片、所述绝缘补丁、以及所述精细引脚位于所述封装层与所述基板之间，所述封装层将所述芯片、所述绝缘补丁、以及所述精细引脚包裹封装。
  15. 根据权利要求11至14任一项所述的集成电路封装方法，其特征在于，在所述基板上设置导体层，在所述导体层上设置所述绝缘补丁，在所述绝缘补丁上设置导体膜，所述导体层的厚度大于所述导体膜的厚度，在所述导体层和导体膜上设置抗蚀剂，所述抗蚀剂设有连线图案，采用化学蚀刻方法，按照所述连线图案将所述导体层蚀刻成所述电路层、将所述导体膜蚀刻成所述精细连线。
  16. 根据权利要求11至14任一项所述的集成电路封装方法，其特征他在于，在所述基板上设有所述电路层，在所述电路层上设置所述绝缘补丁，在所述绝缘补丁上设置光刻胶，在所述光刻胶制作连线槽，采用晶体生长的方式在在所述连线槽内和光刻胶表面制作导体膜，剥离光刻胶，在所述连线槽内形成所述精细连线。
  17. 根据权利要求11至14任一项所述的集成电路封装方法，其特征他在于，在载体上制作绝缘补丁，在所述绝缘补丁上制作所述精细连线，将所述绝缘补丁连同所述精细连线转移至所述基板，将所述精细连线固定于所述基板。
  18. 根据权利要求11至14任一项所述的集成电路封装结构，其特征在于，所述芯片与所述精细连线之间设置连接介质，所述连接介质包括绝缘介质、以 及分布于所述绝缘介质内的至少一个精细导电颗粒；所述精细引脚与所述精细引脚之间的间距小于或等于所述精细导电颗粒的高度，所述精细导电颗粒的一端与所述精细引脚电连接、另一端与所述精细连线电连接；所述芯片引脚与所述精细连线之间的间距大于所述精细导电颗粒的高度，所述芯片引脚和所述精细连线不能通过所述导电颗粒电连接。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108933154B (zh) * 2017-05-26 2021-04-27 京东方科技集团股份有限公司 有机发光二极管显示基板的制备方法、显示基板及显示装置
US11197384B1 (en) * 2020-06-29 2021-12-07 Quanta Computer Inc. Tool-less latch system for a node sled

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1835229A (zh) * 2005-03-16 2006-09-20 索尼株式会社 半导体器件和制造半导体器件的方法
CN104471708A (zh) * 2012-02-08 2015-03-25 吉林克斯公司 具有多个插入件的堆叠裸片组件
WO2016073790A1 (en) * 2014-11-07 2016-05-12 Qualcomm Incorporated Integrated device package comprising silicon bridge in an encapsulation layer

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831355B2 (en) * 2002-12-04 2004-12-14 Minilogic Device Corporation Ltd. Flip-chip sub-assembly, methods of making same and device including same
JP3879853B2 (ja) * 2003-10-10 2007-02-14 セイコーエプソン株式会社 半導体装置、回路基板及び電子機器
US7268012B2 (en) * 2004-08-31 2007-09-11 Micron Technology, Inc. Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
FI122128B (fi) * 2005-06-16 2011-08-31 Imbera Electronics Oy Menetelmä piirilevyrakenteen valmistamiseksi
JP2012124333A (ja) * 2010-12-08 2012-06-28 Sharp Corp 半導体装置および半導体装置の製造方法
CN202210519U (zh) * 2011-10-08 2012-05-02 高庄 提高单位面积引脚量的芯片尺寸封装csp集成电路芯片
US9059179B2 (en) * 2011-12-28 2015-06-16 Broadcom Corporation Semiconductor package with a bridge interposer
US8704364B2 (en) 2012-02-08 2014-04-22 Xilinx, Inc. Reducing stress in multi-die integrated circuit structures
JP5931547B2 (ja) * 2012-03-30 2016-06-08 イビデン株式会社 配線板及びその製造方法
US8946900B2 (en) * 2012-10-31 2015-02-03 Intel Corporation X-line routing for dense multi-chip-package interconnects
US20140131854A1 (en) * 2012-11-13 2014-05-15 Lsi Corporation Multi-chip module connection by way of bridging blocks
US9236366B2 (en) * 2012-12-20 2016-01-12 Intel Corporation High density organic bridge device and method
US8901748B2 (en) * 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US9070644B2 (en) * 2013-03-15 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
US9646894B2 (en) * 2013-03-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
US10037946B2 (en) * 2016-02-05 2018-07-31 Dyi-chung Hu Package structure having embedded bonding film and manufacturing method thereof
KR102632563B1 (ko) * 2016-08-05 2024-02-02 삼성전자주식회사 반도체 패키지
US10510721B2 (en) * 2017-08-11 2019-12-17 Advanced Micro Devices, Inc. Molded chip combination
US11335663B2 (en) * 2017-12-29 2022-05-17 Intel Corporation Microelectronic assemblies

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1835229A (zh) * 2005-03-16 2006-09-20 索尼株式会社 半导体器件和制造半导体器件的方法
CN104471708A (zh) * 2012-02-08 2015-03-25 吉林克斯公司 具有多个插入件的堆叠裸片组件
WO2016073790A1 (en) * 2014-11-07 2016-05-12 Qualcomm Incorporated Integrated device package comprising silicon bridge in an encapsulation layer

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