WO2018098922A1 - 芯片连线方法及结构 - Google Patents

芯片连线方法及结构 Download PDF

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Publication number
WO2018098922A1
WO2018098922A1 PCT/CN2017/076430 CN2017076430W WO2018098922A1 WO 2018098922 A1 WO2018098922 A1 WO 2018098922A1 CN 2017076430 W CN2017076430 W CN 2017076430W WO 2018098922 A1 WO2018098922 A1 WO 2018098922A1
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Prior art keywords
chip
substrate
connection
hole
conductive layer
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PCT/CN2017/076430
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English (en)
French (fr)
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胡川
刘俊军
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深圳修远电子科技有限公司
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Priority to CN201780070448.2A priority Critical patent/CN109937614B/zh
Priority to US16/465,059 priority patent/US10847496B2/en
Publication of WO2018098922A1 publication Critical patent/WO2018098922A1/zh

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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32235—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a via metallisation of the item
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/8301—Cleaning the layer connector, e.g. oxide removal step, desmearing
    • H01L2224/83013—Plasma cleaning
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/8303—Reshaping the layer connector in the bonding apparatus, e.g. flattening the layer connector
    • H01L2224/83031—Reshaping the layer connector in the bonding apparatus, e.g. flattening the layer connector by chemical means, e.g. etching, anodisation
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/8303—Reshaping the layer connector in the bonding apparatus, e.g. flattening the layer connector
    • H01L2224/83035—Reshaping the layer connector in the bonding apparatus, e.g. flattening the layer connector by heating means
    • H01L2224/83039—Reshaping the layer connector in the bonding apparatus, e.g. flattening the layer connector by heating means using a laser
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate

Definitions

  • the invention belongs to the field of electronics, and in particular relates to a chip connection method and structure.
  • a chip In a conventional integrated circuit system, a chip is separately packaged and then mounted on a circuit board together with other electronic components.
  • various materials By connecting to the circuit port of the substrate by bonding or flip-chip, and then connecting to the circuit board, various materials are used in a large amount, the process is complicated, the production cost is high, and it is easy to use a large number of materials with different characteristics. A variety of thermomechanical stresses are induced at the interface of each material.
  • inter-chip data communication and circuit connections between the chip and other electronic components need to pass through the chip pins and electronic device device pins as well as the circuitry inside the board. There must be sufficient space between the chips and between the chips and other electronic components, and the geometry of the entire system is constrained and cannot be sufficiently miniaturized.
  • connection density is limited by the spacing between the chip pins and does not make the chip pins more dense.
  • the present invention overcomes the defects of the prior art, and provides a chip connection method and a chip connection structure.
  • the connection bypasses the occlusion of the chip pins, and can obtain high-density chip pins and connections, and improve the chip.
  • the number of connected nodes increases the data transfer speed of the chip.
  • a chip connection method includes: a substrate is provided with a first connection line and a second connection line, wherein a distance between the first connection line and the chip is smaller than the second connection line in a thickness direction of the substrate a chip is disposed on a top surface of the substrate, the chip is provided with at least two chip pins, the substrate is provided with a second through hole, and the second through hole and the first Corresponding to the two wires, the second through hole is provided with a second conductive layer; wherein at least one of the chip pins is electrically connected to the first wire, and at least one The chip pins correspond to the first openings of the second vias, and the second conductive layer electrically connects the chip pins to the second wires.
  • the substrate is provided with a third connection and a third through hole, and the distance between the third connection and the chip is greater or smaller than the second connection in the thickness direction of the substrate a distance between the line and the chip, a third conductive layer is disposed in the third through hole, and the second connection is at least one, wherein one end of the at least one second connection line and the second through hole Corresponding to and electrically connected to the chip lead through the second conductive layer, the other end corresponding to the third through hole and electrically connected to the third connection through the third conductive layer.
  • the second conductive layer is formed from the second through hole in the process of forming the second conductive layer in the second through hole through the second opening of the second through hole Two openings are fed into the second through hole.
  • the second conductive layer is a solder ball, or a solder paste, or a conductive paste; or the second conductive layer is a metal layer, and the method is performed by immersion gold, sputtering, or electroplating. Metal layer.
  • the conductive bonding material is disposed in the second through hole by screen printing.
  • an adhesive film is disposed between the chip and the substrate, and the adhesive film adheres the chip component to the substrate.
  • an additional via is formed in the adhesive film by laser sintering, plasma cleaning, or chemical solvent through the second opening of the second via, the additional via will be the second The through hole is butted to the chip lead, and the second conductive layer protrudes into the additional through hole.
  • a protective layer is disposed on an inner wall of the second through hole, and the protective layer is used to protect the substrate when the additional through hole is formed.
  • a first through hole is disposed on the substrate, the first connecting line is corresponding to the first through hole, and the first through hole is provided with a first conductive layer, the first A conductive layer electrically connects the first wire to the chip pins.
  • the substrate is a flexible circuit board; or the substrate comprises at least two layers of flexible circuit boards stacked.
  • a chip connection structure includes: a chip disposed on a top surface of the substrate, the substrate being provided with a first connection line and a second connection line, wherein the first connection line and the first connection line are in a thickness direction of the substrate The distance between the chip is smaller than the distance between the second wire and the chip, the chip is provided with at least two chip pins, the substrate is provided with a second through hole, and the second through hole and the second Corresponding to the connection, the second through hole is provided with a second conductive layer; wherein at least one of the chip pins is electrically connected to the first wire, and at least one of the chip pins and the first The two vias correspond to each other, and the first conductive layer electrically connects the chip pins to the second wires.
  • a first through hole is disposed on the substrate, the first connecting line is corresponding to the first through hole, and the first through hole is provided with a first conductive layer, the first A conductive layer electrically connects the first wire to the chip pins.
  • the substrate is provided with a third connection and a third through hole, and a third conductive layer is disposed in the third through hole, and the third connection is in a thickness direction of the substrate
  • the distance from the chip is greater than the distance between the second wire and the chip
  • the second wire is at least one, wherein one end of at least one of the second wires corresponds to the first through hole, The other end corresponds to the second through hole, one end of the second connection is electrically connected to the chip pin through the second conductive layer, and the other end is connected to the third connection through the third conductive layer Line electrical connection.
  • the chip, the first connection, and the third connection are disposed on a top surface of the substrate, and the second connection is disposed on a bottom surface of the substrate.
  • the chip and the first connection are disposed on a top surface of the substrate, and the second connection is disposed on a bottom surface of the substrate.
  • the substrate is a flexible circuit board; or the substrate comprises at least two layers of flexible circuit boards stacked.
  • a chip connecting method comprising: the substrate is provided with a first connection line and a second connection line, and the first connection line and the second connection line may be disposed on a top surface of the substrate, a bottom surface of the substrate, or embedded In the interior of the substrate, the distance between the first wire and the chip is smaller than the distance between the second wire and the chip in the thickness direction of the substrate, similar to layering the first on the substrate Connection and second connection, making the first connection
  • the second line of the line does not interfere with each other, and the first line and the second line are divided into two "layers" in the thickness direction of the substrate, as shown in FIG. 14-15.
  • the chip is placed on the top surface of the substrate, and the chip can be bonded to the substrate or not.
  • the chip is provided with at least two chip pins, and the chip pins of the chip include, but are not limited to, a connection portion drawn inside the chip and an expansion pin electrically connected to the connection portion, as long as the chip pin can be electrically connected to the chip.
  • the substrate is provided with a second through hole corresponding to the second connecting hole, a second conductive layer is disposed in the second through hole, and a portion of the second connecting line is located in the second through hole Adjacent to the opening or extending into the second through hole, the second wire can be electrically connected to the second conductive layer.
  • the chip pins is electrically connected to the first wire, and at least one of the chip pins corresponds to a first opening of the second through hole, and the first conductive layer is The chip pins are electrically connected to the second wire.
  • the chip pin is connected to the second wire through the second conductive layer in the second via hole, and the second conductive layer is disposed from the second opening of the second via hole, so as to avoid the chip-to-chip pin
  • the occlusion enables the second through hole and the chip pin to be accurately positioned, thereby improving the connection precision, and the second through hole can be mass-produced, and a plurality of chips are set in batches to greatly improve the production efficiency; the second conductive layer is disposed in the second pass In the hole, without occupying extra space, the overall volume after packaging can be greatly reduced.
  • the basic whole remains flexible after the completion of the above steps, which is a great advantage.
  • the chip is mounted on the top surface of the substrate, and the area covered by the chip on the substrate is referred to as a "shadow area", the pins of the chip are located in the shadow area, and the chip pins are "escape" from the shadow area to be externally connected.
  • all the wires are disposed on the top surface of the substrate, and the chip pins can only escape from the top surface of the substrate.
  • the wires need to pass through the gap between the chip pins, and the chip pins are to be avoided, resulting in chip leads.
  • Sufficient clearance is required between the feet for the wires to pass through, as shown in Figure 17, which limits the number of wires and does not allow for more wires.
  • the chip pins near the edge of the chip can be taken out by the wires, but there is no gap, and the wires can be connected to the chip pins near the middle of the chip, so the traditional connection method is limited.
  • the chip pins respectively escape through the first connection line and the second connection line and the first connection line and the second connection line are in different thickness layers in the thickness direction of the substrate, and the two do not interfere with each other.
  • the chip pins that escape through the second connection in the shaded area, first escape through the second conductor layer in the second through hole to the layer where the second connection is located, and then escape from the second connection, so that Some of the chip pins escape to the second connection and are externally connected from the layer where the second connection is located.
  • the number of connections that escape from the top surface of the substrate is reduced, and more connections can be arranged, and even if appropriate
  • the line width of the Dalian line will not reduce the number of connections.
  • the second connection does not need to pass through the gap between the chip pins, and the chip pins escape from the dense chip pin surrounding thereof through the second through hole to the layer where the second connection is located, avoiding the multiple chip pins.
  • the mutual blocking can obtain higher density connection.
  • higher density chip pins can be set, and the chip can obtain higher density connection nodes and improve the data transmission speed of the chip.
  • the thickness direction of the substrate it is not limited to being divided into two “layers”. According to actual winding requirements, three “layers”, four “layers” or more “layers” may be provided, so that the chip pins can pass respectively. More “layers” to escape, making the connection settings more flexible, you can get more connection nodes, connecting lines.
  • the substrate is provided with a third connection and a third through hole, and a third conductive layer is disposed in the third through hole, and the third connection and the chip are in a thickness direction of the substrate
  • the distance is greater than or smaller than the distance between the second connection and the chip
  • the second connection is not in the same "layer” as the third connection
  • the third connection may be in the same "layer” as the first connection, It may not be in the same "layer”.
  • the second connection and the third connection of the first connection form three "layers".
  • the second connection is at least one, wherein one end of at least one of the second lines corresponds to the second through hole and passes through the second conductive
  • the layer is electrically connected to the chip pin, and the other end corresponds to the third via hole and is electrically connected to the third connection through the third conductive layer.
  • the chip pin and the third wire may be electrically connected through the second wire, and the chip pin escapes from the dense chip pin to the layer where the second wire is located through the second through hole, and escapes through the third through hole
  • the layer where the third connection is located, and the level of the third connection and the second connection are designed as needed.
  • the pattern of the traces can help the chip pins escape as much as possible to obtain the connection, thereby increasing the density of the chip pins, increasing the density of the connection nodes of the chip, and thereby increasing the data transfer speed of the chip.
  • the chip, the first connection, and the third connection are disposed on a top surface of the substrate, and the second connection is disposed on a bottom surface of the substrate, on a top surface of the substrate, and The bottom surface is coated with a metal layer, and then the first connection, the second connection, and the third connection are simultaneously formed by using a photoresist to improve production efficiency.
  • the conductive bonding material is a solder ball, or a solder paste, or a conductive paste, or a conductive metal paste.
  • One or more combinations may be selected according to the needs of the process or the material of the substrate, the size of the inner wall of the second through hole, and the nature of the surface material.
  • the process of placing a conductive bonding material to form a conductive connecting channel may use common soldering processes, including surface cleaning, flux spraying, precision placement of solder balls and heat treatment using a ball machine, and more special chemical surfaces. Cleaning, surface treatment, precision spraying of solder paste, conductive paste or conductive metal paste, followed by heat treatment to form mechanical and electrical connections.
  • the conductive bonding material is disposed in the second through hole by screen printing during the process of forming the second conductive layer in the second through hole through the second opening of the second through hole.
  • the equipment is universal and can be synchronized with the production of the circuit layer, saving process flow and further reducing costs.
  • An adhesive film is disposed between the chip and the substrate, and the adhesive film adheres the chip component to the substrate. By attaching the chip to the substrate by sticking the adhesive film, the chip can be fixed on the substrate, which saves steps, improves efficiency, and reduces cost.
  • the adhesive film can be insulated such that the chip pins can be electrically insulated from the wires on the top surface of the substrate even if wiring is provided on the top surface of the substrate.
  • a protective layer is disposed on the inner wall of the second through hole, and the protective layer is used to protect the substrate when the additional through hole is formed.
  • the additional via hole can be made, but is not limited to the process of using chemical etching or drilling. In this case, it is required to pass through the second through hole, which may damage the inner wall of the second through hole, thereby causing damage to the substrate and protecting The layer can protect the inner wall of the second through hole from damage.
  • the protective layer may be a material that facilitates electrical connection of the second conductive layer, and the protective layer may be in electrical contact with the second wiring to facilitate electrical connection between the second wiring and the second conductive layer.
  • the protective layer may be a metal film which is pre-sputtered or evaporated on the inner wall of the second via hole, so that the material of the second via inner wall is protected from being exposed to the etching solvent during the chemical etching process.
  • an ion, and such a thin metal layer can also increase the conductivity of the second conductive layer that is subsequently plated in the second via.
  • the first through hole is disposed on the substrate, the first connecting line is corresponding to the first through hole, and the first conductive layer is provided with a first conductive layer, and the first conductive layer is disposed
  • the first connection is electrically connected to the chip pins.
  • the second through hole constitutes a "hole connection" by electrically connecting the chip pin and the second wire, and the chip pin and the first wire may be electrically connected through the first through hole in a manner similar to the foregoing "hole connection". connection.
  • the chip pins are respectively electrically connected to the first connection and the second connection through the first through hole and the second through hole, and the first connection and the second connection are formed in the thickness direction of the substrate.
  • the electrical connection allows more chip pins to escape from the surrounding of the chip pins for electrical connection, thereby increasing the density of the chip pins and increasing the speed of chip data transmission.
  • the substrate is a flexible circuit board; the connection of the chip pins is connected by means of “hole connection”, which can increase the density of the chip pins, thereby reducing the volume of the chip, and the first conductive layer and the second conductive layer.
  • the chip Located in the first through hole and the second through hole respectively, without occupying an extra volume, the chip can be between the substrates It is not even necessary to reserve a gap (but is not limited thereto, and a gap such as an adhesive layer may be provided as needed), and the overall thickness of the chip and the substrate may be reduced, when the substrate is a flexible circuit board or a multilayer flexible circuit board. It can maintain the overall flexibility and can be used in wearable devices and the like.
  • the substrate comprises at least two layers of flexible circuit boards, if two "layers" or more are provided, the first connection, the second connection, or other connection may be set first. Between two adjacent flexible circuit boards.
  • the chip and the first connection line are disposed on a top surface of the substrate, and the second connection line is disposed on a bottom surface of the substrate.
  • a metal layer is coated on the top surface and the bottom surface of the substrate, and then the first connection and the second connection are simultaneously formed by using a photoresist to improve production efficiency.
  • FIG. 1 is a first schematic diagram of a chip connection method according to an embodiment of the present invention.
  • FIG. 2 is a second schematic diagram of a chip connection method according to an embodiment of the present invention.
  • FIG. 3 is a third schematic diagram of a chip connection method according to an embodiment of the present invention.
  • FIG. 4 is a fourth schematic diagram of a chip connection method according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram 5 of a chip connection method according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram 1 of a method for connecting a chip according to an embodiment of the present invention.
  • FIG. 7 is a second schematic diagram of a method for connecting a chip according to an embodiment of the present invention.
  • FIG. 8 is a third schematic diagram of a method for connecting a chip according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram 4 of a method for connecting a chip according to an embodiment of the present invention.
  • FIG. 10 is a first schematic diagram of a three-chip connection method according to an embodiment of the present invention.
  • FIG. 11 is a second schematic diagram of a three-chip connection method according to an embodiment of the present invention.
  • FIG. 12 is a third schematic diagram of a three-chip connection method according to an embodiment of the present invention.
  • FIG. 13 is a fourth schematic diagram of a three-chip connection method according to an embodiment of the present invention.
  • FIG. 14 is a side view of a four-chip connection method according to an embodiment of the present invention.
  • 15 is a side view 2 of a four-chip connection method according to an embodiment of the present invention.
  • 16 is a top plan view of a four-chip connection method according to an embodiment of the present invention.
  • Figure 17 is a top plan view of a conventional wiring method according to a fourth embodiment of the present invention.
  • the integrated package circuit includes: a component 200 and a substrate 100.
  • the component 200 is mounted on the top surface of the substrate 100.
  • the top surface and the bottom surface of the substrate 100 are respectively provided with circuit layers 110a and 110b.
  • the insulating medium 300 is disposed between the component 200 and the substrate 100. (In this embodiment, the insulating medium 300 is simultaneously provided. Also a sticky film).
  • the component 200 is provided with device pins 210a, 210b, the device pins 210a, 210b are facing the substrate 100, the circuit layers 110a, 110b are provided with circuit pins, and the substrate 100 is provided with connection vias 120a, 120b, and the connection vias 120a, 120b Docking with the circuit pins, the first opening 120c connecting the through holes 120a, 120b abuts the device pins 210a, 210b, the second opening 120d connecting the through holes 120a, 120b is an operation window, and the insulating medium 300 (adhesive film) is provided There are additional through holes communicating with the first openings 120c connecting the through holes 120a, 120b.
  • the connecting through holes 120a, 120b are provided with conductive layers 400a, 400b, and the conductive layers 400a, 400b extend into the additional through holes and the device.
  • Pins 210a, 210b are electrically connected.
  • the insulating medium 300 separates the component 200 from the substrate 100.
  • the insulating medium 300 adheresive film
  • the number of device pins 210a, 210b of the component 200 can be set as needed. When the device pins 210a, 210b of the component 200 can have more than two, some of the device pins 210a, 210b are through the integrated circuit package method of the present invention.
  • Substrate 100 or circuit layer 110a, The 110b connection, the insulating medium 300 can prevent additional device pins 210a, 210b from affecting the substrate 100 or circuit layers 110a, 110b.
  • the insulating medium 300 is also an adhesive film, and the insulating medium 300 (adhesive film) bonds the component 200 to the substrate 100.
  • the component 200 is placed on the substrate 100 by means of bonding, and the component 200 is placed on the substrate 100 to fix the component 200 to the substrate 100, thereby saving steps, improving efficiency, and reducing cost.
  • the insulating medium 300 only functions as the isolation component 200 and the substrate 100.
  • the component 200 is fixed to the substrate 100 by another method, and the component 200 may be attached to the substrate 100 by using an adhesive film.
  • the adhesive film does not function to isolate the component 200 from the substrate 100.
  • the integrated circuit packaging method includes: as shown in FIG. 1 , the top surface and the bottom surface of the substrate 100 respectively have circuit layers 110a and 110b, the circuit layers 110a and 110b have circuit pins, and the circuit pins may be circuit layers.
  • the connection portion directly led out by 110a and 110b may be an extension pin electrically connected to the connection portion, and may be electrically connected to the circuit layers 110a and 110b through circuit pins.
  • the device pins 210a, 210b of the component 200 include, but are not limited to, a connection portion drawn inside the component 200 and an extension pin electrically connected to the connection portion, as long as the device pins 210a, 210b can be electrically connected to the component 200.
  • the device pins 210a, 210b are interfaced with the first openings 120c of the connection vias 120a, 120b.
  • one surface of the device 200 on which the device leads 210a and 210b are provided is coated with an adhesive film (not limited to this embodiment, the adhesive film can be applied to the substrate 100), and the component 200 has device pins.
  • One side of 210a and 210b faces the substrate 100, and the component 200 is placed on the substrate 100.
  • the adhesive film mounts the component 200 on the substrate 100.
  • the adhesive film is at the same time the insulating medium 300, and is not limited to the embodiment, and the adhesive film bonding component 200 may not be used.
  • connection vias 120a, 120b are formed on the substrate 100, and the device pins 210a, 210b are butted to the first openings 120c of the connection vias 120a, 120b, and the second vias 120a, 120b are connected.
  • the opening 120d is configured to form the conductive layers 400a, 400b in the connection vias 120a, 120b.
  • the structure of the first opening 120c and the second opening 120d is as shown in FIG. 8.
  • the device pins 210a, 210b are located on the top surface of the substrate 100 through the connection.
  • the second opening 120d of the through holes 120a, 120b can electrically connect the component 200 from the bottom surface of the substrate 100 to the circuit layers 110a, 110b, and evade shielding of the device pins 210a, 210b from above.
  • By connecting the second opening 120d of the through holes 120a, 120b use Laser firing, plasma cleaning, or chemical solvent creates additional vias in the adhesive film, and additional vias interface the vias 120a, 120b with the device leads 210a, 210b to prevent the adhesive film from blocking the device leads 210a, 210b, Electrical connections of conductive layers 400a, 400b, and circuit pins.
  • conductive layers 400a, 400b are formed in the connection vias 120a, 120b through the second openings 120d connecting the via holes 120a, 120b, and the conductive layers 400a, 400b are projected into the additional via holes, and the conductive layers 400a, 400b Device pins 210a, 210b are electrically coupled to circuit pins.
  • Packaging according to the above method can reduce the cost of the integrated circuit package and save packaging time. Moreover, the overall thickness of the substrate 100 and the component 200 is reduced, and even no gap is required between the substrate 100 and the component 200 (in principle, no gap is required, but other components can be disposed on the substrate 100 and the component 200 as needed. Material); no need for heat welding steps, especially for ultra-thin components 200 (such as ultra-thin chips), flexible circuit board packaging, can avoid the overall thermo-mechanical stress distribution of the system caused by large temperature changes, and Impact on the performance of component 200.
  • an encapsulation layer is disposed on the substrate 100, and the component 200 is packaged by the encapsulation layer and the substrate 100.
  • the conductive layers 400a and 400b are formed.
  • an encapsulation layer is disposed on the substrate 100, and the two components 200 are packaged by the encapsulation layer and the substrate 100.
  • the component 200 is encapsulated by the encapsulation layer, the component 200 can be protected, and the encapsulation layer can cover the substrate 100.
  • the encapsulation layer can be simultaneously disposed on the top surface and the bottom surface of the substrate 100 to protect the circuit layer 110a on the substrate 100 and the substrate 100, 110b, to avoid the impact of environmental factors. At the same time, the encapsulation layer also secures the component 200 to the substrate 100 without the need for additional programming to secure the component 200. In addition, the cured encapsulation layer also becomes a better support plate for the entire system, and can be flipped to perform subsequent process on the substrate.
  • connection vias 120a, 120b are mated with the device pins 210a, 210b, and the device pins 210a, 210b are at least partially located adjacent to the first opening 120c of the connection vias 120a, 120b or deep into the vias 120a, 120b, such that The conductive layers 400a, 400b can be electrically coupled to the device pins 210a, 210b; the circuit pins are mated with the connection vias 120a, 120b, the circuit pins being at least partially located adjacent the first opening 120c of the connection vias 120a, 120b, or a second The vicinity of the opening 120d or the vicinity of the inner wall of the connecting vias 120a, 120b, so that the conductive layers 400a, 400b can be electrically connected to the circuit pins; the component 200 can It is a chip or electronic component (including but not limited to resistors, capacitors) or other electronic devices (including but not limited to antennas). The component 200 may be fixed to the substrate 100 through the connection vias 120a,
  • the conductive layers 400a, 400b are formed by electroplating, and the finally formed conductive layer 400a, 400b Referring to Figures 4 and 9, good electrical conductivity can be obtained, and electroplating can control the thickness of the conductive layers 400a, 400b to obtain desired electrical conductivity.
  • the present invention is not limited thereto, and the conductive bonding material may be formed from the connection via 120a during the process of forming the conductive layers 400a and 400b in the connection vias 120a and 120b through the second openings 120d connecting the via holes 120a and 120b.
  • the second opening 120d of 120b is fed into the connection vias 120a, 120b, and the conductive bonding material is bonded to the inner walls of the connection vias 120a, 120b and the device pins 210a, 210b to form the conductive layers 400a, 400b.
  • the conductive bonding material By feeding the conductive bonding material from the second opening 120d, the back surface of the substrate 100 can be operated without being disturbed by the component 200, and the conductive bonding material is adhered to the connection via 120a by bonding.
  • the inner wall of 120b and the device pins 210a, 210b of the component 200 can be mechanically and electrically connected at the same time after proper heating or chemical treatment, and also ensure stable conductive connection performance.
  • the conductive bonding material is a solder ball, or a solder paste, or a conductive paste, or a conductive metal paste.
  • the finally formed conductive layers 400a, 400b can be referred to FIG. 13 and can be connected to the inner wall of the through holes 120a, 120b according to the process requirements or the material of the substrate 100. Nature, choose one or more combinations.
  • a conductive bonding material is provided in the connection via holes 120a, 120b by screen printing. Screen printing is a common manufacturing method of the circuit layers 110a and 110b.
  • the conductive layers 400a and 400b are formed by screen printing.
  • the device is universal and can be synchronized with the fabrication of the circuit layers 110a and 110b, which saves the process flow and further reduces the cost.
  • a plurality of components 200 can be simultaneously mounted on a large panel of a large area, and the batch processing on the large panel further reduces the cost and saves the packaging time.
  • a plurality of sets of components 200 are arranged on a carrier by using a carrier of a large flat plate, the carrier is covered on the top surface of the substrate 100, and the component 200 is attached to the substrate 100 using an adhesive film to separate the carrier from the component 200.
  • the substrate 100 is cut into a plurality of daughter boards according to a predetermined grouping, and each of the daughter boards corresponds to one Group component 200, each daughter board is independent. In this way, packaging operations can be performed in large quantities, and production efficiency is greatly improved.
  • the adhesive film can be an insulating material at the same time
  • the top surface and the bottom surface of the substrate 100 are respectively provided with circuit layers 110a and 110b, and the chip is electrically connected to the circuit layers 110a and 110b at the same time.
  • the circuit layer 110a is embedded in the substrate 100.
  • the device pins 210a, 210b are electrically connected to the circuit layers 110a, 110b; or the top surface of the substrate 100 is provided with circuit layers 110a, 110b, or / and the bottom surface of the substrate 100 is provided with circuit layers 110a, 110b, or /
  • the circuit board 110 is provided with circuit layers 110a, 110b, and the device pins 210a, 210b are at least two, one of the device pins 210a, 210b is electrically connected to at least one of the circuit layers 110a, 110b, and another device pin 210a 210b is electrically connected to at least one of the remaining circuit layers 110a, 110b.
  • the substrate 100 is provided with two or more circuit layers 110a and 110b.
  • the component 200 is electrically connected to at least
  • the substrate 100 may be a flexible circuit board; or the substrate 100 may include at least two layers of flexible circuit boards.
  • the component 200 is mounted on the substrate 100 by the integrated circuit packaging method, and the electrical connection between the component 200 and the circuit layers 110a and 110b on the substrate 100 is realized.
  • the overall thickness of the component 200 and the substrate 100 is small, and the overall flexibility can be maintained. Can be used for wearable devices, etc.
  • the component 200 is a chip or an electronic component.
  • the integrated circuit packaging method is suitable for packaging of chips or electronic components, including but not limited to independent resistors, capacitors, inductors, diodes, or transistors, including but not limited to die, wafer, or packaged integrated chip . Chips or electronic components can be packaged using the same equipment and process flow, reducing costs.
  • the component 200 may be at least two.
  • the integrated circuit packaging method is applicable to two or more components 200. Further, two or more components 200 can be simultaneously operated, and the above components 200 are mounted on the substrate 100 to implement the component 200 and the circuit layer 110a. 110b electrical connection, improve efficiency, drop low cost.
  • the component 200 is at least two, it may be that at least two components 200 include at least one chip and at least one electronic component. Chips and electronic components can be packaged at the same time to increase efficiency and reduce costs.
  • an encapsulation layer is provided on the substrate 100, it is optional to package a single component 200 or package two or more components 200.
  • the purpose of the encapsulation layer is mainly to protect the component 200 from external environmental factors such as the influence of water vapor and electromagnetic radiation on the electrical properties of the component. At the same time, it also fixes the relative positions of the plurality of components 200 on the substrate 100 to ensure the stability of the electrical connection.
  • the encapsulation layer is further used as a support plate, so that we can then conveniently fabricate the conductive layer on the inner wall of the connection via hole on the substrate 100.
  • two or more encapsulation layers may be disposed on one substrate 100, and the encapsulation layers may have a gap between each other to provide a larger curvature, so that the whole of the substrate 100, the component 200, and the encapsulation layer is more flexible.
  • the integrated package circuit can maintain such flexibility, so that the integrated package circuit can be applied to, for example, a wearable device that needs to remain flexible. occasion.
  • the circuit layers 110a, 110b are functional circuits, and the circuit layers 110a, 110b have certain electronic functions; or the circuit layers 110a, 110b themselves constitute electronic components, including but not limited to antennas.
  • the circuit layers 110a, 110b of the integrated package circuit structure have a wide range of applications, and can realize integration of various functions.
  • an auxiliary layer may be formed on the inner walls of the connection vias 120a, 120b through the second opening 120d before the conductive layers 400a, 400b are formed, the auxiliary layer is electrically connected to the circuit layers 110a, 110b, and then electrically conductive is formed on the auxiliary layer.
  • the layers 400a, 400b, the auxiliary layer is used to assist in the fabrication of the conductive layers 400a, 400b, such that the conductive layers 400a, 400b are better electrically connected to the device pins 210a, 210b, the circuit pins, or better attached to the connection vias 120a , the inner wall of 120b.
  • protective layers 121a and 121b are provided on the inner walls of the connection vias 120a and 120b, and the protective layers 121a and 121b are used to protect the substrate 100 when the additional via holes are formed.
  • the additional via holes may be formed by using, but not limited to, a chemical etching or a drilling process. In this case, it is necessary to pass through the connection via holes 120a, 120b, which may damage the material of the inner wall of the connection via holes 120a, 120b, and thus the substrate 100.
  • the circuit layers 110a, 110b cause damage, and the protective layers 121a, 121b can protect the inner walls of the connection vias 120a, 120b from damage.
  • the protective layers 121a, 121b may be materials that facilitate the electrical connection of the conductive layers 400a, 400b, at this time, the protective layers 121a, 121b It can be in contact with the circuit pins to facilitate electrical connection of the circuit pins to the conductive layers 400a, 400b.
  • the inner walls of the connecting through holes 120a, 120b are provided with protective layers 121a, 121b, and the protective layers 121a, 121b are also auxiliary layers, and the protective layers 121a, 121b (auxiliary layers) are not shown in the drawing, referring to FIG. To 13.
  • the protective layers 121a and 121b (auxiliary layers) are made of the same material as the circuit layers 110a and 110b.
  • the circuit layers 110a and 110b are made of copper
  • the protective layers 121a and 121b (auxiliary layers) are also made of copper. Refers to electrical connection performance.
  • the present invention is not limited to this embodiment, and other materials may be used as needed, and the protective layers 121a, 121b or the auxiliary layers for auxiliary electrical connection may be separately provided.
  • the protective layers 121a, 121b (auxiliary layers) are electrically connected to the circuit layers 110a, 110b, and the conductive layers 400a, 400b electrically connect the device pins 210a, 210b and the circuit pins.
  • the protective layers 121a and 121b are directly electrically connected to the circuit pins, and the electrical connection effect is good, and the circuit pins can be extended to reduce the volume of the conductive layers 400a and 400b, which is advantageous for the fabrication of the conductive layers 400a and 400b, and is also advantageous for the fabrication of the conductive layers 400a and 400b. cut costs.
  • the conductive layers 400a and 400b may be formed by electroplating, and an auxiliary layer may be formed by a sputtering or vapor deposition process before electroplating.
  • the sputtered or vapor-deposited auxiliary layer can be better electrically connected to the circuit pins, and the electroplated conductive layers 400a, 400b are attached to the auxiliary layer, which can be better plated on the one hand, and can be better realized by the auxiliary layer on the other hand.
  • the conductive layers 400a, 400b are electrically connected to the circuit pins.
  • sputtering, vapor deposition, and electroplating can simultaneously perform all of the components 200 on the substrate 100 to improve efficiency.
  • the circuit layers 110a and 110b are formed on the substrate 100 in advance, but the circuit layers 110a and 110b may be formed on the substrate 100 during the integrated circuit package.
  • the circuit layers 110a and 110b may be formed on the substrate 100.
  • the mold layer has a mold groove having a contour similar to that of the circuit layers 110a and 110b. After the connection via holes 120a and 120b are formed, the circuit layers 110a and 110b are formed in the mold groove while the conductive layers 400a and 400b are formed.
  • the conductive layers 400a and 400b and the circuit layers 110a and 110b are made of the same material, and while plating the conductive layers 400a and 400b, a conductive layer is also plated in the mold groove and the surface of the release layer.
  • the substrate surface circuit layers 110a, 110b can then be formed by removing the release layer and the conductive layer on the surface thereof.
  • the process of forming the conductive layers 400a, 400b by electroplating is also included in Prior to electroplating, an auxiliary layer on the surface of the device leads 210b and 210c is formed in the connection vias 120a and 120b by a sputtering or evaporation process, and then electroplated.
  • the sputtered or evaporated auxiliary layer is better electrically connected to the circuit leads, and the plated conductive layers 400a, 400b are attached to the auxiliary layer.
  • Sputtering or vapor deposition of the auxiliary layer on the one hand can improve the quality of the plating, and on the other hand, can better achieve the electrical connection between the conductive layers 400a, 400b and the circuit pins.
  • connection vias 120a and 120b are formed on the substrate 100 in advance, and the component 200 is mounted on the substrate 100.
  • the specific steps are: the substrate 100 is provided with prefabricated connection vias 120a, 120b.
  • the component 200 is placed on the substrate 100, so that the device pin 210a of the component 200 is provided.
  • the second opening 120c is connected to the first opening 120c of the connecting through hole 120a, 120b.
  • an insulating medium 300 is disposed between the component 200 and the substrate 100 (in this embodiment, the insulating medium 300 is also The adhesive film has the function of isolating the component 200 and the substrate 100 and bonding the component 200 to the substrate 100.
  • An additional via hole is formed in the insulating medium 300, and the via hole and the device pin 210a are added.
  • the first openings 120c of the connection vias 120a and 120b are butted.
  • the conductive layers 400a and 400b are formed in the connection vias 120a and 120b.
  • the conductive layers 400a and 400b are deep-attached to the device pins. 210a, 210b and the circuit pins are electrically connected, as shown in FIG.
  • the device pins 210a, 210b are butted to the first openings 120c of the connection vias 120a, 120b, and are not necessarily strictly aligned as long as the device pins 210a, 210b can be connected through the additional vias and the connection vias 120a, 120b.
  • the conductive layers 400a and 400b may be electrically connected.
  • the protective layers 121a, 121b are electrically connected to the circuit layers 110a, 110b; as shown in FIG. 11, the component 200 is placed on the substrate 100, and the adhesive film (insulation) The medium 300) is attached to the substrate 100; as shown in FIG. 12, an auxiliary via is formed in the adhesive film (insulating material); as shown in FIG. 13, a conductive layer 400a is formed in the connecting vias 120a, 120b, 400b, conductive layers 400a, 400b electrically connect device pins 210a, 210b and circuit pins.
  • the auxiliary layer (protective layers 121a, 121b) is directly electrically connected to the circuit pins, and the electrical connection effect is good and can be extended
  • the circuit pins which reduce the volume of the conductive layers 400a, 400b, facilitate the fabrication of the conductive layers 400a, 400b and also reduce the cost.
  • the substrate 100 includes at least two substrates 101, at least two of which are stacked, and the top surface of the substrate 101 is provided with the circuit layers 110a, 110b, or/and the substrate 101.
  • the bottom surface is provided with the circuit layers 110a, 110b, at least one of the substrates 101 is provided with a via hole, and at least two of the circuit layers 110a, 110b are electrically connected through the via holes. Extend the range of components 200 to achieve more circuit connections in a smaller circuit volume.
  • a conductive connection port 500 electrically connected to the conductive layers 400a, 400b is formed on the bottom surface of the substrate 100.
  • the conductive connection port 500 is a solder ball. Dot matrix, or connect a dot matrix, or a metal pin grid.
  • the device pin 210c of the component 200 is connected to the conductive connection port 500 of the bottom surface of the substrate 100, which can greatly expand the connection space of the device pin 201c, and facilitate the connection of the component 200 to an external circuit.
  • the component 200 is made as small as possible, and the space for the external connection of the device pin 210c is small, through the conductive connection vias 400, 400a, 400b and the substrate bottom or top surface or substrate interior.
  • the circuit layers 110a, 110b, the pins 210c of the component can extend to the external conductive connection port 500 on the bottom surface of the substrate, which greatly expands the connection space of the components.
  • the direct benefit of this design is that the access and access data communication channels can be set at a higher density, while increasing the communication bandwidth and transmission speed.
  • the components are chips and the device pins are chip pins.
  • the substrate is provided with a plurality of connecting through holes.
  • the connecting through holes are respectively referred to as a first through hole and a second through hole, and each connecting through hole is provided with a corresponding conductive layer, which is simple and simple to describe.
  • the first conductive layer is provided in the first through hole
  • the second conductive layer is disposed in the second through hole
  • the third conductive layer is disposed in the third through hole.
  • the first circuit layer and the second circuit layer may be connected, and the wires are electrically connected or not connected to the chip or the component.
  • the circuit layer includes a plurality of wires, which are clear and concise for description.
  • the connection is recorded as the first connection, the second connection, and the third connection.
  • the chip 201 is provided with chip pins 211a, 211b, and 211c.
  • the top surface of the substrate 100 is provided with a first connection line 111b and a third connection line 111d, and the bottom surface of the substrate is provided with a second connection line 111a, 111c. .
  • the first connection line 111b and the third connection line 111d are disposed on the top surface of the substrate 100, and the second connection lines 111a and 111c are disposed on the bottom surface of the substrate 100.
  • the thickness direction of the substrate 100 is The distance between the first connection 111b and the third connection 111d and the chip 201 is smaller than the distance between the second connection 111a, 111c and the chip.
  • the first connection 111b, the second connection 111a, 111c, and the third connection 111d may be embedded in the inside of the substrate 100 as long as the first connection 111b is satisfied in the thickness direction of the substrate 100.
  • the distance from the chip 201 is smaller than the distance between the second wire and the chip 201. At this time, the first wire 111b and the second wire 111a, 111c form two "layers" of wires in the thickness direction of the substrate 100.
  • a layer of adhesive film 300 is provided on the top surface of the substrate 100, and the chip is bonded to the top surface of the substrate 100 through the adhesive film 300.
  • the adhesive film 300 may be insulated such that the chip leads 211a, 211b, and 211c can be electrically insulated from the wiring of the top surface of the substrate 100 even if wiring is provided on the top surface of the substrate 100.
  • a first through hole 121b is disposed on the substrate 100.
  • the first connection line 111b corresponds to the first through hole 121b.
  • the first through hole 121b is provided with a first conductive layer 401b.
  • the first conductive layer 401b connects the first connection line 111b with The chip pins 211b are electrically connected.
  • the first conductive layer 401b is not shown in the drawing. Not limited to this embodiment, two or more chip pins 211b may be electrically connected to the first wiring 111b.
  • the substrate 100 is provided with second through holes 121a and 121c.
  • the second through holes 121a and 121c correspond to the second connecting lines 121a and 121c.
  • the second through holes 121a and 121c are provided with second conductive layers 401a and 401c. Portions of the wires 121a, 121c are located near the openings of the second through holes 121a, 121c or protrude into the second through holes 121a, 121c such that the second wires 121a, 121c can be electrically connected to the second conductive layers 401a, 401c.
  • the chip pin 211b is electrically connected to the first wire 111b, and the first conductive layer 401b leads the chip
  • the pin 211b is electrically connected to the first wire 121b;
  • the chip pins 211a, 211c correspond to the first openings of the second through holes 121a, 121c, and the second conductive layers 401a, 401c connect the chip pins 211a, 211c with the second
  • the wires 121a, 121c are electrically connected.
  • two or more chip pins may be electrically connected to the second wires 121a and 121c.
  • the substrate 100 is provided with a third connecting line 111d and a third through hole 121d.
  • the third through hole 121d is provided with a third conductive layer 401d.
  • the distance between the third connecting line 111d and the chip 201 is smaller than (
  • the third connection line 111d and the first connection line 111b are disposed on the top surface of the substrate 100, which is equivalent to the distance between the second connection lines 121a and 121c and the chip 201.
  • the third connection 111d and the first connection 111b are located in the same "layer" in the thickness direction of the substrate 100, and the second connection 121a, 121c is disposed on the bottom surface of the substrate 100, and a metal layer is coated on the top surface and the bottom surface of the substrate 100. Then, the first connection line 111b, the second connection lines 121a and 121c, and the third connection line 111d are simultaneously formed by the photoresist to improve the production efficiency.
  • the present invention is not limited to this embodiment, and the third connection 111d may not be in the same "layer" as the first connection 111b.
  • a third conductive layer 401d is disposed in the third via hole 121d, and the second connection line is at least one, wherein one end to the second connection line 121a corresponds to the second via hole 121a and passes through the second conductive layer 401a and the chip pin 211a The other end corresponds to the third through hole 121d and is electrically connected to the third connection 111d through the third conductive layer 401d.
  • the chip pins 211a, 211c escape from the dense chip lead enclosure through the second via holes 121a, 121c to the layer where the second traces 121a, 121c are located, and then the second trace 121a escapes through the third via 121d to
  • the layer where the third connection 111d is located if necessary, design the layer of the third connection 111d and the second connection lines 121a, 121c and the pattern of the traces, so as to help the chip pins escape as much as possible to obtain the connection, thereby
  • the density of the chip pins is increased, the connection node density of the chip 201 is increased, and the data transmission speed of the chip 201 is improved.
  • two or more second wires 121a and 121c may be electrically connected to the third wire 111d.
  • the chip pins 211a, 211c are connected to the second wires 121a, 121c through the second conductive layers 401a, 401c in the second via holes 121a, 121c, and from the second openings of the second via holes 121a, 121c
  • the second conductive layers 401a and 401c are disposed to avoid the occlusion of the chip pins 211a and 211c by the chip 201, so that the second through holes 121a and 121c and the chip pins are accurately positioned, thereby improving the connection precision.
  • the second through holes 121a and 121c can be mass-produced, and the plurality of chips 201 are disposed in batches to greatly improve the production efficiency.
  • the second conductive layers 401a and 401c are disposed in the second through holes 121a and 121c, and occupy no additional space, and can be greatly reduced.
  • the overall volume after a small package, in particular, the ability to reliably use a flexible circuit board as the substrate 100 is a great advantage.
  • the conventional wiring method is as shown in FIG. 17, and the wirings 111a, 111b, and 111c are all disposed on the top surface of the substrate 100, and the chip pins 211a, 211b, and 211c can be taken out only on a single plane.
  • the timing wires 111a, 111b, and 111c need to pass between the chip pins 211a, 211b, and 211c, and the chip pins 211a, 211b, and 211c are to be avoided, so that sufficient gaps need to be reserved between the chip pins for wiring.
  • the gap D1 of the chip pin limits the number of wires, can not obtain a more wire, and if the number of chip pins is large, the chip pins near the edge of the chip 201 can be led out by the wire
  • the traditional connection method limits the density of the connection and the density of the chip pins.
  • the chip pins are respectively led out through the first connection line 111b and the second connection lines 121a, 121c, and the first connection line 111b and the second connection line 121a, 121c are in the thickness of the substrate 100.
  • the layers are in different thickness layers, and the two wires do not interfere with each other.
  • the second wires 121a and 121c do not need to pass through the gap D2 between the chip pins, so that a higher density connection can be obtained. Similarly, it can be set. With higher density chip pins, the chip 201 obtains a higher density connection node and improves the data transfer speed of the chip 201.
  • the conductive bonding material is removed from the second opening of the second through holes 121a, 121c
  • the second conductive layers 401a and 401c are formed by being fed into the second through holes 121a and 121c and bonding the conductive adhesive to the inner walls of the second through holes 121a and 121c and the chip leads 211a and 211c.
  • the chip of the top layer is firmly bonded to the substrate 100 in the second via holes 121a, 121c to prevent the device from falling off, and the chip pins 211a, 211c from the chip are formed to the second conductive Conductive channels of layers 111a, 111c for good electrical connection properties.
  • the conductive bonding material is a solder ball, or a solder paste, or a conductive paste, or a conductive metal paste. According to the needs of the process or the material of the substrate 100, the size of the inner wall of the second through holes 121a, 121c, and the nature of the surface material, A combination of one or more.
  • the process of placing a conductive bonding material to form a conductive connecting channel may use common soldering processes, including surface cleaning, flux spraying, precision placement of solder balls and heat treatment using a ball machine, and more special chemical surfaces. Cleaning, surface treatment, precision spraying of solder paste, conductive paste or conductive metal paste, followed by heat treatment to form mechanical and electrical connections.
  • conductive bonding is provided in the second through holes 121a, 121c by screen printing. material.
  • the device is universal and can be synchronized with the production of the second connection 111a, 111c, which saves the process flow and further reduces the cost.
  • the laser is used to melt through the second openings of the second through holes 121a, 121c.
  • Plasma cleaning or chemical solvent creates additional via holes in the adhesive film 300.
  • the additional via holes abut the second via holes 121a, 121c with the chip leads 211a, 211c, and the second conductive layers 401a, 401c protrude into the additional via holes.
  • the adhesive film 300 is prevented from impeding the electrical connection of the chip leads 211a, 211c, the second conductive layers 401a, 401c, and the second wires 111a, 111c.
  • a protective layer is provided on the inner walls of the second through holes 121a, 121c for protecting the substrate 100 when making additional through holes.
  • the fabrication of the additional via holes may be, but is not limited to, a process using chemical etching or drilling, in which case it is necessary to pass through the second through holes 121a, 121c, which may cause damage to the inner walls of the second through holes 121a, 121c, and thus to the substrate 100. The damage is caused, and the protective layer can protect the inner walls of the second through holes 121a, 121c from damage.
  • the protective layer may be a material that facilitates electrical connection of the second conductive layers 401a, 401c.
  • the protective layer may be in electrical contact with the second wires 121a, 121c, contributing to the second wires 121a, 121c and Electrical connection of the two conductive layers 401a, 401c.
  • the protective layer may be a metal film which is pre-sputtered or evaporated on the inner walls of the second through holes 121a, 121c, so that the material of the inner walls of the second through holes 121a, 121c is not exposed to being exposed during the chemical etching process.
  • the solvent or ions are etched, and such a thin metal layer can also improve the conductivity of the second conductive layers 401a, 401c which are subsequently plated in the second via holes 121a, 121c.
  • a method of fabricating the second conductive layers 401a and 401c in the second via holes 121a and 121c may be performed to form the first conductive layer 401b in the first via hole 121b and the third conductive layer in the third via hole 121d.
  • an additional through hole and a protective layer can also be formed by a method similar to the above.
  • the first conductive layer 401b, the second conductive layer 401a, 401c, and the third conductive layer 401d are simultaneously formed in the first via hole 121b, the second via hole 121a, 121c, and the third via hole 121d, thereby improving production efficiency.
  • the chip pins are respectively electrically connected to the first connection line 111b and the second connection lines 121a and 121c through the first through hole 121b and the second through holes 121a and 121c, respectively, and the first connection line 111b and The second wires 121a and 121c form two “layers” in the thickness direction of the substrate 100.
  • the present invention is not limited thereto, and three or more layers of “layers” may be provided through the aforementioned “hole connection”.
  • the chip pins are electrically connected to the third, fourth, ..., n-layer wiring, so that more chip pins can escape from the surrounding of the surrounding chip pins for electrical connection, thereby increasing the density of the chip pins. Improve the speed of chip 201 data transmission.
  • the second through holes 121a and 121c electrically connect the chip pins 211a and 211c and the second wires 121a and 121c to form a “hole connection”, and pass the first method in a similar manner to the aforementioned “hole connection”.
  • the via hole 121b electrically connects the chip pin 211b and the first wiring 111b.
  • the chip pin 211b and the first wire 111b are electrically connected by other means, for example, the chip pin 211b and the first wire 111b are directly in contact connection.
  • the substrate 100 may be a normal hard board, and the substrate 100 may also be a flexible circuit board.
  • the chip pins are connected by a "hole connection" method to improve the chip pins. Density, thereby reducing the volume of the chip 201, and the first conductive layer 401b and the second conductive layers 401a, 401c are respectively located in the first through hole 121b and the second through holes 121a, 121c, occupying no extra volume, the chip 201 There may be no need to reserve a gap between the substrates 100 (but not limited thereto, a gap such as an adhesive layer may be provided as needed), and the overall thickness of the chip 201 and the substrate 100 may be reduced, when the substrate 100 is a flexible circuit.
  • the board or the multilayer flexible circuit board When the board or the multilayer flexible circuit board is used, the overall flexibility can be maintained, and it can be used for a wearable device or the like.
  • the substrate 100 includes at least two layers of flexible circuit boards stacked, if two "layers" or more are provided, the first connection 111b, or the second connection 121a, 121c, and the third may be first used.
  • the connection 121d or other connection is disposed between the adjacent two flexible circuit boards, and the first through hole 121b, the second through holes 121a and 121c, and the third through hole 121d are formed.

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Abstract

一种芯片(201)连线方法及结构，其中芯片(201)连线方法包括：所述基板(100)设有第一连线(111b)和第二连线(111a、111c)，在所述基板(100)的厚度方向上，所述第一连线(111b)与所述芯片(201)的距离小于所述第二连线(111a、111c)与所述芯片(201)的距离，将芯片(201)设于所述基板(100)的顶面，所述芯片(201)设有至少两个芯片引脚(211a、211b、211c)，所述基板(100)设有第二通孔(121a、121c)，所述第二通孔(121a、121c)与所述第二连线(111a、111c)对应，所述第二通孔(121a、121c)内设有第二导电层(401a、401c)；其中，至少一个所述芯片引脚(211a、211b、211c)与所述第一连线(111b)电连接，另有至少一个所述芯片引脚(211a、211b、211c)与所述第二通孔(121a、121c)的第一开口(120c)对应、并且所述第二导电层(401a、401c)将所述芯片引脚(211a、211b、211c)与所述第二连线(111a、111c)电连接。连线绕过芯片引脚(211a、211b、211c)的遮挡，可以获得高密度的芯片引脚(211a、211b、211c)、连线，提高芯片(201)连接的节点数量，提高芯片(201)数据传输速度。

Description

芯片连线方法及结构 技术领域
本发明属于电子领域，具体涉及一种芯片连线方法及结构。
背景技术
传统的集成电路系统，需要将芯片单独封装后，再与其它电子元件等一起安装于电路板上。通过以键合或者倒装的方式连接到基板的电路端口上，再接入到电路板上，各种材料使用量大，工艺复杂，生产成本高；而且使用大量特性各异的材料，也容易在各材料界面诱发多种热机械应力的问题。
并且，芯片间数据通讯以及芯片和其它电子元件之间的电路连接需要通过芯片引脚和电子元件器件引脚以及电路板内部的电路。芯片之间以及芯片和其它电子元件之间必须留有足够空间，整个系统的几何尺寸也因而受到约束，不能充分小型化。
连线密度收到芯片引脚之间的间距的限制，不能将芯片引脚更加密集。
发明内容
基于此，本发明在于克服现有技术的缺陷，提供一种芯片连线方法以及芯片连线结构，连线绕过芯片引脚的遮挡，可以获得高密度的芯片引脚、连线，提高芯片连接的节点数量，提高芯片数据传输速度。
其技术方案如下：
一种芯片连线方法，包括：基板设有第一连线和第二连线，在所述基板的厚度方向上，所述第一连线与所述芯片的距离小于所述第二连线与所述芯片的距离，将芯片设于所述基板的顶面，所述芯片设有至少两个芯片引脚，所述基板设有第二通孔，所述第二通孔与所述第二连线对应，所述第二通孔内设有第二导电层；其中，至少一个所述芯片引脚与所述第一连线电连接，另有至少一 个所述芯片引脚与所述第二通孔的第一开口对应、并且所述第二导电层将所述芯片引脚与所述第二连线电连接。
其中一个实施例中，所述基板设有第三连线和第三通孔，在所述基板的厚度方向上，所述第三连线与所述芯片的距离大于或小于所述第二连线与所述芯片的距离，在所述第三通孔内设置第三导电层，所述第二连线为至少一个，其中至少一个所述第二连线的一端与所述第二通孔对应并且通过所述第二导电层与所述芯片引脚电连接、另一端与所述第三通孔对应并且通过所述第三导电层与所述第三连线电连接。
其中一个实施例中，通过所述第二通孔的第二开口在所述第二通孔内制作第二导电层的过程中，将所述第二导电层从所述第二通孔的第二开口送入所述第二通孔内。
其中一个实施例中，所述第二导电层为焊球、或焊锡膏、或导电胶；或者，所述第二导电层为金属层，采用沉金、溅射、或电镀的方法制作所述金属层。
其中一个实施例中，采用丝网印刷在所述第二通孔内设置所述导电粘接材料。
其中一个实施例中，在所述芯片与所述基板之间设置粘装膜，所述粘装膜将所述芯片件粘贴于所述基板。
其中一个实施例中，通过所述第二通孔的第二开口，使用激光烧熔、等离子清洁、或化学溶剂在所述粘装膜制作附加通孔，所述附加通孔将所述第二通孔与所述芯片引脚对接，所述第二导电层伸入所述附加通孔内。
其中一个实施例中，在所述第二通孔的内壁设置保护层，所述保护层用于在制作所述附加通孔时保护所述基板。
其中一个实施例中，所述基板上设有第一通孔，所述第一连线与所述第一通孔对应，所述第一通孔内设有第一导电层，所述第一导电层将所述第一连线与所述芯片引脚电连接。
其中一个实施例中，所述基板为柔性电路板；或者，所述基板包括至少两层层叠设置的柔性电路板。
一种芯片连线结构，包括：芯片设于基板的顶面，所述基板设有第一连线和第二连线，在所述基板的厚度方向上，所述第一连线与所述芯片的距离小于所述第二连线与所述芯片的距离，所述芯片设有至少两个芯片引脚，所述基板设有第二通孔，所述第二通孔与所述第二连线对应，所述第二通孔内设有第二导电层；其中，至少一个所述芯片引脚与所述第一连线电连接，另有至少一个所述芯片引脚与所述第二通孔对应、并且所述第一导电层将所述芯片引脚与所述第二连线电连接。
其中一个实施例中，所述基板上设有第一通孔，所述第一连线与所述第一通孔对应，所述第一通孔内设有第一导电层，所述第一导电层将所述第一连线与所述芯片引脚电连接。
其中一个实施例中，所述基板设有第三连线和第三通孔，所述第三通孔内设有第三导电层，在所述基板的厚度方向上，所述第三连线与所述芯片的距离大于所述第二连线与所述芯片的距离，所述第二连线为至少一个，其中至少一个所述第二连线的一端与所述第一通孔对应、另一端与所述第二通孔对应，所述第二连线的一端通过所述第二导电层与所述芯片引脚电连接、另一端通过所述第三导电层与所述第三连线电连接。
其中一个实施例中，所述芯片、所述第一连线、和所述第三连线设于所述基板的顶面，所述第二连线设于所述基板的底面。
其中一个实施例中，所述芯片和所述第一连线设于所述基板的顶面，所述第二连线设于所述基板的底面。
其中一个实施例中，所述基板为柔性电路板；或者，所述基板包括至少两层层叠设置的柔性电路板。
本发明的有益效果在于：
1、一种芯片连线方法，包括：所述基板设有第一连线和第二连线，第一连线和第二连线可以设置于基板的顶面、基板的底面、或嵌设于基板的内部，在所述基板的厚度方向上，所述第一连线与所述芯片的距离小于所述第二连线与所述芯片的距离，类似于在基板上分层设置第一连线和第二连线，使第一连 线第二连线彼此不相干涉，第一连线和第二连线在基板的厚度方向上分为两“层”，如图14-15所示。
将芯片设于基板的顶面，可以将芯片绑定于基板上，也可以不绑定。所述芯片设有至少两个芯片引脚，芯片的芯片引脚包括但不限于芯片内部引出的连接部、与连接部电连接的扩展脚，只要通过芯片引脚能够和芯片电连接均可。
所述基板设有第二通孔，所述第二通孔与所述第二连线对应，所述第二通孔内设有第二导电层，第二连线的部分位于第二通孔开口附近或者伸入第二通孔，使得第二连线可以与第二导电层电连接。其中，至少一个所述芯片引脚与所述第一连线电连接，另有至少一个所述芯片引脚与所述第二通孔的第一开口对应、并且所述第一导电层将所述芯片引脚与所述第二连线电连接。
首先，通过第二通孔内的第二导电层将芯片引脚与第二连线相连接，并从第二通孔的第二开口设置第二导电层，可以避开芯片对芯片引脚的遮挡，使第二通孔与芯片引脚精准定位，可以提高连接的精度，并且可以批量制作第二通孔、并且批量设置多个芯片，大幅提高生产效率；第二导电层设于第二通孔内，不占用额外空间，可以大幅减小封装后整体的体积，特别是，对于使用柔性电路板作为基板，上述步骤完成后基本整体的仍然保持柔性，是一个很大的优势。
其次，芯片安装于基板的顶面，基板上给芯片覆盖的区域称为“阴影区域”，芯片的引脚位于阴影区域内，芯片引脚要从阴影区域“逃逸(escape)”才能对外连接。传统方式将连线全部设于基板的顶面，芯片引脚只能从基板顶面逃逸，此时连线需要穿过芯片引脚之间的间隙，并且要避开芯片引脚，导致芯片引脚之间需要预留足够的间隙供连线穿过，如图17所示，这样就限制了连线的数量，不能获得更过的连线。并且，如果芯片引脚的数量很多，那么靠近芯片边沿的芯片引脚可以由连线引出、但就已经没有空隙可以设置连线将靠近芯片中部的芯片引脚引出，所以传统连线方式限制了连线的密度、芯片引脚的密度。但本发明中，芯片引脚分别通过第一连线和第二连线逃逸，并且第一连线、第二连线在基板的厚度方向上处于不同的厚度层，二者之间不相干涉， 一部分芯片引脚从第一连线逃逸、另一部分芯片引脚通过第二连线逃逸，相当于芯片引脚可以通过两“层”平面来逃逸，增加芯片引脚的密度。
对于通过第二连线逃逸的芯片引脚，在阴影区域内先通过第二通孔内的第二导体层逃逸到第二连线所在的层，再从第二连线向外逃逸，这样的话有部分芯片引脚逃逸到第二连线后从第二连线所在的层对外连接，从基板顶面逃逸出阴影区域的连线数量就减少，可以布置更多的连线，并且即使适当增大连线的线宽也不会降低连线的数量。第二连线不需要经过芯片引脚之间的间隙，芯片引脚通过第二通孔从其周围密集的芯片引脚包围中逃逸到第二连线所在层，避开多个芯片引脚之间的相互阻挡，可以获得更高密度的连线，同理，可以设置更高密度的芯片引脚，芯片获得更高密度的连接节点，提高芯片的数据传输速度。本发明的芯片连线方法和结构，并且，本发明中，部分芯片引脚直接从阴影区域通过第二通孔逃逸到第二连线，芯片上可以制作更高密度的芯片引脚，从而获得等过的连接节点。
但在基板的厚度方向上不限于分为两“层”，根据实际绕线需要，可以设置三“层”、四“层”或者跟更多的“层”，这样，芯片引脚可以分别通过更多“层”来逃逸，使得连线的设置更灵活，可以获得更多的连接节点、连接线。
2、所述基板设有第三连线和第三通孔，所述第三通孔内设有第三导电层，在所述基板的厚度方向上，所述第三连线与所述芯片的距离大于或小于所述第二连线与所述芯片的距离，第二连线与第三连线不在同一“层”，第三连线可以与第一连线在同一“层”、也可以不在同一“层”，当第三连线与第一连线不在同一“层”时，第一连线第二连线、第三连线构成三“层”。
在所述第三通孔内设置第三导电层，所述第二连线为至少一个，其中至少一个所述第二连线的一端与所述第二通孔对应并且通过所述第二导电层与所述芯片引脚电连接、另一端与所述第三通孔对应并且通过所述第三导电层与所述第三连线电连接。可以通过第二连线将芯片引脚和第三连线电连接，芯片引脚通过第二通孔从密集的芯片引脚包围中逃逸到第二连线所在层，通过第三通孔逃逸到第三连线所在层，根据需要设计第三连线和第二连线的所在的层次以及 走线的图案，可以尽可能多的帮助芯片引脚逃逸出来获得连接，从而提高芯片引脚的密度、提高芯片的连接节点密度，进而提高芯片数据传输速度。
优选的，所述芯片、所述第一连线、以及所述第三连线设于所述基板的顶面，所述第二连线设于所述基板的底面，在基板的顶面和底面涂布金属层，然后用光刻胶同步制作所述第一连线、第二连线、第三连线，提高生产效率。
3、通过所述第二通孔的第二开口在所述第二通孔内制作第二导电层的过程中，将导电粘接材料从所述第二通孔的第二开口送入所述第二通孔内，使所述导电粘接材料粘接于所述第二通孔的内壁和所述器件引脚上构成所述第二导电层。采用从第二开口送入导电粘接材料的方式，可以在基板的底面进行操作，而不会被芯片干扰。通过使用导电性的粘接材料，在第而通孔内把顶层的芯片牢固地粘接到基板上避免器件脱落的同时，形成从芯片引脚到第二导电层的导电通道，以获得好的导电连接性能。
4、所述导电粘接材料为焊球、或焊锡膏、或导电胶、或导电金属浆。可以根据工艺需要或者基板材质、第二通孔内壁的尺寸、表面材料性质，选择一种或多种的组合。放入导电粘接材料形成导电性连接通道的工艺，可能使用常见的焊接工艺，包括表面清洁、助焊剂喷涂、使用置球机精密放置焊球和热处理等步骤；也可能使用更特别的化学表面清洁，表面处理，精密喷涂焊锡膏、导电胶或导电金属浆，然后热处理以形成机械和电连接。
5、通过所述第二通孔的第二开口在所述第二通孔内制作第二导电层的过程中，采用丝网印刷在所述第二通孔内设置所述导电粘接材料。设备通用、可以和电路层的制作同步进行，节约工艺流程，进一步降低成本。
6、在所述芯片与所述基板之间设置粘装膜，所述粘装膜将所述芯片件粘贴于所述基板。采用粘装膜粘贴的方式，将芯片安放于基板上，就可以实现芯片固定于基板，节约步骤、提高效率、降低成本。粘装膜可以是绝缘的，这样在即使基板顶面设有连线的情况下，芯片引脚也能与所述基板顶面的连线电绝缘。
7、通过所述第二通孔的第二开口在所述第二通孔内制作第二导电层的过程中，通过所述第二通孔的第二开口，使用激光烧熔、等离子清洁、或化学溶剂在所述粘装膜制作附加通孔，所述附加通孔将所述第一通孔与所述器件引脚对接，所述第二导电层伸入所述附加通孔内，避免粘装膜阻碍芯片引脚、第二导电层、以及第二连线的电连接。
8、在所述第二通孔的内壁设有保护层，所述保护层用于在制作所述附加通孔时保护所述基板。制作所述附加通孔，可以但不限于使用化学蚀刻、或钻孔的工艺，此时需要穿过第二通孔，可能会对第二通孔的内壁造成损伤，进而对基板造成损伤，保护层可以保护第二通孔的内壁不受损伤。进一步的，保护层可以是有助于第二导电层电连接的材料，此时保护层可以与第二连线电接触，有助于第二连线与第二导电层的电连接。譬如，所述保护层可以是金属薄膜，被预先溅镀或蒸镀在第二通孔的内壁，这样可以在化学蚀刻过程中，保护所述第二通孔内壁材料不至于被暴露于蚀刻溶剂或离子中，而且这样的金属薄层也可以提高随后在第二通孔中电镀的第二导电层的导电性。
9、所述基板上设有第一通孔，所述第一连线与所述第一通孔对应，所述第一通孔内设有第一导电层，所述第一导电层将所述第一连线与所述芯片引脚电连接。第二通孔将芯片引脚和第二连线电连接的方式构成“孔连接”，也可以采用与前述“孔连接”类似的方式通过第一通孔将芯片引脚和第一连线电连接。芯片引脚分别通过第一通孔和第二通孔分别逃逸到第一连线和第二连线所在层次进行电连接，第一连线和第二连线在所述基板的厚度方向上形成两“层”，但不限于此，也可以设置三层或三层以上的连线“层”，通过前述“孔连接”的方式将芯片引脚与第三、四、…、n层连线电连接，使更多的芯片引脚可以从其周围芯片引脚的包围中逃逸出来进行电连接，从而可以增加芯片引脚的密度，提高芯片数据传输的速度。
10、所述基板为柔性电路板；通过“孔连接”的方式将芯片引脚引出在连接，可以提高芯片引脚的密度，从而减小芯片的体积，并且第一导电层和第二导电层分别位于第一通孔和第二通孔内，不占用额外的体积，芯片可基板之间 甚至不需要预留间隙(但不限于此，根据需要也可以设置间隙，例如粘装层)，可以减小芯片和基板构成的整体的厚度，当基板为柔性电路板或多层柔性电路板时，可以保持整体的柔性，可以用于可穿戴设备等。当所述基板包括至少两层层叠设置的柔性电路板时优选的，如果设置了两“层”以上的连线，可以先将第一连线、或第二连线、或其他的连线设置于相邻两层柔性电路板之间，在。
11、所述芯片和所述第一连线设于所述基板的顶面，所述第二连线设于所述基板的底面。在基板的顶面和底面涂布金属层，然后用光刻胶同步制作所述第一连线、第二连线，提高生产效率。
附图说明
图1为本发明实施例一芯片连线方法示意图一；
图2为本发明实施例一芯片连线方法示意图二；
图3为本发明实施例一芯片连线方法示意图三；
图4为本发明实施例一芯片连线方法示意图四；
图5为本发明实施例一芯片连线方法示意图五；
图6为本发明实施例二芯片连线方法示意图一；
图7为本发明实施例二芯片连线方法示意图二；
图8为本发明实施例二芯片连线方法示意图三；
图9为本发明实施例二芯片连线方法示意图四；
图10为本发明实施例三芯片连线方法示意图一；
图11为本发明实施例三芯片连线方法示意图二；
图12为本发明实施例三芯片连线方法示意图三；
图13为本发明实施例三芯片连线方法示意图四；
图14为本发明实施例四芯片连线方法侧视图一；
图15为本发明实施例四芯片连线方法侧视图二；
图16为本发明实施例四芯片连线方法俯视图；
图17为本发明实施例四传统连线方法俯视图。
附图标记说明：
100、基板，101、基片，110a、110b、电路层，120a、120b、连接通孔，120c、第一开口，120d、第二开口，121a、121b、保护层，200、元器件，210a、210b、210c、器件引脚，300、绝缘介质，400a、400b、导电层，500、导电连接端口，201、芯片，211a、211b、211c、芯片引脚，111a、111c、第二连线，111b、第一连线，111d、第三连线，121a、121c、第二通孔，121b、第一通孔，121d、第三通孔，401a、401c、第二导电层，401b、第一导电层，401d、第三导电层。
具体实施方式
下面对本发明作进一步详细说明，但本发明的实施方式不限于此。
实施例一
本实施例中，如图4所示，集成封装电路包括：元器件200、基板100。元器件200安装于基板100的顶面，基板100的顶面、底面分别设有电路层110a、110b，元器件200与基板100之间设有绝缘介质300(本实施例中，绝缘介质300同时也是粘装膜)。元器件200设有器件引脚210a、210b，器件引脚210a、210b朝向基板100，电路层110a、110b设有电路引脚，基板100设有连接通孔120a、120b，连接通孔120a、120b与电路引脚对接，连接通孔120a、120b的第一开口120c与器件引脚210a、210b对接，连接通孔120a、120b的第二开口120d为操作窗口，绝缘介质300(粘装膜)设有附加通孔，附加通孔与连接通孔120a、120b的第一开口120c相连通，连接通孔120a、120b内设有导电层400a、400b，导电层400a、400b伸入附加通孔与器件引脚210a、210b电连接。其中，绝缘介质300将元器件200与基板100隔开，绝缘介质300(粘装膜)可以避免元器件200对基板100顶面的电路层110a、110b或其他导电的结构产生影响。根据需要可以设置元器件200的器件引脚210a、210b数量，当元器件200的器件引脚210a、210b可以有两个以上，其中部分器件引脚210a、210b通过本发明的集成电路封装方法与基板100或电路层110a、 110b连接，绝缘介质300可以避免另外的器件引脚210a、210b对基板100或电路层110a、110b产生影响。本实施例中，绝缘介质300也是粘装膜，绝缘介质300(粘装膜)将元器件200粘贴于基板100。采用粘贴的方式将元器件200安放于基板100上，将元器件200安放于基板100的过程就可以将元器件200固定于基板100，节约步骤、提高效率、降低成本。但不限于此，可以是绝缘介质300仅起到隔离元器件200和基板100的作用，采用另外的方法将元器件200固定于基板100，也可以采用粘装膜将元器件200粘贴于基板100，但粘装膜不起到将元器件200与基板100隔离的作用。
本实施例中，集成电路封装方法，包括：如图1所示，基板100的顶面、底面分别具有电路层110a、110b，电路层110a、110b具有电路引脚，电路引脚可以是电路层110a、110b直接引出的连接部，也可以是和连接部电连接的扩展引脚，只要通过电路引脚能够和电路层110a、110b电连接均可。元器件200的器件引脚210a、210b包括但不限于元器件200内部引出的连接部、与连接部电连接的扩展脚，只要通过器件引脚210a、210b能够和元器件200电连接均可。使器件引脚210a、210b与连接通孔120a、120b的第一开口120c对接。
如图2所示，元器件200上设有器件引脚210a、210b的一面涂布粘装膜(不限于本实施例，可以在基板100涂布粘装膜)，元器件200具有器件引脚210a、210b的一面朝向基板100，将元器件200安放于基板100，此时，粘装膜将元器件200安装于基板100上。(本实施例中粘装膜同时是绝缘介质300，不限于本实施例，也可以不采用粘装膜粘贴元器件200)
如图3所示，在所述基板100上制作连接通孔120a、120b，使器件引脚210a、210b与连接通孔120a、120b的第一开口120c对接，连接通孔120a、120b的第二开口120d可供在连接通孔120a、120b内制作导电层400a、400b，第一开口120c、第二开口120d结构参照图8所示，器件引脚210a、210b位于基板100的顶面，通过连接通孔120a、120b的第二开口120d，可以从基板100的底面将元器件200与电路层110a、110b电连接，回避元器件200从上方对器件引脚210a、210b的遮挡。通过连接通孔120a、120b的第二开口120d，使用 激光烧熔、等离子清洁、或化学溶剂在粘装膜制作附加通孔，附加通孔将连接通孔120a、120b与器件引脚210a、210b对接，避免粘装膜阻碍器件引脚210a、210b、导电层400a、400b、以及电路引脚的电连接。
如图4所示，通过连接通孔120a、120b的第二开口120d在连接通孔120a、120b内制作导电层400a、400b，导电层400a、400b伸入附加通孔内，导电层400a、400b将器件引脚210a、210b与电路引脚电连接。
按以上方法封装，可以降低集成电路封装的成本、节约封装时间。并且，降低基板100和元器件200构成的整体的厚度，甚至基板100和元器件200之间不需要预留间隙(原则上无需预留间隙，但是根据需要可以在基板100与元器件200设置其他材料)；不需要进行加热焊接的步骤，特别是针对超薄的元器件200(例如超薄芯片)、柔性电路板的封装，可以避免较大温度变化所产生的系统整体热机械应力分布，以及对元器件200性能的影响。
此外，在制作导电层400a、400b后，在基板100上设置封装层，元器件200被封装层和基板100包裹封装；或者，在将元器件200安放于基板100后、制作导电层400a、400b形之前，在基板100上设置封装层，两个元器件200被封装层和基板100包裹封装。采用封装层将元器件200包封，可以保护元器件200，并且封装层可以覆盖基板100，可以在基板100的顶面、底面同时设置封装层，保护基板100以及基板100上的电路层110a、110b，避免环境因素的影响。同时，封装层也将元器件200固定于基板100，而不需要另外程序将元器件200固定。另外，固化后的封装层也变成整个系统整体更好的支撑板，可以翻转后进行在基板上的后续工艺制程。
其中，连接通孔120a、120b与器件引脚210a、210b对接，器件引脚210a、210b至少部分位于连接通孔120a、120b的第一开口120c附近、或深入连接通孔120a、120b内，使得导电层400a、400b可以与器件引脚210a、210b电连接；电路引脚和连接通孔120a、120b对接，电路引脚至少部分位于连接通孔120a、120b的第一开口120c附近、或第二开口120d附近、或连接通孔120a、120b内壁的附近，使得导电层400a、400b可以与电路引脚电连接；元器件200可以 是芯片或者电子元件(包括但不限于电阻、电容)或者其他电子器件(包括但不限于天线)。元器件200可以通过连接通孔120a、120b、导电层400a、400b固定于基板100，也可以是，元器件200通过其他方式(包括但不限于粘贴、模压塑料包封)固定于基板100。
其中，通过连接通孔120a、120b的第二开口120d在连接通孔120a、120b内制作导电层400a、400b的过程中，采用电镀的方式制作导电层400a、400b，最终形成的导电层400a、400b参照图4、9，可以获得很好的导电性能，电镀可以控制导电层400a、400b的厚度，获得理想的导电性能。但不限于此，还可以是，通过连接通孔120a、120b的第二开口120d在连接通孔120a、120b内制作导电层400a、400b的过程中，将导电粘接材料从连接通孔120a、120b的第二开口120d送入连接通孔120a、120b内，使导电粘接材料粘接于连接通孔120a、120b的内壁和器件引脚210a、210b上构成导电层400a、400b。采用从第二开口120d送入导电粘接材料的方式，可以在基板100的背面进行操作，而不会被元器件200干扰，通过粘接的方式将导电粘接材料粘附于连接通孔120a、120b的内壁和元器件200的器件引脚210a、210b，在适当加热或化学处理后，可以同时形成机械和电连接，也确保稳定的导电连接性能。导电粘接材料为焊球、或焊锡膏、或导电胶、或导电金属浆，最终形成的导电层400a、400b参照图13，可以根据工艺需要或者基板100材质、连接通孔120a、120b内壁的性质，选择一种或多种的组合。或者，通过连接通孔120a、120b的第二开口120d在连接通孔120a、120b内制作导电层400a、400b的过程中，采用丝网印刷在连接通孔120a、120b内设置导电粘接材料。丝网印刷是电路层110a、110b常用制作方法，采用丝网印刷的方式制作导电层400a、400b，设备通用、可以和电路层110a、110b的制作同步进行，节约工艺流程，进一步降低成本。
进一步的，可以在很大面积的大面板上同时安装多个元器件200，大面板上的批量处理进一步减低成本、节约封装时间。批量生产时，采用大平板的载体，将多组元器件200排列于载体上，将载体覆盖于基板100顶面，使用粘装膜将元器件200粘贴于基板100，将载体与元器件200脱离(可以是采用光敏 或热敏材料将元器件200安装于载体，改变温度或光照使载体和元器件200脱离)，完成封装后，最后根据预设的分组，将基板100裁剪为多个子板，每个子板对应一组元器件200，每个子板都是独立的。如此，可以大批量进行封装作业，大幅提高生产效率。(其中，粘装膜可以同时是绝缘材料)
本实施例中，基板100的顶面和底面分别设有电路层110a、110b，芯片同时与电路层110a、110b电连接；但不限于此，可以是，基板100内嵌设有电路层110a、110b，器件引脚210a、210b与电路层110a、110b电连接；还可以是基板100的顶面设有电路层110a、110b、或/和基板100的底面设有电路层110a、110b、或/和基板100内设有电路层110a、110b，器件引脚210a、210b为至少两个，其中一个器件引脚210a、210b至少与其中一个电路层110a、110b电连接，另有一个器件引脚210a、210b至少与余下另一个电路层110a、110b电连接。基板100设有两层以上的电路层110a、110b，元器件200通过不同的器件引脚210a、210b同时与至少两层不同的电路层110a、110b电连接，扩展电路功能。
本实施例中，可以是，基板100为柔性电路板；或者，基板100包括至少两层层叠设置的柔性电路板。通过本集成电路封装方法将元器件200安装于基板100，并实现元器件200与基板100上电路层110a、110b的电连接，元器件200、基板100构成的整体厚度小，可以保持整体的柔性，可以用于可穿戴设备等。
其中，元器件200为芯片、或电子元件。本集成电路封装方法适用于芯片或电子元件的封装，电子元件包括但不限于独立的电阻、电容、电感、二极管、或三极管，芯片包括但不限于裸片、晶圆、或者经过封装的集成芯片。可以使用相同的设备和工艺流程对芯片或者电子元件进行封装，降低成本。
其中，图1至4仅示例单个元器件200的结构，但不限于此，还可以是，元器件200为至少两个。本集成电路封装方法适用于两个以上元器件200，进一步的，可以同时对两个以上的元器件200进行操作，将以上的元器件200安装于基板100并实现元器件200与电路层110a、110b的电连接，提高效率、降 低成本。当元器件200为至少两个时，可以是，至少两个元器件200当中，包括至少一个芯片和至少一个电子元件。可以同时对芯片和电子元件进行封装，提高效率，降低成本。当在基板100上设置封装层时，可以选择封装单个元器件200或封装两个以上元器件200。封装层的目的主要是保护元器件200不受外界环境因素的影响，譬如水汽、电磁辐射对元器件电性能的影响。同时，它也固定了多个元器件200在基板100上的相对位置，确保电连接的稳定性。在此发明中，在封装层固化后，封装层更作为支撑板，让我们随后可以方便地在基板100上进行连接通孔内壁导电层的制作。此外，还可以在一个基板100上设置两个以上的封装层，封装层相互之间留有间隙，可以提供更大的曲率，使基板100、元器件200、封装层构成的整体更具装柔性，特别是当基板100为柔性电路板或基本为两成以上的柔性电路板构成时，能够使集成封装电路保持这种柔性，使集成封装电路可以应用于例如可穿戴设备这类需要保持柔性的场合。
其中，电路层110a、110b为功能电路，电路层110a、110b具有一定的电子功能；或者电路层110a、110b本身构成电子元件，包括但不限于天线。本集成封装电路结构的电路层110a、110b适用范围广，可以实现集成多种功能。
根据需要，可以在制作导电层400a、400b前，通过第二开口120d在连接通孔120a、120b的内壁上制作辅助层，辅助层与电路层110a、110b电连接，然后在辅助层上制作导电层400a、400b，辅助层用于辅助制作导电层400a、400b，使导电层400a、400b更好地与器件引脚210a、210b、电路引脚电连接，或者更好的附着于连接通孔120a、120b的内壁。或者，在连接通孔120a、120b的内壁设有保护层121a、121b，保护层121a、121b用于在制作附加通孔时保护基板100。制作附加通孔，可以使用但不限于化学蚀刻、或钻孔的工艺，此时需要穿过连接通孔120a、120b，可能会对连接通孔120a、120b的内壁材料造成损伤，进而对基板100、电路层110a、110b造成损伤，保护层121a、121b可以保护连接通孔120a、120b的内壁不受损伤。进一步的，保护层121a、121b可以是有助于导电层400a、400b电连接的材料，此时保护层121a、121b 可以与电路引脚接触，有助于电路引脚与导电层400a、400b的电连接。
本实施例中，连接通孔120a、120b的内壁设有保护层121a、121b，保护层121a、121b同时也是辅助层，保护层121a、121b(辅助层)未在图中示出，参照图10至13。并且，本实施例中保护层121a、121b(辅助层)采用与电路层110a、110b相同的材料制作，例如电路层110a、110b采用铜，保护层121a、121b(辅助层)也采用铜，进一步提到电连接性能。但不限于本实施例，可以根据需要，可以采用其他材料，可以单独设置提供保护的保护层121a、121b或者辅助电连接的辅助层。其中，保护层121a、121b(辅助层)与电路层110a、110b电连接，导电层400a、400b将器件引脚210a、210b和电路引脚电连接。保护层121a、121b(辅助层)直接与电路引脚电连接，电连接效果好，并且可以延长电路引脚，缩小导电层400a、400b的体积，有利于导电层400a、400b的制作，也利于降低成本。
本实施例中，还可以是，采用电镀的方式制作导电层400a、400b，在电镀前，采用溅镀或者蒸镀的工艺制作辅助层。溅镀或者蒸镀的辅助层能够更好地与电路引脚电连接，电镀的导电层400a、400b附着于辅助层，一方面可以更好的电镀，另一方面通过辅助层能够更好的实现导电层400a、400b与电路引脚电连接。并且溅镀、蒸镀、电镀可以对基板100上的所有元器件200同时进行，提高效率。
本实施例中，预先在基板100制作好电路层110a、110b，但不限于此，也可以在集成电路封装时再在基板100上制作电路层110a、110b，例如，在基板100的底面设置脱模层，脱模层具有与电路层110a、110b轮廓类似的模型槽，在制作连接通孔120a、120b后，在制作导电层400a、400b的同时在模型槽内形成电路层110a、110b。
以电镀制作方式为例，导电层400a和400b、电路层110a和110b采用相同的材料制作，在电镀导电层400a、400b的同时，也在模型槽内和脱模层表面电镀一层导电层，然后除去脱模层以及其表面的导电层，就可以形成基板表面电路层110a、110b。采用电镀的方式制作导电层400a、400b的工艺还包括在 电镀前，采用溅镀或者蒸镀的工艺制作在连接通孔120a和120b内、器件引脚210b和210c表面辅助层，然后再电镀。溅镀或者蒸镀的辅助层能够更好地与电路引脚电连接，电镀的导电层400a、400b附着于辅助层。溅镀或者蒸镀辅助层，一方面可以提高电镀的质量，另一方面也能够更好地实现导电层400a、400b与电路引脚的电连接。
实施例二
实施例二与实施例一的区别在于：
预先在基板100上制作好连接通孔120a、120b，再将元器件200安装于基板100。如图5至9所示，具体步骤为，基板100上设有预制好的连接通孔120a、120b如图5所示，将元器件200安放于基板100，使元器件200的器件引脚210a、210b与连接通孔120a、120b的第一开口120c对接，如图6所示，本实施例中，元器件200与基板100之间设有绝缘介质300(本实施例中，绝缘介质300也是粘装膜，同时起到隔离元器件200与基板100、将元器件200粘贴于基板100的作用，但不限于此)，在绝缘介质300上开设附加通孔，附加通孔与器件引脚210a、210b、连接通孔120a、120b的第一开口120c对接，如图7所示，在连接通孔120a、120b内制作导电层400a、400b，导电层400a、400b深入附加通孔将器件引脚210a、210b和电路引脚电连接，如图9所示。前述器件引脚210a、210b与连接通孔120a、120b的第一开口120c对接，不一定是严格对正，只要满足可以通过附加通孔与连接通孔120a、120b将器件引脚210a、210b与导电层400a、400b电连接即可。
如图10所示，本实施例中，保护层121a、121b(辅助层)与电路层110a、110b电连接；如图11所示，将元器件200安放于基板100上，粘装膜(绝缘介质300)将元器件200粘贴于基板100；如图12所示，在粘装膜(绝缘材料)制作辅助通孔；如图13所示，在连接通孔120a、120b内制作导电层400a、400b，导电层400a、400b将器件引脚210a、210b和电路引脚电连接。辅助层(保护层121a、121b)直接与电路引脚电连接，电连接效果好，并且可以延长 电路引脚，缩小导电层400a、400b的体积，有利于导电层400a、400b的制作，也利于降低成本。
实施例三
实施例三与实施例一的区别在于：
所述基板100包括至少两个基片101，至少两个所述基片101层叠设置，所述基片101的顶面设有所述电路层110a、110b、或/和所述基片101的底面设有所述电路层110a、110b，至少一个所述基片101设有过孔，至少两个所述电路层110a、110b通过所述过孔电连接。扩展元器件200连接范围，在较小的电路体积实现更多的电路连接。
在制作所述导电层400a、400b后，在所述基板100的底面制作与所述导电层400a、400b电连接的导电连接端口500，如图14所示，所述导电连接端口500为焊球点阵、或连接点阵、或金属引脚网格。元器件200的器件引脚210c与基板100的底面的导电连接端口500相连接，可以大大扩展器件引脚201c的连接空间，方便元器件200与外部电路的连接。一般为了减小体积，元器件200会做得尽量小，可供器件引脚210c进行对外连接的空间很小，通过所述导电连接通孔400、400a、400b以及基板底面或顶面或基板内部的所述电路层110a、110b，元器件的引脚210c可以延伸到基板底面的外接导电连接端口500，大大扩展了元器件的连接空间。这样设计的直接好处就是可以更高密度地设置接入、接出数据通讯通道，同时提高通讯带宽和传输速度。
实施例四
实施例四与实施例一的区别在于：
元器件为芯片，器件引脚为芯片引脚。基板设有多个连接通孔，为描述简洁、清楚，将这些连接通孔分别记为第一通孔、第二通孔，每个连接通孔内设有相应的导电层，为描述简洁、清楚，分别记为第一通孔内设有第一导电层、第二通孔内设有第二导电层、第三通孔内设有第三导电层。根据电路的原理， 第一电路层和第二电路层可以是连线，这些连线与芯片或元器件等电连接或不连接，本实施例中电路层包括件多个连线，为描述清楚、简洁，将这些连线分别记为第一连线、第二连线、第三连线。
如图14所示，芯片201设有芯片引脚211a、211b、211c，基板100的顶面设有第一连线111b和第三连线111d，基板的底面设有第二连线111a、111c。
本实施例中，第一连线111b和第三连线111d设于基板100的顶面，第二连线111a、111c设于基板100的底面，此时可以认为，在基板100的厚度方向上，第一连线111b和第三连线111d与芯片201的距离小于第二连线111a、111c与芯片的距离。但不限于此，还可以将第一连线111b、第二连线111a、111c和第三连线111d嵌设于基板100的内部，只要满足在基板100的厚度方向上，第一连线111b与芯片201的距离小于第二连线与芯片201的距离，此时，第一连线111b、第二连线111a、111c在基板100的厚度方向上形成两个连线的“层”。
如图14、15所示在基板100的顶面设置一层粘装膜300，将芯片通过粘装膜300粘贴于基板100的顶面。采用粘装膜300粘贴的方式，将芯片201安放于基板100上，就可以实现芯片201固定于基板100，节约步骤、提高效率、降低成本。粘装膜300可以是绝缘的，这样在即使基板100顶面设有连线的情况下，芯片引脚211a、211b、211c也能与基板100顶面的连线电绝缘。
基板100上设有第一通孔121b，第一连线111b与第一通孔121b对应，第一通孔121b内设有第一导电层401b，第一导电层401b将第一连线111b与芯片引脚211b电连接。第一导电层401b未在图中示出。不限于本实施例，可以有两个以上的芯片引脚211b与第一连线111b电连接。
基板100设有第二通孔121a、121c，第二通孔121a、121c与第二连线121a、121c对应，第二通孔121a、121c内设有第二导电层401a、401c，第二连线121a、121c的部分位于第二通孔121a、121c开口附近或者伸入第二通孔121a、121c，使得第二连线121a、121c可以与第二导电层401a、401c电连接。其中，芯片引脚211b与第一连线111b电连接，并且第一导电层401b将芯片引 脚211b与第一连线121b电连接；芯片引脚211a、211c与第二通孔121a、121c的第一开口对应，并且第二导电层401a、401c将芯片引脚211a、211c与第二连线121a、121c电连接。不限于本实施例，也可以有两个以上的芯片引脚与第二连线121a、121c电连接。
基板100设有第三连线111d和第三通孔121d，第三通孔121d内设有第三导电层401d，在基板100的厚度方向上，第三连线111d与芯片201的距离小于(不限于本实施例，也可以大于)第二连线121a、121c与芯片201的距离，本实施例中，第三连线111d和第一连线111b均设于基板100的顶面，相当于第三连线111d与第一连线111b位于基板100厚度方向上的同一“层”，第二连线121a、121c设于基板100的底面，在基板100的顶面和底面涂布金属层，然后用光刻胶同步制作第一连线111b、第二连线121a、121c、第三连线111d，提高生产效率。但不限于本实施例，第三连线111d可以与第一连线111b也可以不在同一“层”。
在第三通孔121d内设置第三导电层401d，第二连线为至少一个，其中至第二连线121a的一端与第二通孔121a对应并且通过第二导电层401a与芯片引脚211a电连接、另一端与第三通孔121d对应并且通过第三导电层401d与第三连线111d电连接。这样，芯片引脚211a、211c通过第二通孔121a、121c从密集的芯片引脚包围中逃逸到第二连线121a、121c所在层，然后第二连线121a通过第三通孔121d逃逸到第三连线111d所在层，根据需要，设计第三连线111d和第二连线121a、121c的所在的层次以及走线的图案，可以尽可能多的帮助芯片引脚逃逸出来获得连接，从而提高芯片引脚的密度、提高芯片201的连接节点密度，进而提高芯片201数据传输速度。不限于本实施例，也可以有两个以上的第二连线121a、121c与第三连线111d电连接。
首先，通过第二通孔121a、121c内的第二导电层401a、401c将芯片引脚211a、211c与第二连线121a、121c相连接，并从第二通孔121a、121c的第二开口设置第二导电层401a、401c，可以避开芯片201对芯片引脚211a、211c的遮挡，使第二通孔121a、121c与芯片引脚精准定位，可以提高连接的精度， 并且可以批量制作第二通孔121a、121c、批量设置多个芯片201，大幅提高生产效率；第二导电层401a、401c设于第二通孔121a、121c内，不占用额外空间，可以大幅减小封装后整体的体积，特别是，能够可靠使用柔性电路板作为基板100是一个很大的优势。
其次，传统连线方式如图17所示，将连线111a、111b、111c全部设于基板100的顶面，只能在一个单一的平面上将的芯片引脚211a、211b、211c引出，此时连线111a、111b、111c需要穿行在芯片引脚211a、211b、211c之间，并且要避开芯片引脚211a、211b、211c，导致芯片引脚之间需要预留足够的间隙供连线穿过，这样芯片引脚的间隙D1就限制了连线的数量，不能获得更过的连线，并且，如果芯片引脚的数量很多，那么靠近芯片201边沿的芯片引脚可以由连线引出、但就已经没有空隙可以设置连线将靠近芯片201中部的芯片引脚引出，所以传统连线方式限制可连线密度、芯片引脚的密度。但本发明中，如图16所示，芯片引脚分别通过第一连线111b和第二连线121a、121c引出，并且第一连线111b、第二连线121a、121c在基板100的厚度方向上处于不同的厚度层，二者之间不相干涉，第二连线121a、121c不需要经过芯片引脚之间的间隙D2，可以获得得更高密度的连线，同理，可以设置更高密度的芯片引脚，芯片201获得更高密度的连接节点，提高芯片201的数据传输速度。
通过第二通孔121a、121c的第二开口在第二通孔121a、121c内制作第二导电层401a、401c的过程中，将导电粘接材料从第二通孔121a、121c的第二开口送入第二通孔121a、121c内，使导电粘接材料粘接于第二通孔121a、121c的内壁和芯片引脚211a、211c上构成第二导电层401a、401c。采用从第二开口送入导电粘接材料的方式，可以在基板100的底面进行操作，而不会被芯片201干扰。通过使用导电性的粘接材料，在第二通孔121a、121c内把顶层的芯片牢固地粘接到基板100上避免器件脱落的同时，形成从芯片的芯片引脚211a、211c到第二导电层111a、111c的导电通道，以获得好的导电连接性能。导电粘接材料为焊球、或焊锡膏、或导电胶、或导电金属浆。可以根据工艺需要或者基板100材质、第二通孔121a、121c内壁的尺寸、表面材料性质，选择 一种或多种的组合。放入导电粘接材料形成导电性连接通道的工艺，可能使用常见的焊接工艺，包括表面清洁、助焊剂喷涂、使用置球机精密放置焊球和热处理等步骤；也可能使用更特别的化学表面清洁，表面处理，精密喷涂焊锡膏、导电胶或导电金属浆，然后热处理以形成机械和电连接。
通过第二通孔121a、121c的第二开口在第二通孔121a、121c内制作第二导电层401a、401c的过程中，采用丝网印刷在第二通孔121a、121c内设置导电粘接材料。设备通用、可以和第二连线111a、111c的制作同步进行，节约工艺流程，进一步降低成本。
通过第二通孔121a、121c的第二开口在第二通孔121a、121c内制作第二导电层401a、401c的过程中，通过第二通孔121a、121c的第二开口，使用激光烧熔、等离子清洁、或化学溶剂在粘装膜300制作附加通孔，附加通孔将第二通孔121a、121c与芯片引脚211a、211c对接，第二导电层401a、401c伸入附加通孔内，避免粘装膜300阻碍芯片引脚211a、211c、第二导电层401a、401c、以及第二连线111a、111c的电连接。
在第二通孔121a、121c的内壁设有保护层，保护层用于在制作附加通孔时保护基板100。制作附加通孔可以但不限于使用化学蚀刻、或钻孔的工艺，此时需要穿过第二通孔121a、121c，可能会对第二通孔121a、121c的内壁造成损伤，进而对基板100造成损伤，保护层可以保护第二通孔121a、121c的内壁不受损伤。进一步的，保护层可以是有助于第二导电层401a、401c电连接的材料，此时保护层可以与第二连线121a、121c电接触，有助于第二连线121a、121c与第二导电层401a、401c的电连接。譬如，保护层可以是金属薄膜，被预先溅镀或蒸镀在第二通孔121a、121c的内壁，这样可以在化学蚀刻过程中，保护第二通孔121a、121c内壁材料不至于被暴露于蚀刻溶剂或离子中，而且这样的金属薄层也可以提高随后在第二通孔121a、121c中电镀的第二导电层401a、401c的导电性。
可以采用在第二通孔121a、121c内制作第二导电层401a、401c的方法来在第一通孔121b内制作第一导电层401b、在第三通孔121d内制作第三导电层 401d，也可以采用与上述类似的方法制作附加通孔、保护层。优选的，在第一通孔121b、第二通孔121a、121c、第三通孔121d内同步制作第一导电层401b、第二导电层401a、401c、第三导电层401d，提高生产效率。
本实施例中芯片引脚分别通过第一通孔121b和第二通孔121a、121c分别逃逸到第一连线111b和第二连线121a、121c所在层次进行电连接，第一连线111b和第二连线121a、121c在基板100的厚度方向上形成两“层”，但不限于此，也可以设置三层或三层以上的连线“层”，通过前述“孔连接”的方式将芯片引脚与第三、四、…、n层连线电连接，使更多的芯片引脚可以从其周围芯片引脚的包围中逃逸出来进行电连接，从而可以增加芯片引脚的密度，提高芯片201数据传输的速度。
本实施例中，第二通孔121a、121c将芯片引脚211a、211c和第二连线121a、121c电连接的方式构成“孔连接”，采用与前述“孔连接”类似的方式通过第一通孔121b将芯片引脚211b和第一连线111b电连接。但不限于此，也可以用其他方式实现芯片引脚211b和第一连线111b电连接，例如芯片引脚211b和第一连线111b直接接触连接。
根据需要，基板100可以是普通硬质板，基板100也可以是柔性电路板；当基板100是柔性电路板时，通过“孔连接”的方式将芯片引脚引出在连接，可以提高芯片引脚的密度，从而减小芯片201的体积，并且第一导电层401b和第二导电层401a、401c分别位于第一通孔121b和第二通孔121a、121c内，不占用额外的体积，芯片201可基板100之间甚至不需要预留间隙(但不限于此，根据需要也可以设置间隙，例如粘装层)，可以减小芯片201和基板100构成的整体的厚度，当基板100为柔性电路板或多层柔性电路板时，可以保持整体的柔性，可以用于可穿戴设备等。当基板100包括至少两层层叠设置的柔性电路板时优选的，如果设置了两“层”以上的连线，可以先将第一连线111b、或第二连线121a、121c、、第三连线121d、或其他的连线设置于相邻两层柔性电路板之间，再制作第一通孔121b、第二通孔121a、121c、第三通孔121d。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种芯片连线方法，其特征在于，包括：基板设有第一连线和第二连线，在所述基板的厚度方向上，所述第一连线与所述芯片的距离小于所述第二连线与所述芯片的距离，将芯片设于所述基板的顶面，所述芯片设有至少两个芯片引脚，所述基板设有第二通孔，所述第二通孔与所述第二连线对应，所述第二通孔内设有第二导电层；
    其中，至少一个所述芯片引脚与所述第一连线电连接，另有至少一个所述芯片引脚与所述第二通孔的第一开口对应、并且所述第二导电层将所述芯片引脚与所述第二连线电连接。
  2. 根据权利要求1所述的芯片连线方法，其特征在于，所述基板设有第三连线和第三通孔，在所述基板的厚度方向上，所述第三连线与所述芯片的距离大于或小于所述第二连线与所述芯片的距离，在所述第三通孔内设置第三导电层，所述第二连线为至少一个，其中至少一个所述第二连线的一端与所述第二通孔对应并且通过所述第二导电层与所述芯片引脚电连接、另一端与所述第三通孔对应并且通过所述第三导电层与所述第三连线电连接。
  3. 根据权利要求2所述的芯片连线结构，其特征在于，在所述基板的顶面设置所述芯片、所述第一连线、和所述第三连线，在所述基板的底面设置所述第二连线。
  4. 根据权利要求1所述的芯片连线方法，其特征在于，通过所述第二通孔的第二开口在所述第二通孔内制作第二导电层的过程中，将所述第二导电层从所述第二通孔的第二开口送入所述第二通孔内。
  5. 根据权利要求4所述的芯片连线方法，其特征在于，所述第二导电层为焊球、或焊锡膏、或导电胶；
    或者，所述第二导电层为金属层，采用沉金、溅射、或电镀的方法制作所述金属层。
  6. 根据权利要求4所述的芯片连线方法，其特征在于，采用丝网印刷在所述第二通孔内设置所述导电粘接材料。
  7. 根据权利要求1所述的芯片连线方法，其特征在于，在所述芯片与所述基板之间设置粘装膜，所述粘装膜将所述芯片件粘贴于所述基板。
  8. 根据权利要求7所述的芯片连线方法，其特征在于，通过所述第二通孔的第二开口，使用激光烧熔、等离子清洁、或化学溶剂在所述粘装膜制作附加通孔，所述附加通孔将所述第二通孔与所述芯片引脚对接，所述第二导电层伸入所述附加通孔内。
  9. 根据权利要求8所述的芯片连线方法，其特征在于，在所述第二通孔的内壁设置保护层，所述保护层用于在制作所述附加通孔时保护所述基板。
  10. 根据权利要求1至9任一项所述的芯片连线方法，其特征在于，所述基板上设有第一通孔，所述第一连线与所述第一通孔对应，所述第一通孔内设有第一导电层，所述第一导电层将所述第一连线与所述芯片引脚电连接。
  11. 根据权利要求1至9任一项所述的芯片连线方法，其特征在于，所述基板为柔性电路板；或者，所述基板包括至少两层层叠设置的柔性电路板。
  12. 一种芯片连线结构，其特征在于，包括：
    芯片设于基板的顶面，所述基板设有第一连线和第二连线，在所述基板的厚度方向上，所述第一连线与所述芯片的距离小于所述第二连线与所述芯片的距离，所述芯片设有至少两个芯片引脚，所述基板设有第二通孔，所述第二通孔与所述第二连线对应，所述第二通孔内设有第二导电层；
    其中，至少一个所述芯片引脚与所述第一连线电连接，另有至少一个所述芯片引脚与所述第二通孔对应、并且所述第一导电层将所述芯片引脚与所述第二连线电连接。
  13. 根据权利要求12所述的芯片连线结构，其特征在于，所述基板上设有第一通孔，所述第一连线与所述第一通孔对应，所述第一通孔内设有第一导电层，所述第一导电层将所述第一连线与所述芯片引脚电连接。
  14. 根据权利要求12所述的芯片连线结构，其特征在于，所述基板设有第三连线和第三通孔，所述第三通孔内设有第三导电层，在所述基板的厚度方向上，所述第三连线与所述芯片的距离大于或等于所述第二连线与所述芯片的 距离，所述第二连线为至少一个，其中至少一个所述第二连线的一端与所述第一通孔对应、另一端与所述第二通孔对应，所述第二连线的一端通过所述第二导电层与所述芯片引脚电连接、另一端通过所述第三导电层与所述第三连线电连接。
  15. 根据权利要求14所述的芯片连线结构，其特征在于，所述芯片、所述第一连线、和所述第三连线设于所述基板的顶面，所述第二连线设于所述基板的底面。
  16. 根据权利要求11至15任一项所述的芯片连线结构，其特征在于，所述芯片和所述第一连线设于所述基板的顶面，所述第二连线设于所述基板的底面。
  17. 根据权利要求11至15任一项所述的芯片连线结构，其特征在于，所述基板为柔性电路板；或者，所述基板包括至少两层层叠设置的电路板。
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