CN109937614A - 芯片连线方法及结构 - Google Patents

芯片连线方法及结构 Download PDF

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Publication number
CN109937614A
CN109937614A CN201780070448.2A CN201780070448A CN109937614A CN 109937614 A CN109937614 A CN 109937614A CN 201780070448 A CN201780070448 A CN 201780070448A CN 109937614 A CN109937614 A CN 109937614A
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line
chip
hole
substrate
conductive layer
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CN109937614B (zh
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胡川
刘俊军
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Shenzhen Xiuyuan Electronic Technology Co ltd
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Shenzhen Xiuyuan Electronic Technology Co ltd
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32235—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/8301—Cleaning the layer connector, e.g. oxide removal step, desmearing
    • H01L2224/83013—Plasma cleaning
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/8303—Reshaping the layer connector in the bonding apparatus, e.g. flattening the layer connector
    • H01L2224/83031—Reshaping the layer connector in the bonding apparatus, e.g. flattening the layer connector by chemical means, e.g. etching, anodisation
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
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    • H01L2224/9212—Sequential connecting processes
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate

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  • Production Of Multi-Layered Print Wiring Board (AREA)
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Abstract

一种芯片(201)连线方法及结构，其中芯片(201)连线方法包括：所述基板(100)设有第一连线(111b)和第二连线(111a、111c)，在所述基板(100)的厚度方向上，所述第一连线(111b)与所述芯片(201)的距离小于所述第二连线(111a、111c)与所述芯片(201)的距离，将芯片(201)设于所述基板(100)的顶面，所述芯片(201)设有至少两个芯片引脚(211a、211b、211c)，所述基板(100)设有第二通孔(121a、121c)，所述第二通孔(121a、121c)与所述第二连线(111a、111c)对应，所述第二通孔(121a、121c)内设有第二导电层(401a、401c)；其中，至少一个所述芯片引脚(211a、211b、211c)与所述第一连线(111b)电连接，另有至少一个所述芯片引脚(211a、211b、211c)与所述第二通孔(121a、121c)的第一开口(120c)对应、并且所述第二导电层(401a、401c)将所述芯片引脚(211a、211b、211c)与所述第二连线(111a、111c)电连接。连线绕过芯片引脚(211a、211b、211c)的遮挡，可以获得高密度的芯片引脚(211a、211b、211c)、连线，提高芯片(201)连接的节点数量，提高芯片(201)数据传输速度。

Description

PCT国内申请，说明书已公开。

Claims (17)

  1. PCT国内申请，权利要求书已公开。
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