CN106252333A - 多元件封装体与其制备方法 - Google Patents

多元件封装体与其制备方法 Download PDF

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Publication number
CN106252333A
CN106252333A CN201510534702.2A CN201510534702A CN106252333A CN 106252333 A CN106252333 A CN 106252333A CN 201510534702 A CN201510534702 A CN 201510534702A CN 106252333 A CN106252333 A CN 106252333A
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China
Prior art keywords
layer
remapping
wafer
multicomponent packaging
multicomponent
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Granted
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CN201510534702.2A
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CN106252333B (zh
Inventor
管式凡
罗翊仁
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Micron Technology Inc
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Inotera Memories Inc
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Abstract

本发明公开了一种多元件封装体与其制备方法，多元件封装体包含基板、至少两个元件区域、第一重布局层、外部晶片以及多个第一连接件。此两个元件区域自基板形成，而第一重布局层设置于基板上，并电性连接至此两个元件区域。外部晶片设置于第一重布局层上，而多个第一连接件设置于第一重布局层与外部晶片之间，以连接第一重布局层与外部晶片。本发明的多元件封装体中的基板与元件区域之间不具有任何界面使元件区域能直接集成，降低元件区域断线或损坏的风险。

Description

多元件封装体与其制备方法
技术领域
本发明涉及一种多元件封装体及其制造方法。
背景技术
随着半导体元件制造技术演进，半导体元件的电路密度不断增加且元件尺寸也进一步微缩以得到高集成密度的半导体元件。如此一来，在半导体元件的尺寸减少与密度增加的情况下，对于封装技术的要求也对应地渐驱严苛。近年来随着对尺寸更小的电子装置需求的成长，对于半导体晶片需要更创新的封装技术。
通常会在晶圆上制备多个元件，并以切割工艺将晶圆上的多个元件分离成独立的晶片。此些晶片会置放于乘载基板上，再进行封装工艺以集成多个晶片于一个封装体中。然而，在置放晶片于乘载基板上的过程中会产生震动，使得晶片易产生断线或损坏的问题并降低了封装体的良率。此外，使用乘载基板需耗费额外的成本，此更降低了封装工艺的效率。据此，业界亟需一种新颖的封装体结构与其制备方法以解决上述的问题。
发明内容
本发明的目的在于提供一种多元件封装体与其制备方法，以集成至少两个元件区域于一个多元件封装体中，而不需使用任何乘载基板，因此多元件封装体中的基板与元件区域之间不具有任何界面。
本发明的一实施例提供一种多元件封装体，其包含基板、至少两个元件区域、第一重布局层、外部晶片以及多个第一连接件。此两个元件区域自基板形成，而第一重布局层设置于基板上，并电性连接至此两个元件区域。外部晶片设置于第一重布局层上，而多个第一连接件设置于第一重布局层与外部晶片之间，以连接第一重布局层与外部晶片。
根据本发明一个或多个实施方式，多元件封装体还包含多个第二连接件设置于第一重布局层上。
根据本发明一个或多个实施方式，第二连接件的直径大于第一连接件的直径与外部晶片的厚度的总和。
根据本发明一个或多个实施方式，多元件封装体还包含封胶层、第二重布局层以及多个第三连接件。封胶层覆盖外部晶片与第一重布局层，第二重布局层设置于封胶层上，而此些第三连接件设置于第二重布局层上。
根据本发明一个或多个实施方式，封胶层包含第一导电接触通过封胶层以连接第一重布局层与第二重布局层。
根据本发明一个或多个实施方式，封胶层包含第二导电接触通过封胶层与外部晶片以连接第一重布局层与第二重布局层。
根据本发明一个或多个实施方式，第一重布局层与第二重布局层包含介电层、多个金属层以及多个导电柱。此些金属层于介电层中呈平行排列，而此些导电柱同样位于介电层中并电性连接相邻的两个金属层。
根据本发明一个或多个实施方式，封胶层包含环氧树脂。
本发明的一实施例提供一种多元件封装体，其包含基板、至少两个元件区域、第一重布局层、外部晶片、第二重布局层以及封胶层。此两个元件区域自基板形成，而第一重布局层设置于基板上。外部晶片设置于第一重布局层上，而第二重布局层设置于第一重布局层上。封胶层设置于第一重布局层与第二重布局层之间，且封胶层包含第一导电接触与第二导电接触。第一导电接触通过封胶层，而第二导电接触通过封胶层与外部晶片，且第一导电接触与第二导电接触连接第一重布局层与第二重布局层。
本发明的一实施例提供一种多元件封装体的制备方法，其包含下列步骤。先在晶圆上形成第一重布局层，晶圆具有至少两个元件区域，且第一重布局层电性连接至此两个元件区域。接着在第一重布局层上形成多个第一连接件，并在此些第一连接件上配置外部晶片，以使外部晶片借由此些第一连接件电性连接至第一重布局层。
根据本发明一个或多个实施方式，多元件封装体的制备方法还包含在第一重布局层上形成多个第二连接件，且第二连接件的直径大于第一连接件的直径与外部晶片的厚度的总和。
根据本发明一个或多个实施方式，多元件封装体的制备方法还包含下列步骤。形成暂时粘着层覆盖第二连接件与外部晶片并薄化晶圆，最后再移除暂时粘着层。
根据本发明一个或多个实施方式，多元件封装体的制备方法还包含沿着切割道切割晶圆以形成多元件封装体。
根据本发明一个或多个实施方式，外部晶片具有第一穿孔。
根据本发明一个或多个实施方式，多元件封装体的制备方法还包含下列步骤。形成封胶层覆盖第一重布局层与外部晶片，并移除部分的封胶层以形成第二穿孔与第三穿孔。其中第二穿孔暴露第一重布局层，而第三穿孔贯通第一穿孔以暴露第一重布局层。之后再填充导电材料至第一穿孔、第二穿孔与第三穿孔中以形成第一导电接触与第二导电接触。
根据本发明一个或多个实施方式，多元件封装体的制备方法还包含下列步骤。形成第二重布局层于封胶层上，且第二重布局层电性连接至第一导电接触与第二导电接触。之后再在第二重布局层上形成多个第三连接件。
根据本发明一个或多个实施方式，多元件封装体的制备方法还包含下列步骤。形成暂时粘着层覆盖第三连接件与第二重布局层并薄化晶圆，最后再移除暂时粘着层。
根据本发明一个或多个实施方式，多元件封装体的制备方法还包含沿着切割道切割晶圆以形成多元件封装体。
根据本发明一个或多个实施方式，在晶圆上形成第一重布局层包含下列步骤。沉积介电材料覆盖晶圆，再移除部分的介电材料以形成多个开口暴露晶圆中的此些元件区域。之后在此些开口中形成多个导电柱，并在此些导电柱上形成金属层后再图案化金属层。
根据本发明一个或多个实施方式，在晶圆上形成第二重布局层包含下列步骤。沉积介电材料覆盖封胶层，再移除部分的介电材料以形成多个开口暴露第一导电接触与第二导电接触。之后在此些开口中形成多个导电柱，并在此些导电柱上形成金属层后再图案化金属层。
与现有技术相比，本发明具有如下有益效果：本发明的多元件封装体及其制造方法，以集成至少两个元件区域于一个多元件封装体中，而不需使用任何乘载基板，因此多元件封装体中的基板与元件区域之间不具有任何界面。再者，晶圆中的元件区域是直接集成，从而可降低元件区域断线或损坏的风险。总结以上数点，省略乘载基板的使用降低了多元件封装体的成本，从而封装工艺的效率还大幅增加并提升了多元件封装体的良率。
附图说明
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂，所附图式的详细说明如下：
图1A为依据本发明的部分实施方式中一种多元件封装体的俯视图；
图1B为本发明的部分实施方式中，图1A的多元件封装体沿着AA剖线的剖视图；
图2A为依据本发明的部分实施方式中一种多元件封装体的俯视图；
图2B为本发明的部分实施方式中，图2A的多元件封装体沿着AA剖线的剖视图；
图2C为本发明的部分实施方式中外部晶片的立体示意图；
图2D为本发明的其他部分实施方式中一种多元件封装体的剖视图；
图3A至图3D为依据本发明的部分实施方式中，图1A与图1B的多元件封装体在工艺各个阶段的剖视图；
图4A至图4F为依据本发明的部分实施方式中，图2A与图2B的多元件封装体在工艺各个阶段的剖视图；以及
图5为依据本发明的部分实施方式中，图2D的多元件封装体在工艺的中间阶段的剖视图。
具体实施方式
之后将以示例图式以详细描述本发明的各种实施方式，且在图式和说明书中使用相同的元件符号以指代相同或相似的部分。
以下将以图式公开本发明的多个实施方式，为明确说明起见，许多实务上的细节将在以下叙述中一并说明。然而，应了解到，这些实务上的细节不应用以限制本发明。也就是说，在本发明部分实施方式中，这些实务上的细节是非必要的。此外，为简化图式起见，一些现有惯用的结构与元件在图式中将以简单示意的方式绘示。
请参阅图1A与图1B。图1A为依据本发明的部分实施方式中一种多元件封装体的俯视图，而图1B为本发明的部分实施方式中，图1A的多元件封装体沿着AA剖线的剖视图。如图1A与图1B所示，多元件封装体100包含基板110、至少两个元件区域120、第一重布局层130、外部晶片140、多个第一连接件150与多个第二连接件160。
此些元件区域120自基板110形成，因此元件区域120与基板110之间无任何介面(interface)。通常会切割晶圆以将其上的多个元件区域分离成独立的晶片，并将此些晶片置放于乘载基板上，因此会形成介面于乘载基板与晶片之间。接着再进行封装工艺以集成多个晶片于一个封装体中。然而在置放晶片于乘载基板上的过程中会产生震动，使得晶片易产生断线或损坏的问题并降低了封装体的良率。此外，使用乘载基板需花费额外的成本，此更降低了封装工艺的效率。相对于先前技术，本发明的多元件封装体100是以晶圆级(wafer-level)封装工艺所制备。晶圆级封装是指在晶圆中形成此些元件区域120后，再封装与测试整片晶圆中的元件，之后再切割晶圆而形成图1A与图1B所示的多元件封装体100。值得注意的是，晶圆中的此些元件区域120在切割前即先进行直接集成，因此可省略使用乘载基板，且元件域120与基板110之间无任何界面。
每一个元件区域120包含半导体元件、层间介电层(inter-layer dielectric(ILD)layer)覆盖半导体元件、内金属介电层(inter-metal dielectric(IMD)layer)位于层间介电层上、以及金属内连结构设置于内金属介电层中并电性连接至半导体元件。此外，每一个元件区域120具有导电垫122，其为金属内连结构的最上层金属层。在本发明的部分实施方式中，基板110形成自晶圆，而晶圆的材质包含硅、锗、或其他的III-V族元素，但不以此为限。在本发明的其他实施方式中，半导体元件为记忆体元件，但不以此为限，其他的半导体元件同样适用于本发明。
继续参阅图1B，第一重布局层130设置于基板110上并电性连接至少两个元件区域120。第一重布局层130与元件区域120的导电垫122接触，以使此些元件区域120借由第一重布局层130彼此电性连接。再参阅图1A，图1A绘示的多元件封装体100中具有四个元件区域120，而第一重布局层130电性连接这四个元件区域120。举例来说，元件区域120中的半导体元件可为记忆体元件，且每一个元件区域120可提供2G(gigabyte)的储存容量。第一重布局层130则集成此四个元件区域120而达到8G的储存容量，但不以此为限。
再者，第一重布局层130还可重新分配或重新定位信号至外部设备或输入/输出连结的配置处。第一重布局层130包含介电层132、多个金属层134与多个导电柱136。此些金属层134于介电层132中呈平行排列，而导电柱136同样位于介电层132以电性连接相邻的两个金属层134。值得注意的是，金属层134还借由导电柱136以电性连接至元件区域120的导电垫122，因此可借由导电垫122、导电柱136与金属层134以电性连接至少两个元件区域120。此外，可依据设计需求预先决定导电层136的数量。在本发明的部分实施方式中，导电柱136与金属层134的材质包含铝、铜、或其组合，但不以此为限。其他合适的导电材料同样可用于形成导电柱136与金属层134。在本发明的其他实施方式中，介电层132的材质包含氧化硅、氮化硅、氮氧化硅、或其组合，但不以此为限。其他合适的绝缘材料同样可用于形成介电层132。
继续参阅图1A与图1B，外部晶片140设置于第一重布局层130上，而多个第一连接件150位于第一重布局层130与外部晶片140之间以连接第一重布局层130与外部晶片140。如前所述，第一重布局层130电性连接至少两个元件区域120，而第一连接件150设置于第一重布局层130上并接触第一重布局层130。外部晶片140则设置于第一连接件150上并接触第一连接件150，因此外部晶片140能借由第一连接件150、第一重布局层130与导电垫122而电性连接至此些元件区域120。借此，外部晶片140即可接收元件区域120的信号并进行运算操作。
继续参阅图1A与图1B，多个第二连接件160设置于第一重布局层130上。如图1A所示，此些第二连接件160环绕外部晶片140。第二连接件160设置于第一重布局层130上并接触第一重布局层130以使外部晶片140产生的运算结果传输至第二连接件160。此些第二连接件160还传输运算结果至外部装置，例如印刷电路板。在本发明的部分实施方式中，第二连接件160的直径大于第一连接件150的直径与该外部晶片140的厚度的总和，借此让外部晶片140不会与后续形成的印刷电路板接触，以避免错误的电性连接。在本发明的部分实施方式中，第一连接件150与第二连接件可为材质为锡的焊球或焊接凸块，但不以此为限。
继续参阅图2A与图2B。图2A为依据本发明的部分实施方式中一种多元件封装体的俯视图。如图2A与图2B所示，多元件封装体200包含基板210、至少两个元件区域220、第一重布局层230、外部晶片240、多个第一连接件250、封胶层260、第二重布局层270与多个第三连接件280。
此些元件区域220自基板210形成，因此元件区域220与基板210之间无任何介面。本发明的晶片封装体200同样是以晶圆级封装工艺所制备，其是指在晶圆中形成此些元件区域220后，再封装与测试整片晶圆中的元件，之后再切割晶圆而形成图2A与图2B所示的多元件封装体200。值得注意的是，晶圆中的此些元件区域220在切割前即先进行直接集成，因此可省略使用乘载基板，且元件区域220与基板210之间无任何界面。每一个元件区域220包含半导体元件、层间介电层覆盖半导体元件、内金属介电层位于层间介电层上、以及金属内连结构设置于内金属介电层中并电性连接至半导体元件。此外，每一个元件区域220具有导电垫222，其为金属内连结构的最上层金属层。
在本发明的部分实施方式中，基板210形成自晶圆，而晶圆的材质包含硅、锗、或其他的III-V族元素，但不以此为限。在本发明的其他实施方式中，半导体元件为记忆体元件，但不以此为限，其他的半导体元件同样适用于本发明。
继续参阅图2B，第一重布局层230设置于基板210上并电性连接至少两个元件区域220。第一重布局层230与元件区域220的导电垫222接触，以使此些元件区域220借由第一重布局层230彼此电性连接。再参阅图2A，图2A绘示的多元件封装体200中具有四个元件区域220，而第一重布局层230电性连接这四个元件区域220。举例来说，元件区域220中的半导体元件可为记忆体元件，且每一个元件区域220可提供2G的储存容量。第一重布局层230则集成此四个元件区域220而达到8G的储存容量，但不以此为限。
再者，第一重布局层230还可重新分配或重新定位信号至外部设备或输入/输出连结的配置处。第一重布局层230包含介电层232、多个金属层234与多个导电柱236。此些金属层234于介电层232中呈平行排列，而导电柱236同样位于介电层232中以电性连接相邻的两个金属层234。值得注意的是，金属层234还借由导电柱236以电性连接至元件区域220的导电垫222，因此可借由导电垫222、导电柱236与金属层234以电性连接至少两个元件区域220。此外，可依据设计需求预先决定导电层234的数量。在本发明的部分实施方式中，导电柱236与金属层234的材质包含铝、铜、或其组合，但不以此为限。其他合适的导电材料同样可用于形成导电柱236与金属层234。在本发明的其他实施方式中，介电层232的材质包含氧化硅、氮化硅、氮氧化硅、或其组合，但不以此为限。其他合适的绝缘材料同样可用于形成介电层232。
继续参阅图2A与图2B，外部晶片240设置于第一重布局层230上，而多个第一连接件250位于第一重布局层230与外部晶片240之间以连接第一重布局层230与外部晶片240。如前所述，第一重布局层230电性连接至少两个元件区域220，而第一连接件250设置于第一重布局层230上并接触第一重布局层230。外部晶片240则设置于第一连接件250上并接触第一连接件250，因此外部晶片240能借由第一连接件250、多元件封装体200与导电垫222而电性连接至此些元件区域222。借此，外部晶片140即可接收元件区域220的信号并进行运算操作。
多元件封装体100与多元件封装体200之间的差别在于多元件封装体200中并不具有接触第一重布局层230的第二连接件。多元件封装体200具有覆盖第一重布局层230与外部晶片240的封胶层260，且第二重布局层270设置于封胶层260上。封胶层260中具有第一导电接触262以及第二导电接触264。第一导电接触262通过封胶层260，因此其将接触第一重布局层230与第二重布局层270，以连接第一重布局层230与第二重布局层270。再者，第二导电接触264通过封胶层260与外部晶片240，因此其将接触第一重布局层230与第二重布局层270，以连接第一重布局层230与第二重布局层270。在本发明的部分实施方式中，封胶层260的材质包含环氧树脂。
请参阅图2C以更清楚理解外部晶片240的结构。图2C为本发明的部分实施方式中外部晶片的立体图。如图2C所示，外部晶片240具有第一穿孔242贯穿外部晶片240，而第二导电接触264通过封胶层260与此第一穿孔242而接触外部晶片240下方的第一重布局层230，以提高第一重布局层230与第二重布局层270之间的电性连接性质。再者，第一重布局层230与第二重布局层270的线路布局方式可较为弹性，还增加了工艺效率。值得注意的是，第二导电接触264不会接触外部晶片240中的内部线路以避免错误的连接关系。
第二重布局层270包含介电层272、多个金属层274与多个导电柱276。此些金属层274于介电层272中呈平行排列，而导电柱276同样位于介电层272中以电性连接相邻的两个金属层274。值得注意的是，金属层274还借由导电柱276以电性连接至第一导电接触262与第二导电接触264。此外，还可依据设计需求预先决定导电层274的数量。
继续参阅图2A与图2B，多个第三连接件280设置于第二重布局层270上。此些第三连接件280接触第二重布局层270以使外部晶片240产生的运算结果借由第一连接件250、第一重布局层230、第一导电接触262、第二导电接触264与第二重布局层270传输至第三连接件280。此些第三连接件280还传输运算结果至外部装置，例如印刷电路板。此外，借由第二导电接触264的设置，第三连接件280的布局可更为弹性。在本发明的部分实施方式中，第一连接件250与第三连接件285可为材质为锡的焊球或焊接凸块，但不以此为限。
相较于多元件封装体100，多元件封装体200中的第三连接件280的尺寸相似于多元件封装体100中的第二连接件160的尺寸，但第三连接件280的密集度大于第二连接件160。由于第三连接件280与外部晶片240分别设置于不同的层别，此增加置放第三连接件280的空间并提升其密集度。借此，具有较高密集度的第三连接件280还提高多元件封装体200与印刷电路板之间的电性连接性质。
接着参阅图2D，图2D为本发明的部分实施方式中一种多元件封装体的剖视图。图2D绘示多元件封装体200a，并于下文中讨论多元件封装体200a与多元件封装体200之间的差别。在多元件封装体200a中省略了第二重布局层270，因此此些第三连接件280直接设置于封胶层260上。具体而言，每一个第三连接件280均位于封胶层260上并接触第一导电接触262或第二导电接触，以使外部晶片240产生的运算结果借由第一连接件250、第一重布局层230、以及第一导电接触262或第二导电接触264传输至第三连接件280。此些第三连接件280还传输运算结果至其他外部装置，例如印刷电路板。值得注意的是，省略第二重布局层270的好处在于可减少晶片封装体200a的厚度，此外还可提升封胶层260上的第三连接件280的密集度，以提高多元件封装体200a与后续形成的印刷电路板之间的电性连接性质。
请参阅图3A至图3D以清楚理解图1A与图1B中的多元件封装体100的制备方法。图3A至图3D为依据本发明的部分实施方式中，图1A与图1B的多元件封装体在工艺各个阶段的剖视图。
先参阅图3A，在晶圆300上形成第一重布局层130，晶圆300具有至少两个元件区域120，且第一重布局层130电性连接至此两个元件区域120。值得注意的是，每一个元件区域120包含半导体元件、层间介电层覆盖半导体元件、内金属介电层位于层间介电层上、以及金属内连结构设置于内金属介电层中并电性连接至半导体元件。此外，每一个元件区域120具有导电垫122，其为金属内连结构的最上层金属层。第一重布局层130以下列的步骤所形成。先沉积介电材料以覆盖晶圆300，接着使用微影蚀刻工艺移除部分的介电材料，借此形成多个开口以暴露晶圆300中的元件区域120。具体而言，每一个开口对应至元件区域120的一个导电垫122。之后在此些开口中形成多个导电柱136，再在导电柱136上形成金属层134，并依据布局设置(layout design)图案化金属层134以电性连接至少两个元件区域120。上述的步骤可重复多次以制备得第一重布局层130，其具有多个金属层134在介电层132中，且可依据设计需求预先决定导电层134的数量。
参阅图3B，在第一重布局层130上形成多个第一连接件150，并在此些第一连接件150上配置外部晶片140。可使用回焊工艺在第一重布局层130上形成此些第一连接件150，接着再形成外部晶片140接触此些第一连接件150。外部晶片140借由第一连接件150、第一重布局层130与导电垫122电性连接至多个元件区域120，借此外部晶片140即可接收此些元件区域120的信号并进行运算操作。
继续参阅图3C，在第一重布局层130上形成多个第二连接件，并形成暂时粘着层310覆盖第二连接件160与外部晶片140。同样使用回焊工艺在第一重布局层130上形成此些第二连接件160，且第二连接件160的直径大于第一连接件150的直径与外部晶片140的厚度的总和以确保外部晶片140不会与后续形成的印刷电路板接触。在形成第二连接件160后即形成暂时粘着层310，接着再薄化晶圆300以减少其厚度，以让最后形成的多元件封装体具有较小的尺寸。暂时粘着层310具有乘载层314与粘着层312。暂时粘着层310能减少薄化工艺中产生的应力，因此降低了晶圆破裂的风险。在本发明的部分实施方式中，暂时粘着层310为胶带。在本发明的部分实施方式中，晶圆300是以化学机械研磨(chemicalmechanical polishing)工艺进行薄化。
继续参阅图3D，移除暂时粘着层310，并沿着切割道320切割晶圆300以形成图2A与图2B所示的多元件封装体100。可使用合适的溶剂消除粘着层312的粘性以分离暂时粘着层310与晶圆300。之后再沿着切割道320切割晶圆300以形成多个独立的多元件封装体100。值得注意的是，切割道320不会通过第一重布局层130中的金属层134，以避免第一重布局层130的断线。在本发明的部分实施方式中，在移除暂时粘着层310前即先沿着切割道320切割晶圆300。在本发明的其他部分实施方式中，多元件封装体100还借由第二连接件160连接至印刷电路板，而外部晶片140产生的运算结果即可借由第一连接件150、第一重布局层130以及第二连接件160传输至印刷电路板。
请参阅图4A至图4F以清楚理解图2A与图2B中的多元件封装体200的制备方法。图4A至图4F为依据本发明的部分实施方式中，图2A与图2B的多元件封装体在工艺各个阶段的剖视图。
先参阅图4A，在晶圆400上形成第一重布局层230，晶圆400具有至少两个元件区域220，且第一重布局层230电性连接至此两个元件区域220。值得注意的是，每一个元件区域220包含半导体元件、层间介电层覆盖半导体元件、内金属介电层位于层间介电层上、以及金属内连结构设置于内金属介电层中并电性连接至半导体元件。此外，每一个元件区域220具有导电垫222，其为金属内连结构的最上层金属层。形成第一重布局层230的步骤类似于形成第一重布局层130的步骤，其细节在此不再赘述。
参阅图4B，在第一重布局层230上形成多个第一连接件250，并在此些第一连接件250上配置外部晶片240。可使用回焊工艺在第一重布局层230上形成此些第一连接件250，接着再形成外部晶片240接触此些第一连接件250。外部晶片240借由第一连接件250、第一重布局层230与导电垫222电性连接至多个元件区域220，借此外部晶片240即可接收此些元件区域220的信号并进行运算操作。
继续参阅图4C，形成封胶层260覆盖第一重布局层230与外部晶片240，并移除部分的封胶层260以形成第二穿孔412与第三穿孔414。第二穿孔412暴露第一重布局层230，而第三穿孔414贯通外部晶片240的第一穿孔242以暴露第一重布局层230。可涂布或喷洒环氧树脂以形成封胶层260，再使用微影蚀刻工艺移除部分的封胶层260以形成第二穿孔412与第三穿孔414。如前图2C中所述，外部晶片240具有第一穿孔242，而第三穿孔414大致对准于第一穿孔242以暴露外部晶片240下的第一重布局层230。再者，第二穿孔412通过封胶层260并同样暴露第一重布局层230。之后，填充导电材料至第一穿孔242、第二穿孔412与第三穿孔414中以形成第一导电接触262与第二导电接触264。在本发明的部分实施方式中，第一导电接触262与第二导电接触264的材质包含铜、铝、及其组合，但不以此为限。
继续参阅图4D，在封胶层260上形成第二重布局层270。第二重布局层270是以下列的步骤所形成。先沉积介电材料以覆盖封胶层260，接着使用微影蚀刻工艺移除部分的介电材料，借此形成多个开口，每一个开口对应至第一导电接触262或第二导电接触264。之后在此些开口中形成多个导电柱276，再在导电柱276上形成金属层274，并依据布局设置(layout design)图案化金属层274。上述的步骤可重复多次以制备得第一重布局层270，其在介电层272中具有多个金属层274，且可依据设计需求预先决定导电层274的数量。
继续参阅图4E，在第二重布局层270上形成多个第三连接件280，并形成暂时粘着层420覆盖第三连接件280与第二重布局层270。使用回焊工艺在第二重布局层270上形成此些第三连接件280。在形成第三连接件280后即形成暂时粘着层420，接着再薄化晶圆400以减少其厚度，以让最后形成的多元件封装体具有较小的尺寸。暂时粘着层420具有乘载层424与粘着层422。暂时粘着层420能减少薄化工艺中产生的应力，因此降低了晶圆破裂的风险。在本发明的部分实施方式中，暂时粘着层420为胶带。在本发明的部分实施方式中，晶圆400是以化学机械研磨工艺进行薄化。
继续参阅图4F，移除暂时粘着层420，并沿着切割道430切割晶圆400以形成图2A与图2B所示的多元件封装体200。可使用合适的溶剂消除粘着层412的粘性以分离暂时粘着层420与晶圆400。之后再沿着切割道430切割晶圆400以形成多个独立的多元件封装体200。值得注意的是，切割道430不会通过第一重布局层230中的金属层234与第二重布局层270中的金属层274，以避免第一重布局层230与第二重布局层270的断线。在本发明的部分实施方式中，在移除暂时粘着层420前即先沿着切割道430切割晶圆400。在本发明的其他部分实施方式中，多元件封装体200还借由第三连接件260连接至印刷电路板，而外部晶片240产生的运算结果即可借由第一连接件250、第一重布局层230、第一导电接触262、第二导电接触264、第二重布局层270以及第三连接件280传输至印刷电路板。
请继续参阅图5，图5为依据本发明的部分实施方式中，图2D的多元件封装体在工艺的中间阶段的剖视图。具体而言，图5为晶片封装体200a在制造过程中图4C下一阶段的剖面示意图。在形成第一导电接触262与第二导电接触264在封胶层260中后，还使用回焊工艺在封胶层260上形成第三连接件280。值得注意的是，每一个第三连接件280接触第一导电接触262或第二导电接触264，以电性连接至外部晶片240。之后再使用类似于图4E与图4F的薄化工艺与切割工艺，以减少晶圆400的厚度并将晶圆400切割成多个如图2D所示的独立的多元件封装体200a，其细节在此不再详述。
由上述本发明实施例可知，本发明优于现有的封装体结构与制备方法，并总结此些优点如下。本发明提供一种晶圆级封装工艺，以集成至少两个元件区域于一个多元件封装体中，而不需使用任何乘载基板，因此多元件封装体中的基板与元件区域之间不具有任何界面。再者，晶圆中的元件区域是直接集成，从而可降低元件区域断线或损坏的风险。总结以上数点，省略乘载基板的使用降低了多元件封装体的成本，从而封装工艺的效率还大幅增加并提升了多元件封装体的良率。
本发明已经相当详细地描述某些实施方式，但其他的实施方式也为可能的。因此，所附权利要求的精神和范筹不应限于本文所描述的实施方式。
虽然本发明已经以实施方式公开如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作各种变动与润饰，因此本发明的保护范围当视权利要求所界定者为准。

Claims (20)

1.一种多元件封装体，其特征在于，所述多元件封装体包含：
自基板形成的至少两个元件区域；
第一重布局层，其设置于所述基板上，并电性连接至所述两个元件区域；
外部晶片，其设置于所述第一重布局层上；以及
多个第一连接件，其设置于所述第一重布局层与所述外部晶片之间，其以连接所述第一重布局层与所述外部晶片。
2.如权利要求1所述的多元件封装体，其特征在于，所述多元件封装体还包含多个第二连接件，其设置于所述第一重布局层上。
3.如权利要求1所述的多元件封装体，其特征在于，所述第二连接件的直径大于所述第一连接件的直径与所述外部晶片的厚度的总和。
4.如权利要求1所述的多元件封装体，其特征在于，所述多元件封装体还包含：
封胶层，其覆盖所述外部晶片与所述第一重布局层；
第二重布局层，其设置于所述封胶层上；以及
多个第三连接件，其设置于所述第二重布局层上。
5.如权利要求4所述的多元件封装体，其特征在于，所述封胶层包含第一导电接触，其通过所述封胶层，以连接所述第一重布局层与所述第二重布局层。
6.如权利要求5所述的多元件封装体，其特征在于，所述封胶层包含第二导电接触，其通过所述封胶层与所述外部晶片，以连接所述第一重布局层与所述第二重布局层。
7.如权利要求4所述的多元件封装体，其特征在于，所述第一重布局层与所述第二重布局层包含：
多个金属层，所述金属层在介电层中呈平行排列；以及
多个导电柱，且所述导电柱电性连接相邻的所述两个金属层。
8.如权利要求4所述的多元件封装体，其特征在于，所述封胶层包含环氧树脂。
9.一种多元件封装体，其特征在于，所述多元件封装体包含：
至少两个元件区域设置于基板中；
第一重布局层，其设置于所述基板上；
外部晶片，其设置于所述第一重布局层上；
第二重布局层，其设置于所述第一重布局层上；以及
封胶层，其设置于所述第一重布局层与所述第二重布局层之间，所述封胶层包含：
第一导电接触，其通过所述封胶层；以及
第二导电接触，其通过所述封胶层与所述外部晶片，且所述第一导电接触与所述第二导电接触连接所述第一重布局层与所述第二重布局层。
10.一种多元件封装体的制备方法，其特征在于，所述多元件封装体的制备方法包含：
在晶圆上形成第一重布局层，所述晶圆具有至少两个元件区域，且所述第一重布局层电性连接至所述两个元件区域；
在所述第一重布局层上形成多个第一连接件；以及
在所述第一连接件上配置外部晶片，以使所述外部晶片借由所述第一连接件电性连接至所述第一重布局层。
11.如权利要求10所述的多元件封装体的制备方法，其特征在于，所述多元件封装体的制备方法还包含：
在所述第一重布局层上形成多个第二连接件，且所述第二连接件的直径大于所述第一连接件的直径与所述外部晶片的厚度的总和。
12.如权利要求11所述的多元件封装体的制备方法，其特征在于，所述多元件封装体的制备方法还包含：
形成暂时粘着层，其覆盖所述第二连接件与所述外部晶片；
薄化所述晶圆；以及
移除所述暂时粘着层。
13.如权利要求12所述的多元件封装体的制备方法，其特征在于，所述多元件封装体的制备方法还包含：
沿着切割道切割所述晶圆以形成所述多元件封装体。
14.如权利要求10所述的多元件封装体的制备方法，其特征在于，所述外部晶片具有第一穿孔。
15.如权利要求14所述的多元件封装体的制备方法，其特征在于，所述多元件封装体的制备方法还包含：
形成封胶层，其覆盖所述第一重布局层与所述外部晶片；
移除部分的所述封胶层以形成第二穿孔与第三穿孔，所述第二穿孔暴露所述第一重布局层，而所述第三穿孔贯通所述第一穿孔以暴露所述第一重布局层；以及
填充导电材料至所述第一穿孔、所述第二穿孔与所述第三穿孔中以形成第一导电接触与第二导电接触。
16.如权利要求15所述的多元件封装体的制备方法，其特征在于，所述多元件封装体的制备方法还包含：
在所述封胶层上形成第二重布局层，且所述第二重布局层电性连接至所述第一导电接触与所述第二导电接触；以及
在所述第二重布局层上形成多个第三连接件。
17.如权利要求16所述的多元件封装体的制备方法，其特征在于，所述多元件封装体的制备方法还包含：
形成暂时粘着层，其覆盖所述第三连接件与所述第二重布局层；
薄化所述晶圆；以及
移除所述暂时粘着层。
18.如权利要求17所述的多元件封装体的制备方法，其特征在于，所述多元件封装体的制备方法还包含：
沿着切割道切割所述晶圆以形成所述多元件封装体。
19.如权利要求10所述的多元件封装体的制备方法，其特征在于，在所述晶圆上形成所述第一重布局层包含：
沉积介电材料，其覆盖所述晶圆；
移除部分的所述介电材料以形成多个开口暴露所述晶圆中的所述元件区域；
在所述开口中形成多个导电柱；
在所述导电柱上形成金属层；以及
图案化所述金属层。
20.如权利要求16所述的多元件封装体的制备方法，其特征在于，在所述晶圆上形成所述第二重布局层包含：
沉积介电材料，其覆盖所述封胶层；
移除部分的所述介电材料以形成多个开口暴露所述第一导电接触与所述第二导电接触；
在所述开口中形成多个导电柱；
在所述导电柱上形成金属层；以及
图案化所述金属层。
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