CN103270588A - 具有嵌入式层叠硅通孔管芯的衬底 - Google Patents

具有嵌入式层叠硅通孔管芯的衬底 Download PDF

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Publication number
CN103270588A
CN103270588A CN2011800620102A CN201180062010A CN103270588A CN 103270588 A CN103270588 A CN 103270588A CN 2011800620102 A CN2011800620102 A CN 2011800620102A CN 201180062010 A CN201180062010 A CN 201180062010A CN 103270588 A CN103270588 A CN 103270588A
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Prior art keywords
tube core
tsv
dorsal part
technology
substrate
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CN2011800620102A
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J·S·冈萨雷斯
H·乔玛
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Intel Corp
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Intel Corp
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Priority to CN201810326216.5A priority Critical patent/CN108538734B/zh
Publication of CN103270588A publication Critical patent/CN103270588A/zh
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Abstract

描述了具有嵌入式层叠硅通孔的衬底。例如，一种装置包括第一管芯和第二管芯。第二管芯具有布置在其中的一个或多个硅通孔（TSV管芯）。第一管芯通过所述一个或多个硅通孔电耦合到TSV管芯。该装置还包括无芯衬底。第一管芯和TSV管芯二者都嵌入在无芯衬底中。

Description

具有嵌入式层叠硅通孔管芯的衬底
技术领域
本发明的实施例处于半导体封装领域，具体而言，处于具有嵌入式层叠硅通孔管芯的衬底的领域。
背景技术
如今的消费者电子市场频繁地要求需要非常复杂的电路的复杂功能。缩放到越来越小的例如晶体管之类的基本构建块已经使得能够随着渐进式的世代将甚至更复杂电路合并到单个管芯上。另一方面，尽管缩放通常被认为是尺寸的减小，但是多个所封装的管芯越来越多地耦合在一起以获得计算系统中的更先进的功能和马力。而且，特定半导体封装的尺寸实际上可能被增加以将多个管芯包括在单个半导体封装内。
然而，当尝试耦合多个所封装的管芯时，可能出现结构问题。例如，半导体封装中所使用的组件的之间的热膨胀系数（CTE）差异的影响可能在将所封装的管芯添加在一起时导致有害的缺陷。类似地，用在单个半导体封装内的组件之间的热膨胀系数（CTE）差异的效应可能由于对单个封装内的一个以上管芯执行半导体管芯封装工艺而导致有害的缺陷。
半导体封装被用于保护集成电路（IC）芯片或管芯，并且还用于向管芯提供去往外部电路的电接口。随着对更小的电子器件的要求增加，半导体封装被设计成更紧凑的，并且必须支持更大的电路密度。例如，一些半导体封装现在使用无芯衬底，该无芯衬底不包括常规衬底中常见的厚树脂芯层。此外，对高性能器件的要求导致对经改善的半导体封装的需求，该经改善的半导体封装实现混合技术管芯层叠或者在保持与随后的封装处理兼容的薄封装轮廓和低总翘曲的同时提供封装层叠能力。
无凸块构建层（Bumpless Build-Up Layer）或BBUL是一种处理器封装技术。该技术是无凸块的，因为其不使用常用的微小焊料凸块来将硅管芯附连到处理器封装引线。其具有构建层，因为其是围绕硅管芯生长或构建的。常见方式是单独地制造它们并将它们接合在一起。一些半导体封装现在使用无芯衬底，该无芯衬底不包括常规衬底中常见的厚树脂芯层。
附图说明
图1示出了根据本发明的实施例的具有嵌入式层叠硅通孔管芯的无芯衬底的横截面图。
图2A示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的处理期间的横截面图。
图2B示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的处理期间的横截面图。
图2C示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的进一步处理期间的横截面图。
图2D示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的进一步处理期间的横截面图。
图2E示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的进一步处理期间的横截面图。
图2F示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的进一步处理期间的横截面图。
图2G示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的进一步处理期间的横截面图。
图2H示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的处理期间的横截面图。
图2I示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的处理期间的横截面图。
图2J示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的处理期间的横截面图。
图2K示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的处理期间的横截面图。
图2K’示出了根据本发明的另一实施例的具有嵌入式层叠硅通孔管芯的无芯衬底的横截面图。
图3是根据本发明实施例的计算机系统的示意图。
具体实施方式
描述了具有嵌入式层叠硅通孔管芯的衬底。在以下的描述中，阐述了很多具体细节，诸如封装架构和材料体系，以提供对本发明实施例的透彻理解。将对本领域技术人员明显的是，没有这些具体细节也可实践本发明的实施例。在其它实例中，公知的特征——例如集成电路设计布局——不被详细描述以免不必要地遮蔽本发明变得。此外要理解，附图中示出的各实施例是说明性表示并且不一定按比例绘出。
通常在封装工艺、例如将经封装的存储器管芯与封装逻辑管芯相耦合以后，耦合容纳半导体管芯的多个半导体封装。在一示例中，两个或更多单独封装的管芯之间的连接可以在无凸块构建层（BBUL）制造以后通过使用热压接合（TCB）处理来进行。然而，例如由于逻辑管芯造成的翘曲，可能发生BBUL的翘曲。相反，根据本发明的实施例，将存储器管芯附连到面板。存储器管芯往往是更扁平的，并且为逻辑管芯的随后的接合提供良好的基础。因此，通过从存储器管芯开始然后是逻辑管芯来封装多个管芯，使处理在载体或面板级下变得更容易。此外，与逻辑管芯相比较大的存储器管芯实际上对于这样的面板封装方案可以是优选的，而相反的情况可能对于逻辑芯片和存储器管芯的封装以后的耦合成立。在实施例中，将逻辑管芯与同一封装中的存储器管芯同时封装避免增大在耦合单独和分开封装的管芯时看到的导致翘曲的CTE失配。
根据本发明的实施例，公开了硅通孔（TSV）存储器/逻辑嵌入式封装。例如，描述了一种多管芯封装，该封装消除了对BBUL存储器附连之后热压接合（TCB）的需要。相反，两个管芯都嵌入在该封装上。TCB可以用于链接管芯，但是更扁平的存储器被附连和支承在可剥离的芯上。该方案可以显著减轻有害的翘曲状况。可以首先进行管芯到管芯连接（其中硅块之间的CTE失配最小）。可以使用大面板载体，从而促进处理。而且，在一实施例中，不需要从第一管芯到外部封装的布线。
在此公开了具有嵌入式层叠硅通孔管芯的无芯衬底。在一实施例中，一种装置包括第一管芯和第二管芯。第二管芯具有布置在其中的一个或多个硅通孔（TSV管芯）。第一管芯通过所述一个或多个硅通孔电耦合到TSV管芯。该装置还包括无芯衬底。第一管芯和TSV管芯二者都嵌入在无芯衬底中。
在此还公开了制造具有嵌入式层叠硅通孔管芯的无芯衬底的方法。在一实施例中，一种工艺包括利用管芯接合膜将第一管芯的背侧接合到面板。将包括其中布置的一个或多个硅通孔的第二管芯（TSV管芯）的背侧布置在第一管芯的器件侧之上并且通过所述一个或多个硅通孔接合到第一管芯的器件侧。在TSV管芯的器件侧之上形成密封层，该密封层包围第一管芯和TSV管芯。随后，将面板从管芯接合膜移除。
在本发明的一方面，公开了具有嵌入式层叠硅通孔管芯的无芯衬底。图1示出了根据本发明的实施例的具有嵌入式层叠硅通孔管芯的无芯衬底的横截面图。
参考图1，层叠管芯装置100包括嵌入在无芯衬底104中的第一管芯102。无芯衬底104包括焊区侧106和管芯侧108。第一管芯102还包括有源表面或器件侧110、以及背侧表面或背侧112，并且可以看出，第一管芯102的有源表面110朝向焊区侧106，而背侧112与无芯衬底104的管芯侧108朝向相同的方向。有源表面可以包括多个半导体器件，包括但不限于通过管芯互连结构被连接到一起形成功能电路的晶体管、电容器和电阻器以由此形成集成电路。
本领域的技术人员能够理解，第一管芯102的器件侧110包括具有集成电路和互连的有源部分（未示出）。根据若干不同实施例，第一管芯102可以是任何合适的集成电路器件、包括但不限于微处理器（单核或多核）、存储器器件、芯片组、图形器件、专用集成电路。在一实施例中，层叠管芯装置100还包括布置在第一管芯102的背侧112上的管芯接合膜130。
在一实施例中，第一管芯102是包括第二管芯114的更大装置的一部分，第二管芯114布置在管芯侧108之下并且耦合到第一管芯102。第二管芯114还以简化的图示被示为具有有源表面或器件侧116，但是它还可以具有M1至M11的金属化部或任何数目和顶部金属化部厚度。第二管芯114还具有背侧表面或背侧118。
第二管芯114也嵌入在无芯衬底104中。在一实施例中，第二管芯114具有至少一个硅通孔120。示出了两个硅通孔，枚举了所述两个硅通孔之一，但是为简单起见呈现了所示的两个硅通孔。在一实施例中，第二管芯114中存在高达1000个硅通孔。因此，第二管芯114可以被称为包括其中布置有硅通孔的管芯（TSV管芯114）。TSV管芯114的器件侧116朝向焊区侧106，而背侧118朝向无芯衬底104的管芯侧108。本领域的技术人员能够理解，TSV管芯114的器件侧116还包括具有集成电路和互连的有源部分（未示出）。根据若干不同实施例，TSV管芯114可以是任何合适的集成电路器件，包括但不限于微处理器（单核或多核）、存储器器件、芯片组、图形器件、专用集成电路。
如所示那样，第一管芯102通过所述至少一个硅通孔120耦合到TSV管芯114。在一实施例中，第一管芯102通过所述一个或多个硅通孔电耦合到TSV管芯114。在一个实施例中，第一管芯102经由所述一个或多个硅通孔120通过布置在第一管芯102上的一个或多个相应的导电凸块126以及通过布置在TSV管芯114上的一个或多个接合焊盘（未示出）电耦合到TSV管芯114。接合焊盘被包括在TSV管芯114的背侧118上并且与所述一个或多个硅通孔120对准。在一实施例中，环氧助焊剂材料层128布置在第一管芯102与TSV管芯114之间。在一实施例中，无芯衬底104在第一管芯102与TSV管芯114之间不含附加的布线层。也就是说，在一实施例中，第一管芯102和TSV管芯114仅仅通过第一管芯102的器件侧110上的导电凸块以及TSV管芯114的所述一个或多个硅通孔120来通信。
TSV管芯114还以简化形式被示出具有器件侧118上的的金属化部。金属化部在器件侧116与TSV管芯114中的集成电路接触。在一实施例中，金属化部具有金属1（M1）到金属11（M11）金属化层以便将TSV管芯114的复杂度输出到外界，其中M1与TSV管芯114中的集成电路接触。在所选实施例中，在M1与M11之间可以存在任何数目的金属化部。在示例实施例中，TSV管芯114具有从M1至M7的金属化部，且M7比M1至M6更厚。根据给定应用效用，可实现其他金属化部数目和厚度组合。
在一实施例中，如图1所示，层叠管芯装置100包括在无芯衬底104的焊区侧106处的基础衬底122。例如，在第一管芯102和TSV管芯114是手持式设备（诸如智能电话实施例或手持式阅读器实施例）的一部分的情况下，基础衬底122是主板。在第一管芯102和TSV管芯114是手持式设备（诸如智能电话实施例或手持式阅读器实施例）的一部分的示例性实施例中，基础衬底122是外壳，诸如个人在使用时触摸的部分。在第一管芯102和TSV管芯114是手持式设备（诸如智能电话实施例或手持式阅读器实施例）的一部分的示例性实施例中，基础衬底122包括主板和外壳（诸如个人在使用时触摸的部分）。
外部导电接触部132的阵列布置在无芯衬底104的焊区侧106上。在一实施例中，外部导电接触部132将无芯衬底104耦合到基础衬底122。外部导电接触部132被用于与基础衬底122的电通信。在一个实施例中，外部导电接触部132的阵列是球栅阵列（BGA）。焊料掩模134遮蔽形成无芯衬底104的焊区侧106的材料。外部导电接触部132布置在凸块接合焊盘136上。
层叠管芯装置100包括被完全嵌入和包围的TSV管芯114。如在本公开中所使用的那样，“被完全嵌入和包围”是指，TSV管芯的所有表面都与无芯衬底104的密封膜（比如介电层）接触，或者至少与密封膜内容纳的材料接触。换言之，“被完全嵌入和包围”是指，TSV管芯114的所有露出的表面都与无芯衬底104的密封膜接触。
层叠管芯装置100还包括完全嵌入的第一管芯102。如在本公开中使用的那样，“完全嵌入”是指，第一管芯102的有源表面110和整个侧壁都与无芯衬底104的密封膜（比如介电层）接触或者至少与密封膜内容纳的材料接触。换言之，“完全嵌入”是指，第一管芯102的有源表面110的所有露出区域和整个侧壁的露出部分与无芯衬底104的密封膜接触。然而，第一管芯102未被“包围”，因为第一管芯102的背侧112未与无芯衬底104的密封膜、或密封膜内容纳的材料接触。在此描述了第一管芯102的“完全嵌入”的两个实施例。在第一实施例中，如图1和2K所示，存在第一管芯的一个表面（例如背表面112），该表面从无芯衬底的管芯侧的全局平整表面突出、例如从图1所示的无芯衬底104的表面108突出。在第二实施例中，如图2K’所示，没有第一管芯230的表面从无芯衬底的管芯侧的全部平坦表面突出，例如不存在从图2K’所示的无芯衬底272’的表面270’的突出。
与“被完全嵌入和包围”和“完全嵌入”的上面的定义相对比，“部分嵌入”的管芯是其整个表面、但侧壁的仅仅一部分与无芯衬底的密封膜接触、或者至少与密封膜内容纳的材料接触的管芯。进一步相对比，“未嵌入”的管芯是其最多一个表面、并且没有侧壁部分与无芯衬底的密封膜接触、或者与密封膜内容纳的材料接触。
因此，根据本发明的实施例，无芯衬底104包括密封层124。第一管芯102和TSV管芯114二者都完全嵌入在密封层124中。也就是说，第一管芯102和TSV管芯114被容纳在同一单个绝缘材料层中。
作为所公开的第一管芯和TSV管芯实施例的结果，层叠管芯装置100的Z高度可以被降低。降低的Z高度有益于紧凑的装置设计和使用，比如用于手持式设备。例如，在装置要充当芯片组时可减少总覆盖区域。这是有益的，因为第一管芯102和TSV管芯114的叠层114占据了无芯衬底104上的紧凑的覆盖面积。
层叠管芯装置100尤其可以适于将存储器管芯与逻辑管芯封装在一起。例如，在一实施例中，第一管芯102是具有器件侧110和背侧112的存储器管芯。TSV管芯114是逻辑管芯（逻辑TSV管芯），其包括布置在其中的一个或多个硅通孔120。逻辑TSV管芯114具有器件侧116和背侧118。逻辑TSV管芯114布置在存储器管芯102之上并且与存储器管芯102对准。逻辑TSV管芯114的背侧118朝向存储器管芯102的器件侧110。存储器管芯102通过所述一个或多个硅通孔120电耦合到逻辑TSV管芯114。包括逻辑TSV管芯114和存储器管芯102的封装还包括无芯衬底104。无芯衬底104具有焊区侧106和管芯侧108。存储器管芯102和逻辑TSV管芯114二者都嵌入在无芯衬底104中。存储器管芯102的背侧112朝向无芯衬底104的管芯侧108，并且逻辑TSV管芯114的器件侧116朝向无芯衬底104的焊区侧106。在一个实施例中，存储器管芯102的器件侧110在面积方面比逻辑TSV管芯114的背侧118更大。在本申请的实施例中，存储器管芯102是存储器器件、包括但不限于静态随机存取存储器（SRAM）、动态存取存储器（DRAM）、非易失性存储器（NVM），并且TSV管芯是逻辑器件、包括但不限于微处理器和数字信号处理器。
在本发明的另一方面，公开了用于制造具有嵌入式层叠硅通孔管芯的无芯衬底的方法。可以提供诸如面板之类的载体，其具有布置在其中的多个空腔，每个空腔的尺寸都被设计为容纳管芯。图2A示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的处理期间的横截面图。装置200表示早期处理并且与图1所示的装置100相关。设置有蚀刻停止层202。可蚀刻诸如铜箔层之类的第二层206以提供具有管芯安装表面204的凹陷或空腔。封装堆叠接合焊盘208已经形成在第二层206上。
图2B示出了根据本发明的实施例的在具有嵌入式层叠硅通孔管芯的无芯衬底的制造中的进一步处理期间的横截面图。在处理期间，装置200可以与相同的结构配合，以便构建用于处理效用的背靠背装置。通过将原始装置200与类似装置200’进行背靠背配合，装置210已经被扩大。结果，处理吞吐量被有效倍增。对装置200和200’的描述可以由归于装置200的附图标记来指代，但是能够理解，重复的处理和结构包含在装置200’中。装置210包括粘合释放层212和粘合剂214。切割区216被提供在装置210的每个末端处以用于进一步示出的分离处理。装置210可以形成具有多个相同区的较大面板的一部分，其中所述相同区具有装置210的截面。例如，面板可以在每侧包括1000个凹陷部，从而允许从单个面板中制造2000个单独的封装。
管芯的背侧可以利用管芯接合膜被接合到面板。例如，图2C示出了根据本发明的实施例的在图2B所示装置的进一步处理期间的横截面图。具体而言，通过利用管芯接合膜219将第一管芯220接合在蚀刻停止层202上而进一步处理装置218。在一实施例中，利用管芯接合膜219将第一管芯220的背侧223接合到面板即结合到装置210包括：利用材料、比如但不限于基于环氧树脂的材料进行接合。在一实施例中，蚀刻停止层202是金属层。在一实施例中，蚀刻停止层202是有机材料。根据特定应用，可以将其他材料用于蚀刻停止层202。
第一管芯220具有多个导电凸块，所述导电凸块之一是用附图标记222来表示的。第一管芯220具有有源表面221，该有源表面221与导电凸块222处于相同的表面上。为了便于图解说明，导电凸块222的数目被示为仅仅两个。第一管芯220具有背侧表面223，该背侧表面与有源表面221相对。另外，第一管芯220具有金属化部224，该金属化部224可以包括本公开中所阐述的任何数目和类似厚度的金属化部。在一实施例中，导电凸块222的形成是通过半加成镀覆工艺来执行的。第一管芯220位于形成在第二层206内的凹陷或空腔内。因此，在一实施例中，将第一管芯的背侧223接合到面板包括接合到布置在面板中的空腔的表面。
图2D示出了根据本发明的实施例的在图2C所示装置的进一步处理期间的横截面图。具体而言，图2D示出了添加第一管芯220’以形成装置226。
图2E示出了根据本发明的实施例的在图2D所示装置的进一步处理期间的横截面图。通过将TSV管芯230、互补的TSV管芯230’放置在第一管芯220上，对装置226进一步处理。TSV管芯230具有多个管芯接合焊盘，所述管芯接合焊盘之一是用附图标记232来表示的。TSV管芯220具有有源表面231，该有源表面与接合焊盘232处于同一表面上。为便于图解说明，接合焊盘232的数目被示为仅仅两个，并且这些接合焊盘232不一定与通孔236接触。TSV管芯230具有背侧表面233，该背侧表面与有源表面231相对。另外，TSV管芯230具有金属化部234，该金属化部224可以包括本公开中所阐述的任何数目和类似厚度的金属化部。TSV管芯230还被示为具有两个硅通孔，其中一个是用附图标记236表示的。背侧接合焊盘237被包括在TSV管芯230的背侧233，并且与硅通孔236对准。
图2F示出了根据本发明的实施例的在图2E所示装置的制造中的进一步处理期间的横截面图。TSV管芯230的背侧233布置在第一管芯220的器件侧之上并且接合到该器件侧。在一实施例中，TSV管芯230的背侧233通过所述一个或多个硅通孔236、并且因此通过背侧接合焊盘237接合到第一管芯220的导电凸块222，这如图2F所示。
在一实施例中，将TSV管芯230的背侧233耦合到第一管芯220的器件侧是通过如下方式执行的：用环氧助焊剂材料238将TSV管芯230的背侧233接合到第一管芯220的器件侧。环氧助焊剂材料可以在附连管芯230之前被分配到到管芯220之上。在一个实施例中，环氧助焊剂材料238清洗布置在TSV管芯230的背侧233上的一个或多个相应的接合焊盘237，并且密封布置在第一管芯220的器件侧上的一个或多个导电凸块222与布置在TSV管芯230的背侧233上的一个或多个相应的接合焊盘237之间形成的接合部240。在一实施例中，通过布置在第一管芯220的器件侧上的一个或多个导电凸块222和布置在TSV管芯230的背侧233上的一个或多个相应的接合焊盘237进行耦合是通过使用热压接合技术来执行的。在特定实施例中，TSV管芯230的背侧在热压接合期间被加热到大致220－240摄氏度范围内的温度。
图2G示出了根据本发明的实施例的在图2F所示装置的进一步处理期间的横截面图。密封层242形成在TSV管芯230的器件侧231和管芯接合焊盘232之上。密封层242包围第一管芯220和TSV管芯230的所有露出的区，这如图2G中所示。密封层242可以是介电层。在一实施例中，密封层242是通过层压工艺形成的。在另一实施例中，密封层242是通过在装置的晶片级阵列上旋涂和固化电介质来形成的，其中装置244为便于图解说明仅仅是该阵列的子集。
图2H示出了根据本发明的实施例的在图2G所示装置的进一步处理期间的横截面图。装置246已经被处理为使得图2G中所示密封层242已经被图案化以形成经图案化的密封层248并且若干孔径已经被形成在其中，所述孔径之一是用附图标记250表示的。孔径250暴露TSV管芯230的接合焊盘232。在一些实施例中，可形成更深的孔径251以暴露封装堆叠接合焊盘208，这如图2H中所示。在一实施例中，使用二氧化碳（CO2）或紫外线（UV）处理方案来形成孔径250，所述孔径250将被用于暴露TSV管芯230的管芯接合焊盘232以及封装堆叠接合焊盘208。
可以使用二氧化碳（CO2）、紫外（UV）激光束或准分子激光束来实现激光钻孔。在本申请的实施例中，形成具有直径在30－50微米之间的孔径250。根据各实施例的激光钻孔与现有技术中的钻孔工艺相比允许更高的连接密度，以实现小通孔尺寸和间距，并且以此方式在低成本下导致改进的设计和可扩展的小型化。附加地，激光钻孔允许高对准精确度（例如10至15微米）和吞吐量（大约2000个通孔/秒）以及大范围的可能的通孔尺寸（比如30微米至大约300微米之间）和低成本（大约每1000个通孔2美分）。高对准精确度和小通孔尺寸的组合使得低达60微米的可能的通孔间距成为可能，这些间距远小于用于含芯封装上的通常镀覆的大约400微米的通孔间距。
图2I示出了根据本发明的实施例的在图2H所示装置的进一步处理期间的横截面图。导电通孔252被形成在孔径250中并填充孔径250。布线层254或迹线然后被形成并且通过导电通孔252与TSV管芯230以及封装堆叠接合焊盘208电耦合。在一实施例中，导电通孔252和布线层254是由铜组成，并且TSV管芯230的接合焊盘232和封装堆叠接合焊盘208也是铜。在一实施例中，可以为导电通孔252、布线层254、接合焊盘232和封装堆叠接合焊盘208选择其他金属。在一实施例中，导电通孔252和布线层254是使用半加成工艺（SAP）形成的，以完成无凸块构建层（BBUL）工艺的其余层，这如下面图2K中所示。
图2J示出了根据本发明的实施例的在图2I所示装置的进一步处理期间的横截面图。装置256已经用介电层258进行处理，使得经图案化的密封或介电层248以及布线层或迹线254被包封。电介质258的处理可以通过层压或通过旋涂并固化液体前体来执行，并且可以在晶片级阵列的情况下执行。
图2K示出了根据本发明的实施例的在图2L所示装置的进一步处理期间的横截面图。现在能够理解，具有用于无凸块构建层部分264的外部导电接触部262的阵列的外部接触层260被形成以将TSV管芯230耦合到外界。尽管用于无凸块构建层的外部接触层260是用经图案化的密封或介电层248和介电层258示出的，但是能够理解，可以使用若干层的金属化层和电介质来形成无凸块的构建层部分264，该部分最终是具有嵌入式TSV管芯230的无芯衬底。外部导电接触部262的阵列被布置在一个或多个布线层或迹线254之上并与其电耦合。在一实施例中，能够理解，不需要从第一管芯220的布线以直接与无芯衬底272的外部通信。
再次参考图2K，层204和206以及由此临时的内芯已经被移除。在一实施例中，外部接触层260在移除面板之前被移除。在一个实施例中，外部导电接触部262的阵列是球栅阵列（BGA）。在其他实施例中，外部导电接触部262的阵列是诸如、但不限于焊盘栅阵列（LGA）或针脚阵列（PGA）之类的阵列。
因此，根据本发明的实施例，面板被用于支承TSV管芯的封装直到形成外部导电管道的阵列。面板然后被移除以为TSV管芯提供无芯封装。因此，在一实施例中，术语“无芯”被用于指，上面形成有用于容纳管芯的封装的支承体最终在构建工艺结束时被移除。在特定的实施例中，无芯衬底是在制造工艺完成以后不包括厚芯的衬底。作为示例，厚芯可以由诸如用在主板中的增强材料组成，并且其中可以包括导电通孔。能够理解，管芯接合膜219可以如图2K中所示被保留，或者可以被移除。在两种情况任一中，在移除面板以后包括或排除管芯接合膜219将提供无芯衬底。另外，衬底可以被认为是无芯衬底，因为其不包括诸如纤维增强型玻璃环氧树脂之类的厚芯。
在面板的两侧的多个区被用于封装TSV管芯的情况下，通过移除如图2B中所示的切割区216内的材料，图2J所示的装置可被分割（其被修改以包括用于无凸块构建层的外部接触层260）。在切割区216被移除的情况下，粘合释放层212和粘合剂214（也与图2B相关联地被示出和描述）允许相对的装置被分离。
再次参考图2K，无芯衬底272的管芯侧的全局表面270比管芯接合膜219的背侧276更接近无芯衬底272的焊区侧274。参考图2K’，能够理解，无芯衬底272’的管芯侧的全局表面270’可以被制造为与管芯接合膜219’的背侧276’基本平整。在一实施例中，这样的平整性是通过在面板上不包括第二层206、即在面板中不包括用于将第一管芯与TSV管芯封装在一起的凹陷区（如与图2B相关联地所示那样）。
因此，本发明的实施例使得能够形成具有薄封装配置和小覆盖面积的多芯片封装，由此节省设备主板上的宝贵空间。附加地，本发明的实施例使得能够在不使用封装堆叠（POP）技术的情况下将两个管芯电连接，其中封装堆叠（POP）技术需要表面安装技术（SMT），但是关于需要将翘曲的问题考虑在内。附加地，在本发明的实施例中，使用低温无凸块构建层（BBUL）工艺来形成衬底，以便减少或消除所嵌入的管芯与衬底之间的热膨胀系数（CTE）失配的影响，由此实现非常平整的多芯片封装的制造。
图3是根据本发明实施例的计算机系统300的示意图。根据如本公开所陈述的若干公开实施例及其等效方案中的任一个，所示计算机系统300（也称为电子系统300）可具体实现嵌入式TSV管芯无核衬底（BBUL-CTSV管芯）。计算机系统300可以是移动设备，诸如上网本计算机。计算机系统300可以是移动设备，诸如无线智能电话。计算机系统300可以是台式计算机。计算机系统300可以是手持式阅读器。
在一实施例中，电子系统300是计算机系统，该计算机系统包括用于电气耦合电子系统300的多个部件的系统总线320。根据多个实施例，系统总线320是单个总线或总线的任意组合。电子系统300包括提供功率至集成电路310的电压源330。在一些实施例中，电压源330通过系统总线320向集成电路310提供电流。
根据一实施例，集成电路310电耦合至系统总线320，且包括任何电路或电路的组合。在一实施例中，集成电路310包括任何类型的处理器312。如本文中所使用，处理器312可表示任何类型的电路，诸如但不限于微处理器、微控制器、图形处理器、数字信号处理器或另一种处理器。在一实施例中，处理器312是本文公开的嵌入式层叠TSV管芯。在一实施例中，在处理器的存储器高速缓存中存在SRAM实施例。可以包括在集成电路310中的其他类型电路是定制电路或专用集成电路（ASIC），诸如用于无线设备（诸如蜂窝电话、智能电话、寻呼机、便携式计算机、双向无线电设备、以及类似的电子设备）的通信电路314。在一实施例中，处理器310包括管芯上存储器316，诸如静态随机存取存储器（SRAM）。在一实施例中，处理器310包括嵌入式管芯上存储器316，诸如嵌入式动态随机存取存储器（eDRAM）。
在一实施例中，用随后的集成电路311（诸如嵌入式层叠TSV管芯实施例）来补充集成电路310。有用的实施例包括双处理器313、双通信电路315和双管芯上存储器317，诸如SRAM。在一实施例中，双集成电路310包括嵌入式管芯上存储器317，诸如eDRAM。
在一实施例中，电子系统300还包括外部存储器340，该外部存储器340又可包括适合于特定应用的一个或多个存储器元件，诸如RAM形式的主存储器342、一个或多个硬驱动器344、和/或操作可移除介质346（诸如软磁盘、紧致盘（CD）、数字多功能盘（DVD）、快闪存储器驱动器以及本领域已知的其他可移除介质）的一个或多个驱动器。根据一实施例，外部存储器340也可以是嵌入存储器348，诸如嵌入在嵌入式TSV管芯叠层中的第一管芯。
在一实施例中，电子系统300还包括显示设备350、音频输出360。在一实施例中，电子系统300包括输入设备，诸如控制器370，其可以是键盘、鼠标、轨迹球、游戏控制器、话筒、语音识别设备、或向电子系统300中输入信息的任何其他输入设备。在实施例中，输入设备370是照相机。在一实施例中，输入设备370是数字录音器。在一实施例中，输入设备370是照相机和数字录音器。
如本文所示，集成电路310可以在多个不同实施例中实现，包括根据若干所公开实施例及其等效方案的嵌入式层叠TSV管芯、电子系统、计算机系统、制造集成电路的一种或多种方法、以及制造电子组件的一种或多种方法，该电子组件包括根据本文在多个实施例中阐述的若干所公开实施例以及本领域可认知的等效方案中的任一个的嵌入式层叠TSV管芯。根据所公开的若干嵌入式TSV管芯实施例及其等效方案，可以改变元件、材料、几何形状、尺寸以及操作顺序以适合特定I/O耦合要求，这些要求包括处理器安装衬底中所嵌入的微电子管芯的阵列接触数、阵列接触配置。
因此，已经公开了具有嵌入式层叠硅通孔管芯的无芯衬底。在一实施例中，一种装置包括存储器管芯，该存储器管芯具有器件侧和背侧。该装置还包括逻辑管芯（逻辑TSV管芯），该逻辑管芯具有布置在其中的一个或多个硅通孔。逻辑TSV管芯具有器件侧和背侧，并且布置在存储器管芯之上并与其对准。逻辑TSV管芯的背侧朝向存储器管芯的器件侧，并且存储器管芯通过一个或多个硅通孔电耦合到逻辑TSV管芯。该装置还包括具有焊区侧和管芯侧的无芯衬底。第一管芯和逻辑TSV管芯二者都嵌入在无芯衬底中。存储器管芯的背侧朝向无芯衬底的管芯侧，并且逻辑TSV管芯的器件侧朝向无芯衬底的焊区侧。该装置还包括外部导电接触部的阵列，所述外部导电接触部布置在无芯衬底的焊区侧。

Claims (20)

1.一种装置，包括：
第一管芯；
第二管芯（TSV管芯），包括布置在其中的一个或多个硅通孔，第一管芯通过所述一个或多个硅通孔电耦合到所述TSV管芯；以及
无芯衬底，其中第一管芯和所述TSV管芯二者都嵌入在所述无芯衬底中。
2.如权利要求1所述的装置，其特征在于，所述无芯衬底包括密封层，并且其中第一管芯和所述TSV管芯嵌入在所述密封层中。
3.如权利要求1所述的装置，其特征在于，第一管芯经由所述一个或多个硅通孔通过布置在第一管芯上的一个或多个相应的导电凸块以及通过布置在所述TSV管芯上的一个或多个接合焊盘耦合到所述TSV管芯。
4.如权利要求1所述的装置，其特征在于，还包括：
布置在第一管芯与所述TSV管芯之间的环氧助焊剂材料层。
5.如权利要求1所述的装置，其特征在于，所述无芯衬底不具有在第一管芯与所述TSV管芯之间的布线层。
6.如权利要求1所述的装置，其特征在于，还包括：
布置在第一管芯上的管芯接合膜。
7.如权利要求1所述的装置，其特征在于，第一管芯的表面从所述无芯衬底的表面突出。
8.如权利要求1所述的装置，其特征在于，第一管芯的表面不从所述无芯衬底的表面突出。
9.如权利要求1所述的装置，其特征在于，第一管芯完全嵌入所述无芯衬底，并且其中所述TSV管芯被完全嵌入和包围在所述无芯衬底中。
10.一种工艺，包括：
利用管芯接合膜将第一管芯的背侧接合到面板；
将其中布置有一个或多个硅通孔的第二管芯（TSV管芯）的背侧耦合在第一管芯的器件侧之上并且通过所述一个或多个硅通孔耦合到第一管芯的器件侧；
在所述TSV管芯的器件侧之上形成密封层，所述密封层包围第一管芯和所述TSV管芯；以及随后
将所述面板从所述管芯接合膜移除。
11.如权利要求10所述的工艺，其特征在于，将第一管芯的背侧接合到所述面板包括：将第一管芯的背侧接合到布置在所述面板中的空腔的表面。
12.如权利要求10所述的工艺，其特征在于，利用所述管芯接合膜将第一管芯的背侧接合到所述面板包括：用基于环氧树脂的材料进行接合。
13.如权利要求10所述的工艺，其特征在于，将所述TSV管芯的背侧耦合到第一管芯的器件侧包括：通过布置在第一管芯的器件侧上的一个或多个导电凸块以及通过布置在所述TSV管芯的背侧上的一个或多个相应的接合焊盘进行耦合。
14.如权利要求13所述的工艺，其特征在于，将所述TSV管芯的背侧耦合到第一管芯的器件侧包括：利用环氧树脂助焊剂材料将所述TSV管芯的背侧接合到第一管芯的器件侧。
15.如权利要求14所述的工艺，其特征在于，所述环氧树脂助焊剂材料清洗布置在所述TSV管芯的背侧上的一个或多个相应放入接合焊盘，并且密封在布置在第一管芯的器件侧上的一个或多个导电凸块与布置在所述TSV管芯的背侧上的一个或多个相应的接合焊盘之间形成的接合部。
16.如权利要求13所述的工艺，其特征在于，通过布置在第一管芯的器件侧上的一个或多个导电凸块和布置在所述TSV管芯的背侧上的一个或多个相应的接合焊盘进行耦合包括使用热压接合技术。
17.如权利要求16所述的工艺，其特征在于，所述TSV管芯的背侧在热压接合期间被加热到大致220－240摄氏度范围内的温度。
18.如权利要求10所述的工艺，其特征在于，还包括：
在移除所述面板以前，在所述TSV管芯的器件侧之上形成一个或多个布线层，并且将所述一个或多个布线层与所述TSV管芯的器件侧电耦合。
19.如权利要求18所述的工艺，其特征在于，还包括：
在移除所述面板以前，在所述一个或多个布线层之上形成外部导电接触部的阵列，并且将所述外部导电接触部的阵列与所述一个或多个布线层电耦合。
20.如权利要求19所述的工艺，其特征在于，形成所述外部导电接触部的阵列包括形成球栅阵列（BGA）。
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