1307940 九、發明說明： 【發明之領域】 本發明係提供一種半導體封裝結構的製作方法，尤指—種穿 過基板的堆豐式晶粒大小封裝(thr〇Ugh substrate stackec} chip sc此 package，ts-SCSP)結構的製作方法。 【背景說明】 近年來，隨著筆記型電腦、個人資料助理（PDA)與行動電 話等攜帶式機器的小型化與高功能化，使半導體製程不僅需朝向 向積集度發展’也必需朝向高密度(highdensity)封裝發展。尤其是 數位時代的來臨，基本上各種攜帶式機器都會被研發者朝向行動 通訊的方向發展。例如行動電話，為配合瀏覽網頁(webbrowsing) 以及文子戒息(text message)的功能被整合，逐漸採用較大的顯示榮 幕，如果加上操作面板(key pad)以及符合人體工學的把手，殼體的 本身已不太容易在X以及Y方向上再縮小，如欲製作出體積更小以 及重量更輕、更薄的機型，就必需將殼體的厚度降低。因此，最 新的封裝趨勢除了高密度化之外，也必需超薄化。 在提昇封裝密度方面係取決於封裝之承載器（carrier)的尺 寸，以及晶片與承載器接合所佔之空間，其中’承載器包括習知 的導線架，或是具有開口之積層板（】aminate substrate)。對於單 1307940 、壯 半‘體封裝*吕’晶片上有導腳（leadonchip, LOC)之 封衣二構是常見縮小晶片與承載器接合所佔空間的方法。LOC架 ^係指承翻之導腳延伸至晶片中央的接合墊，導贿晶片主動 壯連接’/亦同時提供晶片物理上之支撐，因此可以縮小整個封 、體積❿承載器包括習知的L〇c型態之導線架，或是具有開 口之積層板 Oaminate substrate )。 而對於多晶粒積體電路之封裝而言，多晶片封裝模組 C_ti-chlp m〇dule，MCM)為常見高密度之封裝結構。根據 不同的積體電路設計需求’將多個晶片同時封裝於同一承載器 上不但此縮小封裝體積，減少製程費用，且因為晶片間訊號傳 遞=徑(讀)縮短，故可改善高頻率特性，增加效能。目前mcm L系架構在印刷電路板（口如㈣也㈣b〇ar(j)上，以將多個晶 片配置於印刷電路板之同一表面，而晶片肖電路板連接方式包括 打線（wire bonding)、敕片自動接合（tape加_流_出叩，MB ) 或覆晶（flipchip)的方式。至於前面所提及之超薄化，則必需對 封褒結構巾之各種封裝娜以及封裝結構本相配置來做努力。 目前吸引許多人貞投人研發的晶粒大小包裝(ehip scale PackaSe)，其大小只約為晶粒尺寸(die size)的110〜120%，自推出以 來，廣受市場歡迎。因為它不只適合顧於各種攜帶式電子產品 1307940 之内，也適合大量應用於各種智慧卡(smartcard)之上，未來仍舊 有十分廣大的發展空間，並且也是朝著高密度化以及超薄化的方 向在發展。 δ月參照圖一 ’圖一為習知堆疊式晶粒大小封裝(stackecJ chip scale package)結構30之示意圖。如圖一所示，將一晶粒12之主動 表面朝上’以絕緣黏著劑14 (insulationglue)塗抹於晶粒12之背 面’並將晶粒12貼附於一基板1〇之一預定區域上，以溫度15〇。〇加 熱烘烤固化晶粒12。接著利用打線（wire bonding )方式，以銅線 15電連接晶粒12之主動表面上之接合墊16與基板1〇上相對應的接 點（未顯示）。然後將另一晶粒18之主動表面朝上，利用絕緣黏 著劑14塗抹於晶粒18之背面，並將晶粒18貼附於晶粒12之一預定 區域上，再以溫度150°C加熱烘烤固化晶粒18。隨著利用打線方 式’以銅線15電連接晶粒18之主動表面上之接合墊22與基板1〇上 相對應的接點（未顯示）。 然後以一封裝材料24完整覆蓋晶粒12、晶粒18以及銅線15.， 並加熱烘烤使封裝材料24固化。之後再進行一蝕刻製程以於基板 10下側形成複數個以球格陣列（ball grid array, BGA )方式排列之 焊球墊（未顯示），並焊接複數個錫球26於複數個焊球墊上。其 中，錫球26用來電連接整個堆疊式晶粒大小封裝結構3〇與—印^ 1307940 電路板（未顯示），而基板10内部具有一電路（未顯示），用來 電連接基板U)之接點與錫球26，因此晶粒12與晶粒!何透過銅線 15、基板10内部之電路與錫球26以電連接印刷電路板。此外，基 _為-積層板，黏著劑14為一高分子材料，封裝材料⑽陶究、 玻璃環氧樹脂或BT樹脂（BTresin)。 在圖一中所顯示的係為一薄型微細間距球格陣列（出比朽收 Pitch ball grid array，TFBGA)封裝結構。而此種堆疊式晶粒大小封 裝結構的觀念，亦可以應用至其他的封裝結構。請參考圖二，圖 二為另一習知堆疊式晶粒大小封裝(stacked chip sca】e package)結 構50之示意圖’並且此封裝結構被稱為TSOP (thin small outline package)。如圖二所示，堆疊式晶粒大小封裝結構5〇之承載器係為 一導線架52，一主動區域朝上之晶粒54以及一主動區域朝下之晶 粒56分別被黏著於導線架52的上方以及下方。再利用打線的方 式’以銅線55分別電連接晶粒52之主動表面上之接合塾58與導線 架52上相對應的接點（未顯示），以及晶粒54之主動表面上之接 合墊62與導線架52上相對應的接點（未顯示）。此外，堆疊式晶 粒大小封裝結構50另包含有一經固化(cured)的封裝材料64，用來 完整覆蓋晶粒52、晶粒58以及銅線55。 習知的堆疊式晶粒大小封裝結構是將晶粒配置於基板或是其 1307940 >載=上以圖—中的封裝結構而言，完成後整個封裝體的 门度係等於；!：干球塾上之錫球底端_〇叫至封裝材料頂端(鄉)之· 距離換句知，即為焊球墊上之錫球、基板、絕緣黏著劑、晶· 粒以及晶粒上之封裝材料的厚度總和。-般而言，目前所製作出 隹X式粒大小封裝體的减均切〗_0腿，以薄顧細間距球 格陣列封裝結構以及薄小包裝結構為例，最後的封裝體高度約為 1·2·。然而’在—⑽新型的電子產品中，封裝結構的高度有呈 厭格的限制’必需姐8酬以下甚至於更小，以先前技術方法所製鲁 作的堆豐式晶粒大小封裝結構之高度，顯然無法達到此要求，往 往造成_上的_，並連帶影響到新型電子產品的開發。因此， 如何開♦出-齡4式晶粒大小封裝結構，其可降麵裝高度， 又不至於影_散熱舰，便成為十分重要的課題。 【發明概述】 因此，本發明之主要目的在於提供一種穿過基板的堆疊式晶馨 ^A^,f^(throughsubstrate^ ^ ts sc^ 結構，以降低封裝高度而得以翻於_則、的電子產品之内。 本發明之另-目的在於提供一種穿過基板的堆疊式晶粒大小 封染SCSP)結構，蝴緣__性以及高簡度_ reliability)砉規。 1307940 在本發明之最佳實施例中，传 .Ε, 係先楗供一基板，且該基板包含 - 有至^ 一窗口、複數個凸塊焊勢、;^奴/ 兄^墊後數個接腳以及一電路，接著 * 利用一承載膠帶來提供該窗口至 口週圍之該基板的物理連 接，隨後再將複數個晶粒依序黏著於該窗口内之該承载膠帶上， /複數個阳粒之主動表面另包含有複數個接合塾，然後進行一 打線製程，以電連接該複數個接合域各該相對應之凸塊焊塾， 最後進行-封膠製程’以完整包覆該基板、該導線以及該複數個鲁 晶粒，並去除該承載膠帶。 本發明利用具有窗σ以及承娜帶的基板為封裝架構，將複 數個具有_魏或不同讀，_大小或糊大小之晶粒配置 於基板内之窗口的承載膠帶之上。由於晶粒並非疊加於基板之 上’整個封裝體的厚度將可㈣顯被降低。此外，在晶粒的背面 直接暴露至環境的情況下，更可藉由設計而被附著至一散熱座，嫌 以幫助散熱，提昇封裝體在高溫情況下的電性表現以及信賴度。 【發明之詳細說明】 請參照圖三至圖五，圖三至圖五為製作本發明之穿過基板堆 疊式晶粒大小封裝(through substrate stacked chip scale package， ts-SCSP)結構100的方法示意圖。如圖三所示，首先提供一具有一 10 1307940 1¾ 口 104之基板102。基板102係為一雙層(^o—iayered)板，其材質 為玻璃環氧基樹脂（FR-4、FR-5)或雙順丁烯二酸醯亞胺 - (Bismaleimide-Triazii^BT)，並利用一承載膠帶(carriertape)1〇6 ‘ 來提供窗口 104以及基板1〇2之物理連接。值得一提的是，基板1〇2 的内部另設有一電路(未顯示)以及複數個導通孔(via)1〇8，用來電 連接複數個之後會被形成的錫球(未顯示）。 如圖四所示，接著將一晶粒112之主動表面背向窗口内之承載春 膠帶106，以絕緣黏著劑114 (insulati〇nglue)塗抹於晶粒112之背 面，並將晶粒112貼附於窗口 1〇4内之承載膠帶1〇6之上，再以15〇 °C左右之溫度加熱烘烤固化晶粒丨丨2。隨後利用打線(wire b〇nding ) 方式，以銅線115電連接晶粒Π2之主動表面上之接合塾1丨6與基板 102上相對應的接點（未顯示）。然後將另一晶粒118之主動表面 背向窗口内之晶粒112，以絕緣黏著劑114塗抹於晶粒118之背面， 並將晶粒118貼附於晶粒Π2之一預定區域上，再以150°c左右之溫參 度加熱烘烤固化晶粒118。同樣地，接著再利用打線方式，以銅線 115電連接晶粒118之主動表面上之接合墊122與基板1〇2上相對應 的接點（未顯示）。在以上的製程中，於封裝體完成之前，承載 膠帶104提供了暫時支持(hold)晶粒112以及晶粒118的作用。其 中，晶粒112與118可為邏輯（bgic)電路晶粒、SRAM晶粒、dram 晶粒、中央處理單元（CPu)晶粒或快閃記憶體（flashmem〇ry) 11 1307940 晶粒專之晶粒。 隨後如圖五所示，以—封裂材料124完整覆蓋晶粒112、晶粒. ns以及mm，並加触烤使封裝材料丨湖化，賴去除承載 膠〇rl06。由於此時封裝材料已經被固化㈣_，封裝結構因而得 以具有-定喊械錢，所以移除承載料並不會騎裝結構產 生破壞。之後再進行-侧製如祕板丨町娜成複數個以球 格陣列（ball grid array，BGA )方式排列之焊球墊（未顯示），並參 焊接複數個錫球126於複數個焊球塾上。其中，錫球126用來電連 接整個穿過基板堆疊式晶粒大小封裝(ts_SCSp)結構1 〇〇與一印刷 電路板（未顯tjt) ’ *基板脱内部的電路（細示）以及導通孔 108，係用來電連接基板102之接點與錫球126，因此晶粒ιΐ2與晶 粒118可透過銅線115、基板1〇2内部之電路與鍚球126以電連接印 刷電路板。 雖然在圖示中只以單-結構來作說明，但事實上基板i〇2係為 複數個重複性的結構，因此於上述步驟之後，還要再進行一個被 稱為切單(singulation)的步驟’才算完成穿過基板堆疊式晶粒大小 封裝(ts-SCSP)結構100的製作。此外，黏著劑114為一高分子材料， 封裝材料m為陶究、玻璃環氧樹脂或Βτ樹脂（BTresin)。由於 完成後整個封裝體的高度’係等於焊球塾上之錫球底端⑽—至 12 1307940 封裝材料頂端(top)之距離。關五所示之堆疊式晶粒大小封裂結 構100而5，係為焊球墊上之錫球126以及基板1〇2的厚度總和。若 基板102的厚度係為0.36mm，封裝體完成後的錫球126厚度係為 - 〇.21mm，最後的封裝體高度即為〇.57mn^同時，晶粒I〗]、U8 的厚度約為4mils(相當於㈣遍叫，承載膠帶刚的厚度約為⑽ #m(相當於o.imm)。 另外’因為晶粒m的背面如咖卿係為直接暴露㈣㈣出φ 來’故可視實際之需求並經由設計而附著以一散熱座邮來 幫助散熱(heatdissipation) ’進而提昇封裝體在高溫情況下的電性 表現(electrical performance)以及信賴度(rdiabiiity)。值得一提的 是’晶粒112以及晶粒118的大小可以一致或是不一致。另外，相 同的封裝概糾可延伸至三個或三個以上晶粒的封裝結構，於實 把時基板的厚度也必需相應增加，成為—四層咖咖响板或是 六層Gix-layered；)板等之多層(multi_丨吵⑽由板。 籲 圖五中所示的封褒結構係兩個不同晶粒之主動表面均朝向同 -方向’而在本發_第二實施例巾，_不同晶粒之主動表面 係朝向相反的方向。請參相六至圖人，圖六製以為製作本發 明中第二實施例之穿過基板堆疊式晶粒大小封·scsp)結構 200的方法示意圖。如圖六所示，首先提供—具有―窗口綱之基 13 1307940 板2〇2，基板2〇2係為一Ktwo_iayered)板，其材質為玻璃環氧基 樹脂（FR-4、FR-5 )或雙順丁稀二酸醯亞胺（Bismaleimide_Triazine， BT)，並利用一承載膠帶(carriertape)2〇6來提供窗口2〇4以及基板- 202之物理連接。值得一提的是，基板2〇2的内部具有一電路(未顯 示)以及複數個導通孔208,用來電連接複數個之後會被形成的錫球 (未顯示）。 如圖七所示’接著將一晶粒212之主動表面朝向承載料 _ 206，再將晶粒212貼附於窗口2〇4内之承載膠帶2〇6之上。然後將 另一晶粒218之主動表面朝向窗口 2〇4，以絕緣黏著劑2〗4塗抹於晶 粒218之背面，並將晶粒218貼附於晶粒212之一預定區域上，再以 溫度150C加熱烘烤固化晶粒218。接著利用打線方式，以銅線215 電連接晶粒218之主動纟面上之接合塾222與裂反2〇2上相對應的 接點（未顯示）。在以上的製程巾，於封裝體完成之前，承載膠 帶206提供了暫時支持(_)晶粒212以及晶粒218的作用。其中，馨 晶粒212與218可為邏輯（l〇gic)電路晶粒、SRAM曰曰曰粒、dram 晶粒、中央處理單元（CPU)曰曰曰粒或快閃記憶體（flashmem〇iy) 晶粒等之晶粒。 如圖八所示，然後以-封裝材料224完整覆蓋晶粒212、晶粒 218以及銅線215 ’並加熱烘烤使封裝材料224固化，再去除承載膠 14 1307940 帶206。由於此時封裝材料已經被固化(curecj) ’封裝結構已具有一 定的機械強度’移除承載膠帶206並不會對封裝結構產生破壞。隨 後利用打線（wirebonding)方式，以銅線215電連接晶粒212之主 動表面上之接合墊216與基板202上相對應的接點（未顯示），接 著以一封裝材料224完整覆蓋晶粒212以及銅線215，並加熱烘烤使 封裝材料224固化。 再進行一蝕刻製程以於基板202下側形成複數個以球格陣列 (ball grid array，BGA)方式排列之焊球墊（未顯示），並焊接複 數個錫球226於複數個焊球墊上。其中，錫球226係用來電連接整 個穿過基板堆疊式晶粒大小封裝(ts_scsp)結構2〇〇與一印刷電路 板（未顯示），而基板2〇2内部的電路（未顯示）以及導通孔2〇8， 係用來電連接基板202之接點與錫球226，因此晶粒212與晶粒218 可透過鋼線215、基板2G2内部之電路與錫球226以電連接印刷電路 板最後再進行一個被稱為切單(singulati〇n)的步驟，以完成穿過 基板堆疊式晶粒大小封裝(ts_scsp)結構2〇〇的製作。 由於完成後整個封裝體的高度，係等於焊球墊上之錫球底端 (bottom)至封裝材料頂端(t〇p)之距離。以圖八所示之堆疊式晶粒大 J封裝、、’。構2〇〇而5 ’係為焊球墊上之錫球η6、基板搬以及基板 皿上方封裝材料的厚度總和。若基板2_厚度係狀麻爪，封 15 1307940 破體元成後的錫球126厚度係為0.21mm，基板202上方封裝材料的 厚度係為0.20mm ’最後的封裝體高度即為〇77mm。同時，晶粒 212、218的厚度約為4mils(相當於〇 1〇16_ ’承載膠帶2〇6的厚度 約為100/m(相當於〇.imm)。值得一提的是，晶粒212以及晶粒218 的大小可以-致或是不—致。同獅，相同的封裝概念亦可延伸 至三個或三個以上晶粒的封裝結構，於實施時基板的厚度也必需 相應增加，絲-四層(f(W_laye_板歧六層恤妨㈣)板等之 多層(multi-layered)板。 簡而言之’本發明係糊具有窗口以及承娜帶的基板為封 裝架構’⑽複數健有相同魏或不同魏，綱大小或不同 大小之晶粒配置於基㈣之窗口的承娜帶之上。如此—來，因 為晶粒並非疊加於基板之上，油封裝體的厚度將可以明顯被降 低’而且由於晶粒魅縣駐外界魏的情況下，更可大幅提 南晶片（chip)的散熱性。 相較於習知晶粒直接配置於基板上之方法，本發明利用且有 窗口以及承載膠帶的基板作為封裝架構，將複數個具有相同功能 或不同功i，姻大小或不同大小之晶粒配置於基㈣之窗口的 承載膠帶之上，以有效降低封裝體的厚度。此外，由於晶粒係直 接暴露至環境的情況下，故可财際之需求並經由設計而再附著 16 1307940 以-散熱絲獅賴，進喊昇職财高溫情況 現以及信賴。 衣 以上所述鶴本發日狀較佳實蘭，凡依本發日科請專利範 圍所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。 【圖示之簡單說明】 圖一為習知堆疊式晶粒大小封裝結構之示意圖。 圖二為另一習知堆疊式晶粒大小封裝結構之示意圖。 圖二至圖五為製作本發明之穿過基板堆疊式晶粒大小封裝結 構的方法示意圖。 圖六至圖八為製作本發明中第二實施例之穿過基板堆疊式晶 粒大小封襞結構的方法示意圖。 【圖示之符號說明】 10 基板 12 晶粒 14 絕緣黏著劑 15 銅線 16 接合墊 18 晶粒 22 接合墊 24 封裝材料 26 錫球 17 1307940 30 堆疊式晶粒大小封裝結構 50 堆疊式晶粒大小封裝 52 導線架 54 晶粒 55 銅線 56 晶粒 58 接合塾 62 接合墊 64 封裝材料 100 穿過基板堆疊式晶粒大小封裝結構 102 基板 104 窗口 106 承載膠帶 108 導通孔 112 晶粒 114 絕緣黏著劑 115 銅線 116 接合墊 118 晶粒 122 接合墊 124 封裝材料 126 錫球 200 穿過基板堆疊式晶粒大小封裝結構 202 基板 204 窗口 206 承載膠帶 208 導通孔 212 晶粒 214 絕緣黏著劑 215 銅線 216 接合墊 218 晶粒 222 接合墊 224 封裝材料 226 錫球1307940 IX. Description of the Invention: [Technical Field] The present invention provides a method for fabricating a semiconductor package structure, in particular, a stack-type grain size package (thr〇Ugh substrate stackec) chip sc through the substrate, ts-SCSP) structure manufacturing method. [Background] In recent years, with the miniaturization and high functionality of portable devices such as notebook computers, personal data assistants (PDAs) and mobile phones, semiconductor processes have not only developed toward accumulating degrees, but also must be oriented toward high Density packaging development. Especially in the digital age, basically all kinds of portable machines will be developed by developers towards mobile communication. For example, mobile phones are integrated with the functions of webbrowsing and text messages, and gradually adopt a larger display screen. If a key pad and an ergonomic handle are added, The housing itself is less likely to shrink in the X and Y directions. To make a smaller and lighter, thinner model, it is necessary to reduce the thickness of the housing. Therefore, in addition to high density, the latest packaging trends must be ultra-thin. In terms of increasing the packing density, it depends on the size of the package carrier and the space occupied by the wafer and the carrier. The 'carrier includes a conventional lead frame or a laminated board with an opening. Substrate). For the single 1307940, the "packaged" (lead chip) of the "sleeve" (LDC) wafer is a common method for reducing the space occupied by the wafer and the carrier. The LOC frame refers to the bonding pad that extends to the center of the wafer, and the briquette wafer actively connects to the body.//The physical support of the wafer is also provided, so that the entire sealing and volume carrier can be reduced, including the conventional L. 〇c-type lead frame, or laminated board with opening OAMinate substrate). For multi-die integrated circuit packages, the multi-chip package module C_ti-chlp m〇dule, MCM) is a common high-density package structure. According to different integrated circuit design requirements, the simultaneous packaging of multiple wafers on the same carrier not only reduces the package size, reduces the process cost, but also improves the high frequency characteristics because the signal transmission between the wafers = the diameter (read) is shortened. Increase performance. At present, the mcm L-system is on a printed circuit board (such as (4) and (4) b〇ar (j), so that a plurality of wafers are disposed on the same surface of the printed circuit board, and the wafer connection method includes wire bonding, The cymbal is automatically joined (tape plus _flow _ 叩, MB) or flip chip. As for the ultra-thinning mentioned above, it is necessary to encapsulate the various structures of the sealing structure and the packaging structure. Configuration to make efforts. Currently attracting many people to invest in the development of the chip size package (ehip scale PackaSe), its size is only about 110~120% of the die size (die size), since its launch, it has been widely welcomed by the market. Because it is not only suitable for all kinds of portable electronic products 1307940, but also suitable for a large number of smart cards, it still has a lot of development space in the future, and it is also towards high density and ultra-thinning. The direction is developing. δ month refers to Figure 1 'Figure 1 is a schematic diagram of a conventional stackecJ chip scale package structure 30. As shown in Figure 1, the active surface of a die 12 is facing upwards' An insulating adhesive 14 is applied to the back surface of the die 12 and the die 12 is attached to a predetermined area of a substrate 1 at a temperature of 15 Torr. The baked solidified die 12 is heated and baked. The wire bonding method electrically connects the bonding pads 16 on the active surface of the die 12 to the corresponding contacts on the substrate 1 (not shown). Then, the active surface of the other die 18 faces upward. Applying an insulating adhesive 14 to the back surface of the die 18, and attaching the die 18 to a predetermined area of the die 12, and heating and baking the cured die 18 at a temperature of 150 ° C. 'The copper wire 15 electrically connects the bond pads 22 on the active surface of the die 18 to the corresponding contacts on the substrate 1 (not shown). The die 12, the die 18 and the copper are then completely covered by a package material 24. Line 15. and heating and baking to cure the encapsulating material 24. Thereafter, an etching process is performed to form a plurality of solder ball mats (not shown) arranged on the lower side of the substrate 10 in a ball grid array (BGA) manner. And soldering a plurality of solder balls 26 to a plurality of solder ball pads. The solder ball 26 is used to electrically connect the entire stacked die-size package structure 3 and the printed circuit board (not shown), and the substrate 10 has a circuit (not shown) for electrically connecting the substrate U). The dots and the solder balls 26, and thus the crystal grains 12 and the crystal grains, are transmitted through the copper wires 15, the circuits inside the substrate 10, and the solder balls 26 to electrically connect the printed circuit boards. Further, the base layer is a laminate, the adhesive 14 is a polymer material, and the encapsulating material (10) is a ceramic material, a glass epoxy resin or a BT resin (BTresin). Shown in Figure 1 is a thin Pitch ball grid array (TFBGA) package structure. The concept of such a stacked die size package structure can also be applied to other package structures. Referring to FIG. 2, FIG. 2 is a schematic diagram of another conventional stacked chip sca package e package structure and is referred to as a TSOP (thin small outline package). As shown in FIG. 2, the carrier of the stacked die-size package structure is a lead frame 52, an active area facing upward die 54 and an active area downward facing die 56 are respectively adhered to the lead frame. Above and below 52. Then, the wire bonding method is used to electrically connect the bonding pads 58 on the active surface of the die 52 to the corresponding contacts on the lead frame 52 (not shown), and the bonding pads on the active surface of the die 54. 62 corresponds to a corresponding point on the lead frame 52 (not shown). In addition, the stacked grain size package structure 50 further includes a cured package material 64 for completely covering the die 52, the die 58 and the copper wire 55. The conventional stacked die-size package structure is to arrange the die on the substrate or the package structure in the figure of 1307940 and the above-mentioned package. After completion, the degree of the door of the whole package is equal to; The bottom end of the solder ball on the ball 〇 〇 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到The sum of the thicknesses. Generally speaking, the subtractive-cutting _0 leg of the 隹X-type grain size package is currently produced, taking a thin-pitch ball grid array package structure and a thin package structure as an example, and the final package height is about 1 ·2·. However, in the new electronic products of (10), the height of the package structure is disproportionately limited, and it is required to be smaller or smaller, and the stack-type grain size package structure made by the prior art method is Height, obviously can not meet this requirement, often resulting in _, and associated with the development of new electronic products. Therefore, how to open the 龄-out 4 type grain size package structure, which can reduce the surface mount height, and not to shadow the heat sink, has become an important issue. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a stacked crystal substrate that passes through a substrate to reduce the height of the package and to turn over the electrons. Further within the product, it is another object of the present invention to provide a stacked grain size sealed SCSP structure, a rim and a high simplification _ reliability. 1307940 In a preferred embodiment of the present invention, the substrate is first supplied to a substrate, and the substrate comprises - a window to a plurality of bumps, and a plurality of bumps; a pin and a circuit, and then * using a carrier tape to provide a physical connection of the window to the substrate around the port, and then sequentially bonding a plurality of dies to the carrier tape in the window, / a plurality of yang The active surface of the particle further comprises a plurality of bonding defects, and then performing a wire bonding process to electrically connect the corresponding bonding pads of the plurality of bonding domains, and finally performing a sealing process to completely cover the substrate, The wire and the plurality of rugs are removed and the carrier tape is removed. The present invention utilizes a substrate having a window σ and a enamel band as a package structure, and a plurality of dies having a wei or different read, _ size or paste size are disposed on a carrier tape of a window in the substrate. Since the grains are not superimposed on the substrate, the thickness of the entire package will be significantly reduced. In addition, in the case where the back surface of the die is directly exposed to the environment, it can be attached to a heat sink by design to help dissipate heat and improve the electrical performance and reliability of the package at high temperatures. DETAILED DESCRIPTION OF THE INVENTION Referring to FIG. 3 to FIG. 5, FIG. 3 to FIG. 5 are schematic diagrams showing a method for fabricating a through substrate stacked chip scale package (ts-SCSP) structure 100 of the present invention. . As shown in FIG. 3, a substrate 102 having a 10 1307940 13⁄4 port 104 is first provided. The substrate 102 is a two-layered (^o-iayered) plate made of glass epoxy resin (FR-4, FR-5) or bismuthimide-bis (Bismaleimide-Triazii^BT). And using a carrier tape 1 〇 6 ' to provide a physical connection between the window 104 and the substrate 1 〇 2 . It is worth mentioning that the inside of the substrate 1〇2 is further provided with a circuit (not shown) and a plurality of vias 1〇8 for electrically connecting a plurality of solder balls (not shown) which are formed later. As shown in FIG. 4, the active surface of a die 112 is then applied back to the spring-loaded tape 106 in the window, and the insulating adhesive 114 is applied to the back surface of the die 112, and the die 112 is attached. Above the carrier tape 1〇6 in the window 1〇4, the solidified grain 丨丨2 is heated and baked at a temperature of about 15 °C. Subsequently, a copper wire 115 is used to electrically connect the bonding pads 1 on the active surface of the die 2 to the corresponding contacts (not shown) on the substrate 102 by means of wire b〇nding. Then, the active surface of the other die 118 is turned away from the die 112 in the window, the insulating adhesive 114 is applied to the back surface of the die 118, and the die 118 is attached to a predetermined area of the die 2, and then The solidified grains 118 are baked and baked at a temperature of about 150 ° C. Similarly, the bonding wire 122 on the active surface of the die 118 is electrically connected to the corresponding pad (not shown) on the substrate 1 2 by the bonding method. In the above process, the carrier tape 104 provides the role of temporarily holding the die 112 and the die 118 before the package is completed. Wherein, the grains 112 and 118 may be logic (bgic) circuit dies, SRAM dies, dram dies, central processing unit (CPu) dies or flash memory (flashmem 〇ry) 11 1307940 grain. Then, as shown in FIG. 5, the sealing material 124 completely covers the crystal grains 112, the crystal grains, the ns and the mm, and is baked to make the encapsulating material immersed in the lake, and the carrier 155 is removed. Since the encapsulating material has been cured (4) _, the package structure has to be fixed, so that the removal of the carrier material does not cause damage to the riding structure. After that, the side-side system, such as the secret board, is a plurality of ball grid arrays (BGA) arranged in a ball grid array (BGA), and is welded to a plurality of solder balls 126 in a plurality of solder balls.塾上. Wherein, the solder balls 126 are used to electrically connect the entire through-substrate stacked die-size package (ts_SCSp) structure 1 and a printed circuit board (not shown) (the circuit is removed from the substrate) and the vias 108 For electrically connecting the contacts of the substrate 102 and the solder balls 126, the die ΐ 2 and the die 118 can pass through the copper wires 115, the circuit inside the substrate 1 and the ball 126 to electrically connect the printed circuit board. Although only the single-structure is illustrated in the drawings, the substrate i〇2 is actually a plurality of repetitive structures. Therefore, after the above steps, another process called singulation is performed. The step 'completes the fabrication of the through-substrate stacked die size package (ts-SCSP) structure 100. Further, the adhesive 114 is a polymer material, and the encapsulating material m is ceramic, glass epoxy or BT resin. Since the height of the entire package after completion is equal to the distance from the bottom end of the solder ball on the solder ball (10) to the top of the 12 1307940 package material. The stacked grain size sealing structures 100 and 5 shown in FIG. 5 are the sum of the thicknesses of the solder balls 126 and the substrate 1〇2 on the solder ball pads. If the thickness of the substrate 102 is 0.36 mm, the thickness of the solder ball 126 after the package is completed is -21.21 mm, and the height of the final package is 〇.57mn^, and the thickness of the grain I] and U8 is about 4mils (equivalent to (four) times, the thickness of the carrying tape is just about (10) #m (equivalent to o.imm). In addition, because the back of the grain m is directly exposed (4) (four) out of φ, it can be seen as actual. The demand is attached by design to a heat sink to help heat dissipation (heatdissipation), thereby improving the electrical performance and reliability (rdiabiiity) of the package at high temperatures. It is worth mentioning that 'die 112 And the size of the die 118 can be uniform or inconsistent. In addition, the same package can be extended to three or more die packaging structures, and the thickness of the substrate must be correspondingly increased to become four layers. Multi-layered board (such as multi-noise (10) by the board. The sealing structure shown in Figure 5 is the same as the active surface of two different grains. 'And in the present hair _ second embodiment towel, _ different Active surface of the grain-based opposite directions. Referring to FIG phase six people six FIG made that method of manufacturing a schematic view of the present invention in a second embodiment of a stacked substrate through the grain size of the sealing · scsp) structure 200. As shown in Fig. 6, firstly, a substrate with a window of 13 1307940, a substrate 2〇2, and a substrate 2〇2 is a Ktwo_iayered plate, which is made of glass epoxy resin (FR-4, FR-5). Or Bismaleimide_Triazine (BT), and a carriertape 2〇6 is used to provide a physical connection between the window 2〇4 and the substrate-202. It is worth mentioning that the inside of the substrate 2〇2 has a circuit (not shown) and a plurality of via holes 208 for electrically connecting a plurality of solder balls (not shown) which are then formed. As shown in Fig. 7, the active surface of a die 212 is then directed toward the carrier _ 206, and the die 212 is attached to the carrier tape 2 〇 6 in the window 2〇4. Then, the active surface of the other die 218 is directed toward the window 2〇4, the insulating adhesive 2 is applied to the back surface of the die 218, and the die 218 is attached to a predetermined area of the die 212, and then The solidified grains 218 are baked by heating at a temperature of 150C. Then, the bonding wire 222 on the active surface of the die 218 is electrically connected to the corresponding contact point (not shown) on the splitting surface 2 2 by the wire bonding method. In the above process towel, the carrier tape 206 provides temporary support for (_) die 212 and die 218 prior to completion of the package. Among them, the sinuous grains 212 and 218 can be logic (l〇gic) circuit dies, SRAM granules, dram dies, central processing unit (CPU) 曰曰曰 granules or flash memory (flashmem 〇 iy) Grains of grains and the like. As shown in FIG. 8, the die 212, the die 218, and the copper wire 215' are then completely covered with a package material 224 and baked to cure the encapsulation material 224, and the carrier tape 14 1307940 tape 206 is removed. Since the encapsulating material has been cured at this time, the encapsulating structure has a certain mechanical strength. The removal of the carrier tape 206 does not cause damage to the package structure. Then, the bonding pads 216 on the active surface of the die 212 are electrically connected to the corresponding pads (not shown) on the substrate 202 by wire bonding, and then the die 212 is completely covered by a sealing material 224. The copper wire 215 is heated and baked to cure the encapsulating material 224. An etching process is further performed to form a plurality of solder ball pads (not shown) arranged on the lower side of the substrate 202 in a ball grid array (BGA) manner, and soldering a plurality of solder balls 226 on the plurality of solder ball pads. Wherein, the solder ball 226 is used to electrically connect the entire through-substrate stacked die-size package (ts_scsp) structure 2〇〇 and a printed circuit board (not shown), and the circuit (not shown) inside the substrate 2〇2 and the turn-on The holes 2〇8 are used to electrically connect the contacts of the substrate 202 and the solder balls 226. Therefore, the die 212 and the die 218 can pass through the steel wire 215, the circuit inside the substrate 2G2 and the solder ball 226 to electrically connect the printed circuit board. A step called singulating is performed to complete the fabrication of the stacked chip size package (ts_scsp) structure through the substrate. Since the height of the entire package after completion is equal to the distance from the bottom of the solder ball on the solder ball pad to the top of the package material (t〇p). As shown in Figure 8, the stacked die large J package, '. The structure is 2〇〇 and 5' is the sum of the thicknesses of the solder balls η6 on the solder ball pads, the substrate transfer, and the encapsulation material above the substrate. If the substrate 2_thickness is pegs, the thickness of the solder balls 126 after the breakage of the fuses is 0.21 mm, and the thickness of the encapsulation material above the substrate 202 is 0.20 mm'. The final package height is 〇77 mm. At the same time, the thickness of the grains 212, 218 is about 4 mils (corresponding to the thickness of the 〇1〇16_' carrying tape 2〇6 is about 100/m (equivalent to 〇.imm). It is worth mentioning that the die 212 and The size of the die 218 can be either - or not. With the lion, the same package concept can be extended to three or more die packages, and the thickness of the substrate must be increased accordingly. Four layers (f (W_laye_板6-piece six-piece) (multi-layered) board. In short, 'the invention has a window and the substrate of the substrate is a package structure' (10) complex health The same or different Wei, the size of the size or the size of the crystal is placed on the base of the base (4) window. So, because the grain is not superimposed on the substrate, the thickness of the oil package will be obvious It is reduced' and the heat dissipation of the south chip can be greatly improved due to the fact that the grain is located in the outside world. Compared with the conventional method in which the die is directly disposed on the substrate, the present invention utilizes and has a window and a load. The substrate of the tape is used as a package structure, and the plurality of phases have a phase The function or the different work i, the size of the size or the size of the die is placed on the carrying tape of the window of the base (4) to effectively reduce the thickness of the package. In addition, due to the direct exposure of the die to the environment, The demand for finance has been re-attached by design. 16 1307940 - The heat sink is the lion, and the high temperature situation of the promotion is now and trustworthy. The average variation and modification of the patent range should be covered by the patent of the present invention. [Simplified illustration of the drawing] Figure 1 is a schematic diagram of a conventional stacked grain size package structure. Figure 2 is another conventional stack. Schematic diagram of a grain size package structure. Figures 2 to 5 are schematic views of a method for fabricating a stacked die size package structure of the present invention. Fig. 6 to Fig. 8 are diagrams for fabricating the second embodiment of the present invention. Schematic diagram of the method of stacking the substrate size of the substrate. [Description of symbols] 10 substrate 12 die 14 insulating adhesive 15 copper wire 16 bonding pad 18 die 22 bonding pad 24 Material 26 Tin Ball 17 1307940 30 Stacked Grain Size Package 50 Stacked Grain Size Package 52 Lead Frame 54 Die 55 Copper Wire 56 Die 58 Bonding 塾 62 Bond Pad 64 Packaging Material 100 Through Substrate Stacked Grain Size Package Structure 102 Substrate 104 Window 106 Carrier Tape 108 Via Hole 112 Grain 114 Insulation Adhesive 115 Copper Wire 116 Bond Pad 118 Die 122 Bond Pad 124 Package Material 126 Tin Ball 200 Through Substrate Stacked Grain Size Package Structure 202 Substrate 204 Window 206 Carrier Tape 208 Via Hole 212 Die 214 Insulation Adhesive 215 Copper Wire 216 Bond Pad 218 Die 222 Bond Pad 224 Packaging Material 226 Tin Ball
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