CN112400227B - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

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Publication number
CN112400227B
CN112400227B CN201980005827.2A CN201980005827A CN112400227B CN 112400227 B CN112400227 B CN 112400227B CN 201980005827 A CN201980005827 A CN 201980005827A CN 112400227 B CN112400227 B CN 112400227B
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layer
circuit layer
electronic element
electronic component
electronic
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CN112400227A (zh
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傅志杰
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Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Avary Holding Shenzhen Co Ltd
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Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Avary Holding Shenzhen Co Ltd
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Abstract

一种封装结构，包括内层线路层、第一介质层、第一外层线路层及电子组件，所述第一介质层包括第一表面及与所述第一表面相对第二表面，所述内层线路层及所述电子组件从所述第一表面嵌入所述第一介质层，所述第一外层线路层设置于所述第二表面，所述电子组件包括第一电子元件及第二电子元件，所述第二电子元件靠近所述第二表面设置，且所述第二电子元件的电连接端朝向所述第二表面，所述第一电子元件设置于所述第二电子元件背离第二表面的一侧，并且所述第一电子元件从所述第一表面露出，所述第一外层线路分别与所述第二电子元件的电连接端及所述内层线路层电连接。本发明还有必要提供一种封装结构的制造方法。

Description

封装结构及其制造方法
技术领域
本发明涉及封装领域，尤其涉及一种封装结构及其制造方法。
背景技术
现有的内埋元件的电路板，由于其制作工艺的限制，只能在一个容纳腔内装入一个元件，而无法将多个元件堆叠设置。当需要内埋多个元件时，只能在电路板上设置多个容纳腔，因此会占用大量空间。此外，装入的元件只能在单侧与电路板的线路层连接，这会限制线路设计。
发明内容
有鉴于此，有必要提供一种有利于线路设计的封装结构的制造方法。
还有必要提供一种封装结构。
一种封装结构的制造方法，其包括以下步骤：
提供一承载板，并在所述承载板的表面形成内层线路层，所述内层线路层包括至少一开口，所述承载板从所述开口露出；
对应所述开口在所述承载板上固定第一电子元件，其中，所述第一电子元件的电连接端朝向所述承载板；
在所述第一电子元件背离所述承载板的一侧固定第二电子元件，其中，所述第二电子元件的电连接端背向所述承载板；
提供第一层压板，并将第一层压板压合至所述承载板形成内层线路层的表面，所述第一层压板包括第一介质层及第一铜层，所述第一介质层覆盖所述内层线路层并填充所述开口，所述第一铜层设于所述第一介质层背离所述承载板的一侧；
在所述第一层压板上开设第一连通孔及第二连通孔，其中，所述第一连通孔对应所述第二电子元件的电连接端以露出所述第二电子元件的电连接端，所述第二连通孔对应所述内层线路层设置以露出所述内层线路层的部分区域；
在所述第一层压板背离所述承载板的一侧进行线路制作形成第一外层线路层，并对应所述第一连通孔形成第一导电结构电连接所述第一外层线路层及所述第二电子元件，对应所述第二连通孔形成第二导电结构电连接所述第一外层线路层及所述内层线路层；以及
移除所述承载板获得封装结构，其中，所述第一电子元件的电连接端露出。
进一步地，所述封装结构包括位于表面的连接垫，在步骤“移除所述承载板获得封装结构，其中，所述第一电子元件的电连接端露出”之后还包括步骤：
在所述封装结构的表面形成防焊层，且所述封装结构表面的连接垫及所述第一电子元件的电连接端从所述防焊层露出。
进一步地，在步骤“移除所述承载板获得封装结构，其中，所述第一电子元件的电连接端露出”之后还包括步骤：
将第三电子元件设置于移除所述承载板后形成的中间体上以封装所述第一电子元件及第二电子元件，且所述第三电子元件通过焊球与所述第一电子元件的电连接端及所述内层线路层的连接垫电连接。
进一步地，所述第一电子元件通过第一胶层固定于所述承载板，所述第二电子元件通过第二胶层固定于所述第一电子元件背离所述承载板的一侧。
进一步地，所述承载板包括基底结构及形成于所述基底结构相对两侧的铜箔层，所述内层线路层设置于所述铜箔层背离所述基底结构的表面。
进一步地，步骤“移除所述承载板获得封装结构，其中，所述第一电子元件的电连接端露出”具体包括：
分离所述基底结构与所述铜箔层，获得所述基底结构及带有所述铜箔层的中间体；
快速蚀刻去除所述中间体上的所述铜箔层，并露出所述第一电子元件的电连接端，从而获封装结构。
进一步地，在步骤“移除所述承载板获得封装结构，其中，所述第一电子元件的电连接端露出”之前还包括步骤：
在所述第一外层线路背离所述承载板的一侧压合第二层压板，所述第二层压板覆盖所述第一外层线路层并填满所述第一外层线路层的空隙；
在所述第二层压板背离所述承载板的一侧进行线路制作形成第二外层线路层，且所述第二外层线路层与所述第一外层线路层电连接。
一种封装结构，包括内层线路层、第一介质层、第一外层线路层及电子组件，所述第一介质层包括第一表面及与所述第一表面相对第二表面，所述内层线路层及所述电子组件从所述第一表面嵌入所述第一介质层，并且所述内层线路层与所述第一表面平齐，所述第一外层线路层设置于所述第二表面，所述电子组件包括第一电子元件及第二电子元件，所述第二电子元件靠近所述第二表面设置，且所述第二电子元件的电连接端朝向所述第二表面，所述第一电子元件设置于所述第二电子元件背离第二表面的一侧，并且所述第一电子元件从所述第一表面露出，所述第一外层线路分别与所述第二电子元件的电连接端及所述内层线路层电连接。
进一步地，所述第一介质层还开设有第一连通孔及第二连通孔，所述第一连通孔连通所述第一外层线路层及第二电子元件的电连接端，所述第二连通孔连通所述第一外层线路层及所述内层线路层；所述封装结构还包括对应所述第一连通孔设置的第一导电结构以及对应所述第二连通孔设置的第二导电结构，所述第一导电结构电连接所述第一外层线路层及第二电子元件的电连接端，所述第二导电结构电连接所述第一外层线路层及所述内层线路层。
进一步地，所述封装结构还包括第三电子元件，所述第三电子元件设置于所述内层线路层背离所述第一外层线路层的一侧以封装所述第一电子元件及第二电子元件，其中，所述第三电子元件与所述第一电子元件的电连接端及所述内层线路层的连接垫电连接。
本发明的封装结构的制造方法，在第一介质层中内嵌层叠设置的第一电子元件及第二电子元件，从而增加了内埋元件的数量。所述第二电子元件的电连接端与所述第一外层线路层电连接，且所述第一外层线路层与所述内层线路层电连接，同时，所述第一电子元件的电连接端从所述第一介质层中裸露，从而增加所述封装结构整体的信号输入/输出通道(I/O数)。另外，本发明的封装结构的制造方法工艺简单便于生产。
附图说明
图1-图15是本发明提供的一实施方式的封装结构的制造方法。
图16是在本发明提供的一实施方式的封装结构的截面示意图。
主要元件符号说明
Figure BDA0002498847850000041
Figure BDA0002498847850000051
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。
下面结合附图，对本发明的一些实施方式作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
请结合参阅图1～图15，本发明一较佳实施方式的封装结构的制造方法，其包括以下步骤：
步骤S1，请参见图1，提供一承载板10，并在所述承载板10上形成内层线路层20。其中，所述内层线路层20包括至少一开口201以露出所述承载板10，所述内层线路层20还包括至少一连接垫(图未标)。
在本实施方式中，所述承载板10的相对两侧分别形成一内层线路层20，且每一内层线路层20包括至少一开口201以露出所述承载板10。
步骤S2，请参阅图2，对应所述开口201在所述承载板10上设置第一胶层31。
步骤S3，请参阅图3，在所述第一胶层31背离所述承载板10的一侧设置第一电子元件41。其中，所述第一电子元件41的电连接端朝向所述承载板10。
具体的，所述第一电子元件41朝向所述承载板10的一侧设有至少一连接垫411作为电连接端。
在其他实施方式中，可先在第一电子元件41上设置第一胶层31，再将所述第一电子元件41通过所述第一胶层31对应所述开口201粘接于所述承载板10，以替换上述步骤S2及步骤S3。在其他实施方式中，还可通过其他方式将所述第一电子元件41固定于所述承载板10上。
步骤S4，请参阅图4，在所述第一电子元件41背离所述承载板10的一侧设置第二胶层33。
步骤S5，请参阅图5，在所述第二胶层33背离所述承载板10的一侧设置第二电子元件43。其中，所述第二电子元件43的电连接端背向所述承载板10。
具体的，所述第二电子元件43背向所述承载板10的一侧设有至少一连接垫431作为电连接端。
在其他实施方式中，可先在第二电子元件43上设置第二胶层33，再将所述第二电子元件43通过所述第二胶层33粘接于所述第一电子元件41，以替换上述步骤S2及步骤S3。在其他实施方式中，还可通过其他方式将所述第二电子元件43固定于所述承载板10上。
步骤S6，请参阅图6，提供第一层压板50，并将第一层压板50压合至所述承载板10，使得所述内层线路层20、所述第一电子元件41及所述第二电子元件43夹设于所述第一层压板50与所述承载板10之间。
本实施方式中，所述第一层压板50可包括第一介质层51及设置于所述第一介质层51一侧的第一铜层53。所述第一介质层51背离所述第一铜层53的一侧与所述承载板10结合覆盖所述内层线路层20，且在压合时所述第一介质层51流动性增加并填充所述开口201，从而使得所述内层线路层20、所述第一电子元件41及所述第二电子元件43嵌设于所述第一介质层51中。
所述第一介质层51可选自但不仅限于聚丙烯、环氧树脂、聚氨酯、酚醛树脂、脲醛树脂、三聚氰胺-甲醛树脂、不饱和树脂、聚酰亚胺等中的至少一种。
本实施方式中，所述第一层压板50的数量为两个，分别压合至所述承载板10设有所述内层线路层20的两侧。
步骤S7，请参阅图7，在所述第一层压板50上开设第一连通孔501及第二连通孔503，所述第一连通孔501对应所述第二电子元件43的电连接端设置以露出所述第二电子元件43的电连接端，所述第二连通孔503对应所述内层线路层20设置以露出所述内层线路层20的部分区域。
步骤S8，请参阅图8，在所述第一层压板50背离所述承载板10的一侧进行线路制作形成第一外层线路层60，并对应所述第一连通孔501形成第一导电结构601，对应所述第二连通孔503形成第二导电结构603。
所述第一导电结构601电连接所述第一外层线路层60及所述第二电子元件43；所述第二导电结构603电连接所述第一外层线路层60及内层线路层20。
所述第一外层线路层60可包括至少一连接垫(图未标)。
步骤S9，请参阅图9，在所述第一外层线路层60背离所述承载板10的一侧压合第二层压板55，所述第二层压板55覆盖所述第一外层线路层60并填满所述第一外层线路层60的空隙。
本实施方式中，所述第二层压板55可包括第二介质层56及设置于所述第二介质层56一侧的第二铜层58。所述第二介质层56背离所述第二铜层58的一侧与所述第一外层线路层60结合，且在压合时所述第二介质层56流动性增加并填充所述第一外层线路层60的空隙。
所述第二介质层56可选自但不仅限于聚丙烯、环氧树脂、聚氨酯、酚醛树脂、脲醛树脂、三聚氰胺-甲醛树脂、不饱和树脂、聚酰亚胺等中的至少一种。
本实施方式中，所述第二层压板55的数量为两个，分别压合至两第一外层线路层60相背的两侧。
步骤S10，请参阅图10，在所述第二层压板55背离所述第一外层线路层60的一侧进行线路制作形成第二外层线路层65，且所述第二外层线路层65与所述第一外层线路层60电连接。
所述第二外层线路层65包括至少一连接垫。
步骤S11，请参阅图11，移除所述承载板10并去除所述第一胶层31以露出所述第一电子元件41的电连接端，从而获得封装结构100。
本实施方式中，所述封装结构的制造方法还可继续包括步骤S12及步骤S13，具体如下：
步骤S12，请参阅图12，在所述封装结构100的表面形成防焊层70，且所述封装结构100表面的连接垫(图未标)及所述第一电子元件41的电连接端从所述防焊层70露出。
本实施方式中，具体的，在所述内层线路层20背离所述第二外层线路层65的一侧及所述第二外层线路层65背离所述内层线路层20的一侧形成防焊层70，且所述内层线路层20中的连接垫(图未标)、所述第二外层线路层65中的连接垫(图未标)及所述第一电子元件41的电连接端从所述防焊层70露出。
步骤S13，请参阅图13，将第三电子元件80设置于所述封装结构100上以封装所述第一电子元件41及第二电子元件43，所述第三电子元件80通过焊球(图未标)与所述第一电子元件41的电连接端及所述内层线路层20的连接垫电连接。
本实施方式中，所述第三电子元件80可为存储器。
在本实施方式中，所述步骤S13还包括对应所述外层线路结构60从所述防焊层70露出的连接垫形成焊球(图未标)。
本实施方式中，请参阅图1，步骤S1中所述承载板10可包括基底结构11及形成于所述基底结构11相对两侧的铜箔层13，所述内层线路层20设置于所述铜箔层13背离所述基底结构11的表面。
在本实施方式中，步骤S11中“移除所述承载板10并去除所述第一胶层31以露出所述第一电子元件41的电连接端，从而获得封装结构100”具体包括：
请参阅图14，分离所述基底结构11与所述铜箔层13，获得所述基底结构11及两个带有铜箔层13的中间体200；
请参阅图15，快速蚀刻去除所述中间体200上的所述铜箔层13；以及
请参阅图11，去除第一胶层31以露出所述第一电子元件41的电连接端，从而获得封装结构100。
在其他实施方式中，在步骤S10之后及步骤S11之前，还可继续增层形成其他外层线路层。
在其他实施方式中，还可省略步骤S9及步骤S10。
在其他实施方式中，还可省略步骤S12。
在其他实施方式中，还可省略步骤S13。在一些实施方式中，所述存储器还可替换为其他电子元件。
本实施方式中，所述内层线路层20的形成方法可包括如下步骤：
第一步，在所述承载板10的相对两侧分别压合一感光膜(图未示)。
第二步，对所述感光膜进行曝光显影形成图案(图未示)。
第三步，对应所述图案进行镀铜形成所述第一线路层20。
第四步，去除曝光显影后的感光膜。
请参阅图16，本发明还提供一实施方式的封装结构100，其包括内层线路层20、第一介质层51、第一外层线路层60及电子组件40。所述第一介质层51包括第一表面511及与所述第一表面511相对第二表面513。所述内层线路层20及所述电子组件40从所述第一表面511嵌入所述第一介质层51且所述内层线路层20与所述第一表面511平齐。所述第一外层线路层60设置于所述第二表面513。所述电子组件40包括第一电子元件41及第二电子元件43。所述第二电子元件43靠近所述第二表面513设置，且所述第二电子元件43的电连接端朝向所述第二表面513。所述第一电子元件41设置于所述第二电子元件43背离第二表面513的一侧，并且所述第一电子元件41从所述第一表面511露出。所述第一外层线路层60分别与所述第二电子元件43的电连接端及所述内层线路层20电连接。
本实施方式中，所述电子组件40完全嵌入所述第一介质层51，且所述电子组件40背离所述第一外层线路层60的表面低于所述第一表面511。
本实施方式中，所述第一介质层51还开设有第一连通孔501及第二连通孔503。所述第一连通孔501连通所述第一外层线路层60及第二电子元件43的电连接端；所述第二连通孔503连通所述第一外层线路层60及所述内层线路层20。所述封装结构100还包括对应所述第一连通孔501设置的第一导电结构601以及对应所述第二连通孔503设置的第二导电结构603。所述第一导电结构601电连接所述第一外层线路层60及第二电子元件43的电连接端；所述第二导电结构603电连接所述第一外层线路层60及所述内层线路层20。
所述封装结构100还可包括第二介质层56及第二外层线路层65。所述第二介质层56覆盖所述第一外层线路层60背离所述内层线路层20的一侧，并填充所述第一外层线路层60的空隙。所述第二外层线路层65设置于所述第二介质层56背离所述内层线路层20的一侧。所述第二外层线路层65与所述第一外层线路层60电连接。
在其他实施方式中，所述封装结构100还可包括设置于所述第二外层线路层65背离所述内层线路层20的一侧的其他介质层及外层线路层。
所述第一介质层51及所述第二介质层56可分别选自但不仅限于聚丙烯、环氧树脂、聚氨酯、酚醛树脂、脲醛树脂、三聚氰胺-甲醛树脂、不饱和树脂、聚酰亚胺等中的至少一种。
所述封装结构100还可包括防焊层70。本实施方式中，所述防焊层70设置于所述内层线路层20背离所述第一外层线路层60的一侧及所述第二外层线路层65背离所述第一外层线路层60的一侧。所述内层线路层20中的连接垫、所述第二外层线路层65的连接垫及所述第一电子元件41的电连接端从所述防焊层70露出。
本实施方式中，所述第二外层线路层60从所述防焊层70露出的连接垫上还可设置焊球。
所述封装结构100还可包括第三电子元件80，所述第三电子元件80设置于所述内层线路层20背离所述第一外层线路层60的一侧以封装所述第一电子元件41及第二电子元件43。其中，所述第三电子元件80与所述第一电子元件41的电连接端及所述内层线路层20的连接垫电连接。
本实施方式中，所述第三电子元件80通过焊球与所述第一电子元件41的电连接端及所述内层线路层20的连接垫电连接。
本实施方式中，所述第一电子元件41与所述第二电子元件43之间通过胶层进行粘接。
本发明的封装结构的制造方法，在第一介质层51中内嵌层叠设置的第一电子元件41及第二电子元件43，从而增加了内埋元件的数量。所述第二电子元件43的电连接端与所述第一外层线路层60电连接，且所述第一外层线路层60与所述内层线路层20电连接，同时，所述第一电子元件41的电连接端从所述第一介质层51中裸露，从而增加所述封装结构整体的信号输入/输出通道(I/O数)。另外，本发明的封装结构的制造方法工艺简单便于生产。
以上所述，仅是本发明的较佳实施方式而已，并非对本发明任何形式上的限制，虽然本发明已是较佳实施方式揭露如上，并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施方式，但凡是未脱离本发明技术方案内容，依据本发明的技术实质对以上实施方式所做的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (10)

1.一种封装结构的制造方法，其包括以下步骤：
提供一承载板，并在所述承载板的表面形成内层线路层，所述内层线路层包括至少一开口，所述承载板从所述开口露出；
对应所述开口在所述承载板上固定第一电子元件，其中，所述第一电子元件的电连接端朝向所述承载板；
在所述第一电子元件背离所述承载板的一侧固定第二电子元件，其中，所述第二电子元件的电连接端背向所述承载板；
提供第一层压板，并将第一层压板压合至所述承载板形成内层线路层的表面，所述第一层压板包括第一介质层及第一铜层，所述第一介质层覆盖所述内层线路层并填充所述开口，所述第一铜层设于所述第一介质层背离所述承载板的一侧；
在所述第一层压板上开设第一连通孔及第二连通孔，其中，所述第一连通孔对应所述第二电子元件的电连接端以露出所述第二电子元件的电连接端，所述第二连通孔对应所述内层线路层设置以露出所述内层线路层的部分区域；
在所述第一层压板背离所述承载板的一侧进行线路制作形成第一外层线路层，并对应所述第一连通孔形成第一导电结构电连接所述第一外层线路层及所述第二电子元件，对应所述第二连通孔形成第二导电结构电连接所述第一外层线路层及所述内层线路层；以及
移除所述承载板获得封装结构，其中，所述第一电子元件的电连接端露出。
2.如权利要求1所述的封装结构的制造方法，其特征在于，所述封装结构包括位于表面的连接垫，在步骤“移除所述承载板获得封装结构，其中，所述第一电子元件的电连接端露出”之后还包括步骤：在所述封装结构的表面形成防焊层，且所述封装结构表面的连接垫及所述第一电子元件的电连接端从所述防焊层露出。
3.如权利要求1所述的封装结构的制造方法，其特征在于，在步骤“移除所述承载板获得封装结构，其中，所述第一电子元件的电连接端露出”之后还包括步骤：将第三电子元件设置于移除所述承载板后形成的中间体上以封装所述第一电子元件及第二电子元件，且所述第三电子元件通过焊球与所述第一电子元件的电连接端及所述内层线路层的连接垫电连接。
4.如权利要求1所述的封装结构的制造方法，其特征在于，所述第一电子元件通过第一胶层固定于所述承载板，所述第二电子元件通过第二胶层固定于所述第一电子元件背离所述承载板的一侧。
5.如权利要求1所述的封装结构的制造方法，其特征在于，所述承载板包括基底结构及形成于所述基底结构相对两侧的铜箔层，所述内层线路层设置于所述铜箔层背离所述基底结构的表面。
6.如权利要求5所述的封装结构的制造方法，其特征在于，步骤“移除所述承载板获得封装结构，其中，所述第一电子元件的电连接端露出”具体包括：
分离所述基底结构与所述铜箔层，获得所述基底结构及带有所述铜箔层的中间体；
快速蚀刻去除所述中间体上的所述铜箔层，并露出所述第一电子元件的电连接端，从而获封装结构。
7.如权利要求1所述的封装结构的制造方法，其特征在于，在步骤“移除所述承载板获得封装结构，其中，所述第一电子元件的电连接端露出”之前还包括步骤：
在所述第一外层线路背离所述承载板的一侧压合第二层压板，所述第二层压板覆盖所述第一外层线路层并填满所述第一外层线路层的空隙；
在所述第二层压板背离所述承载板的一侧进行线路制作形成第二外层线路层，且所述第二外层线路层与所述第一外层线路层电连接。
8.一种封装结构，包括内层线路层、第一介质层、第一外层线路层及电子组件，所述第一介质层包括第一表面及与所述第一表面相对第二表面，其特征在于，所述内层线路层及所述电子组件从所述第一表面嵌入所述第一介质层并且所述内层线路层与所述第一表面平齐，所述第一外层线路层设置于所述第二表面，所述电子组件包括第一电子元件及第二电子元件，所述第二电子元件靠近所述第二表面设置，且所述第二电子元件的电连接端朝向所述第二表面，所述第一电子元件设置于所述第二电子元件背离第二表面的一侧，并且所述第一电子元件的电连接端从所述第一表面露出，所述第一外层线路分别与所述第二电子元件的电连接端及所述内层线路层电连接。
9.如权利要求8所述的封装结构，其特征在于，所述第一介质层还开设有第一连通孔及第二连通孔，所述第一连通孔连通所述第一外层线路层及第二电子元件的电连接端，所述第二连通孔连通所述第一外层线路层及所述内层线路层；所述封装结构还包括对应所述第一连通孔设置的第一导电结构以及对应所述第二连通孔设置的第二导电结构，所述第一导电结构电连接所述第一外层线路层及第二电子元件的电连接端，所述第二导电结构电连接所述第一外层线路层及所述内层线路层。
10.如权利要求8所述的封装结构，其特征在于，所述封装结构还包括第三电子元件，所述第三电子元件设置于所述内层线路层背离所述第一外层线路层的一侧以封装所述第一电子元件及第二电子元件，其中，所述第三电子元件与所述第一电子元件的电连接端及所述内层线路层的连接垫电连接。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103270588A (zh) * 2010-12-22 2013-08-28 英特尔公司 具有嵌入式层叠硅通孔管芯的衬底
CN105590914A (zh) * 2014-10-24 2016-05-18 宏启胜精密电子(秦皇岛)有限公司 电子元件封装结构及制作方法
CN106672888A (zh) * 2015-11-11 2017-05-17 飞思卡尔半导体公司 封装集成电路管芯的方法和器件

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
FI20041525A (fi) * 2004-11-26 2006-03-17 Imbera Electronics Oy Elektroniikkamoduuli ja menetelmä sen valmistamiseksi
CN101364583A (zh) * 2007-08-10 2009-02-11 全懋精密科技股份有限公司 电容元件埋入半导体封装基板结构及其制作方法
TWI348213B (en) * 2007-08-15 2011-09-01 Packaging substrate structure with capacitor embedded therein and method for fabricating the same
TWI434382B (zh) * 2011-07-06 2014-04-11 Unimicron Technology Corp 嵌埋有電子元件之封裝結構及其製法
CN103681559B (zh) * 2012-09-25 2016-11-09 宏启胜精密电子(秦皇岛)有限公司 芯片封装基板和结构及其制作方法
US20160005675A1 (en) * 2014-07-07 2016-01-07 Infineon Technologies Ag Double sided cooling chip package and method of manufacturing the same
US9385041B2 (en) * 2014-08-26 2016-07-05 Semiconductor Components Industries, Llc Method for insulating singulated electronic die
CN105655258B (zh) * 2014-11-14 2018-07-13 欣兴电子股份有限公司 嵌入式元件封装结构的制作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103270588A (zh) * 2010-12-22 2013-08-28 英特尔公司 具有嵌入式层叠硅通孔管芯的衬底
CN105590914A (zh) * 2014-10-24 2016-05-18 宏启胜精密电子(秦皇岛)有限公司 电子元件封装结构及制作方法
CN106672888A (zh) * 2015-11-11 2017-05-17 飞思卡尔半导体公司 封装集成电路管芯的方法和器件

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