CN102656686B - 凹陷型嵌入式管芯无核封装 - Google Patents

凹陷型嵌入式管芯无核封装 Download PDF

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CN102656686B
CN102656686B CN201080059434.9A CN201080059434A CN102656686B CN 102656686 B CN102656686 B CN 102656686B CN 201080059434 A CN201080059434 A CN 201080059434A CN 102656686 B CN102656686 B CN 102656686B
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tube core
pop
island
coreless substrate
microelectronic
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CN102656686A (zh
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J.古泽克
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Intel Corp
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Intel Corp
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Abstract

描述形成微电子封装结构的方法以及由此形成的相关联的结构。那些方法可包括：在镀覆材料中形成空腔以容纳管芯；在空腔中附着管芯；相邻于管芯形成电介质材料；在与管芯相邻的电介质材料中形成通路；在通路中形成PoP岛；在通路中形成互连；然后去除镀覆材料以暴露PoP岛和管芯，其中管芯设置在PoP岛上。

Description

凹陷型嵌入式管芯无核封装
背景技术
随着对于更高处理器性能的半导体技术的发展，封装体系结构的发展可包括封装上封装（PoP）体系结构和其它这样的组合件。随着封装结构的设计变得更加复杂，通常会导致组装费用的增加。因此，需要显著降低高级封装结构的封装和组装成本。
附图说明
尽管说明书的随附权利要求特别指出并且明确要求本发明的某些实施例的权利，但是通过结合附图阅读以下对本发明的描述，可更加容易地确定本发明的优点，附图中：
图1a-1m表示根据本发明一个实施例用于形成结构的方法。
图2表示根据本发明一个实施例的系统。
具体实施方式
在以下详细描述中，参考附图，附图通过图示示出可在其中实践本发明的特定实施例。将对这些实施例进行足够详细地描述以使得本领域技术人员能够实践本发明。将了解，尽管本发明的各种实施例有所不同，但它们不一定相互排斥。例如，在不偏离本发明的精神和范围的情况下，本文中结合一个实施例描述的特定特征、结构或特性可在其它实施例内实现。另外，将了解，在不偏离本发明的精神和范围的情况下，可修改每个公开实施例中的各个元件的位置或布置。因此，不应将以下详细描述视为是限制意义，本发明的范围只由合适解释的随附权利要求以及赋予这些权利要求的全部范围内的等效物来限定。附图中，在所有几个视图中，类似的数字表示相同或类似的功能性。
描述形成与利用诸如封装结构的微电子结构的方法和相关联的结构。那些方法可包括：在镀覆材料中形成空腔以容纳管芯；在空腔中附着管芯；相邻于管芯形成电介质材料；在与管芯相邻的电介质材料中形成通路；在通路中形成PoP岛；在通路中形成互连；然后去除镀覆材料以暴露PoP岛和管芯。本发明的方法使得能够制作封装上封装体系结构，例如PoP组合件，其包括部分凹陷和/或完全嵌入的管芯，或任何其它类型的球栅阵列（BGA）封装。
图1a-1m示出用于形成诸如封装结构的微电子结构的方法的实施例。图1a示出材料100。在一个实施例中，材料100可包括镀覆材料，例如但不限于铜箔镀覆材料。在一些实施例中，取决于特定应用，可使用任何合适的镀覆材料。在图1b中，可在材料100中形成空腔102。在一些实施例中，可利用诸如本领域中已知的任何合适的蚀刻工艺来形成空腔102。在一个实施例中，可形成空腔102以使得空腔102可容纳管芯，例如微电子管芯。空腔102可包括底部部分101、成角度部分103和顶部部分105。在一个实施例中，底部和顶部部分可由阻挡层隔开以有助于形成空腔结构，尤其是对于蚀刻工艺。在一个实施例（未示出）中，可在表面101上形成PoP岛结构（本文将进一步描述）。
在一个实施例中，可将管芯104附着在空腔102内（图1c）。在一个实施例中，管芯104可包括薄管芯104，且其厚度可小于约150微米。在一个实施例中，管芯104可附着到空腔101的顶部部分105。在一个实施例中，管芯104可包括至少一个侧壁106、顶侧107和底/有源侧108。在一些情况中，可利用粘性膜和/或附着工艺来将管芯104附着到镀覆材料100的空腔102中。在一个实施例中，可利用粘性膜（未示出）作为最终封装的永久部分，以例如保护管芯背侧，提供用于做标记的表面，和/或应对可能在管芯104内出现的任何翘曲。可在镀覆材料100上相邻于镀覆材料100的空腔102中的管芯104形成电介质材料110（图1d）。在一个实施例中，可通过例如层压工艺来形成电介质材料110。电介质材料110可形成在空腔102的底部部分101、空腔102的成角度部分103和镀覆材料100的空腔102的顶部部分105的围绕管芯104的部分上。可在电介质材料110的与管芯104相邻的区域114中形成通路112（图1e）。在一个实施例中，可在通路112内形成封装上封装（PoP）岛区113，其中可去除镀覆材料100的一部分以形成PoP岛区113。在一个实施例中，可利用任何合适的蚀刻工艺来去除镀覆材料100和电介质材料110。
在一个实施例中，可在PoP岛区113中形成PoP岛结构116（图1f）。可通过利用例如电镀工艺来在PoP岛区113中形成PoP岛结构116，但是也可利用任何合适的工艺来形成PoP岛结构116。在一个实施例中，可利用PoP岛区113内的镀覆材料100来作为用于形成PoP岛结构116的镀覆总线。在一个实施例中，镀覆材料100可包括可用作镀覆总线的铜箔。在一些情况下，根据特定应用，镀覆冶金可包括金、镍、金/镍、金/镍/钯及类似的合适材料。在一个实施例中，可在PoP岛区113上镀覆丝焊焊盘，以例如允许在CPU管芯背侧上进行混合技术堆叠。
在一个实施例中，可在管芯区119中形成通路118，其中可以在管芯104的有源侧108上暴露诸如铜管芯焊盘的管芯焊盘（图1g）。可利用金属材料来镀覆与PoP岛结构116（电介质区域114中的PoP岛结构116）相邻的通路112以及管芯区119中的通路118（图1h）以形成PoP岛结构116互连结构117并形成管芯焊盘互连结构120。在一个实施例中，PoP岛互连结构117可电连接至PoP岛结构116，并且管芯焊盘互连结构120可电连接至管芯104的有源侧108上的管芯焊盘。
在一个实施例中，可利用半加成工艺（SAP）来形成管芯焊盘互连结构120和PoP互连结构118。在一些实施例中，可在相同工序中形成管芯焊盘互连结构120和PoP互连结构118，或者在其它实施例中，可在单独的形成步骤中形成管芯焊盘互连结构120和PoP互连结构118。可在管芯焊盘互连结构120和PoP互连结构118上形成第二电介质层110’（图1i）。可在第二电介质层110’中形成第一金属化层121。
接着，可利用例如标准衬底SAP积层处理来形成随后层，其中更多的电介质层120’’和金属化层121’可形成在彼此之上以通过利用积层工艺来形成无核衬底125（图1j）。然后，可从无核衬底125的管芯104和PoP岛结构116中去除镀覆材料100，以暴露PoP岛和管芯，从而形成无核封装结构126（图1k）。无核封装结构126可包括围绕管芯104的电介质材料110的填角结构(fillet structure)127，其中电介质材料110可围绕管芯104的侧壁106和底部108，但是其中在管芯104的顶侧107上则不存在电介质材料110。
填角结构127可包括相对于无核衬底125的电介质110的平面顶部部分111成角度/凸起的电介质110部分。该填角结构127的几何形状可优化成提供管芯/封装的最大可靠性，其中填角结构127的角度128可改变以优化可靠性。在一个实施例中，填角结构的角度可包括约70度或更小，但是也可根据应用而改变。
在一个实施例中，无核封装结构126可包括至少部分嵌入在无核衬底125中的管芯104。在其它实施例中，无核封装结构126可包括基本上完全嵌入在无核衬底125中的管芯104。在一些实施例中，管芯104的顶侧107可与电介质110的顶部部分111基本上共平面。在另一个实施例中，在管芯104的顶侧107与PoP岛116的顶侧131之间可存在距离129。
无核封装结构126可包括封装互连结构区122，其中可附着诸如球栅阵列（BGA）球的互连结构124（图1l）。无核封装结构126的PoP岛结构116可包括设置在无核衬底125的顶部上的凸起的电镀岛116，从而使得能够在无核封装结构126的顶部上附着另一个封装（例如，封装上封装结构）。
图1m描绘PoP结构130，其中第二封装132通过附着到PoP岛结构116而连接至无核封装结构126。在一个实施例中，第二封装132可包括位于无核封装结构126的管芯104的正上方的管芯104’。第二封装132的互连球124’可附着到无核封装结构126的PoP岛结构116。
图2是示出能够利用用于制造诸如图1l的无核封装结构126的微电子结构的方法进行操作的实例性系统200的图。将了解，本实施例只不过是可在其中使用本发明的无核封装结构的许多可能系统之一。
图2示出根据本发明一个实施例的计算机系统。系统200包括处理器210、存储器装置220、存储器控制器230、图形控制器240、输入和输出（I/O）控制器250、显示器252、键盘254、定位装置256、外围装置258和总线260。处理器210可以是通用处理器或专用集成电路（ASIC）。I/O控制器250可包括用于进行有线或无线通信的通信模块。存储器装置220可以是动态随机存取存储器（DRAM）装置、静态随机存取存储器（SRAM）装置、闪速存储器装置或这些存储器装置的组合。因此，在一些实施例中，系统200中的存储器装置220不一定要包括DRAM装置。
系统200中示出的一个或多个组件可包含在诸如图11的无核封装结构126的一个或多个集成电路封装中。例如，处理器210、或存储器装置220、或I/O控制器250的至少一部分、或这些组件的组合可包含在包括图1a-1m中所描述的结构的至少一个实施例的集成电路封装中。
系统200可包括计算机（例如，桌面型、膝上型、手持式、服务器、Web器具、路由器等）、无线通信装置（例如，蜂窝电话、无绳电话、寻呼机、个人数字助理等）、计算机有关的外围设备（例如，打印机、扫描仪、监视器等）、娱乐装置（例如，电视、无线电装置、立体声系统、磁带和光盘播放器、盒式磁带录像机、摄像机、数码相机、MP3（移动图片专家组，音频层3）播放器、视频游戏机、手表等）等。
本发明的益处实现了可以用当前封装体系结构的大约一半的成本来满足未来移动/手持式芯片上系统（SoC）处理器的设计要求的新的封装体系结构。实施例提供将管芯嵌入在衬底中的方法，由此使得能够除去许多组装工序。实施例实现了薄管芯组装、PoP兼容性、衬底设计规则可伸缩性、封装厚度减小和封装/组装成本降低。另外，衬底不再局限于条带制作能力，由此实现了全面板处理，这也降低了成本。
尽管以上描述指定了可在本发明的方法中使用的某些步骤和材料，但本领域技术人员将明白，可进行许多修改和替换。因此，所有这些修改、改变、替换和增加要视为是落在由随附权利要求限定的本发明的精神和范围内。另外，应明白，诸如封装结构的各种微电子结构在本领域中是众所周知的。因此，本文提供的图只示出属于本发明的实践的实例性微电子装置的部分。因而，本发明不局限于本文描述的结构。

Claims (11)

1.一种微电子结构，包括：
设置在无核衬底中的部分嵌入的管芯，其中所述部分嵌入的管芯包括顶侧和底侧/有源侧，其中所述无核衬底包括电介质材料，所述电介质材料具有平面顶部部分并且具有相对于所述平面顶部部分凸起的填角结构，其中所述填角结构具有从所述平面顶部部分延伸到与所述部分嵌入的管芯的顶侧相邻的位置而没有延伸到所述部分嵌入的管芯的顶侧之上的倾斜部分，并且其中所述填角结构与所述部分嵌入的管芯的侧壁相邻；以及
在所述无核衬底的所述平面顶部部分上与所述部分嵌入的管芯相邻的凸起的PoP岛，
其中所述PoP岛能够接纳第二衬底。
2.如权利要求1所述的微电子结构，还包括设置在所述部分嵌入的管芯的顶表面上的粘性膜，并且其中所述无核衬底包括PoP封装结构的一部分。
3.如权利要求1所述的微电子结构，其中所述无核衬底包括PoP封装结构的一部分，并且其中第二封装的互连结构设置在所述无核衬底的所述PoP岛上。
4.如权利要求3所述的微电子结构，其中所述第二封装的管芯位于所述无核衬底中设置的所述部分嵌入的管芯的正上方。
5.如权利要求1所述的微电子结构，其中在所述管芯的顶侧与所述PoP岛的顶侧之间存在一定的距离。
6.一种微电子结构，包括：
设置在无核衬底中的管芯，其中所述管芯的至少一部分嵌入在所述无核衬底中，并且其中所述管芯包括顶侧和底侧/有源侧，其中所述无核衬底包括电介质材料，所述电介质材料具有平面顶部部分并且具有相对于所述平面顶部部分凸起的填角结构，其中所述填角结构具有从所述平面顶部部分延伸到与所述管芯的顶侧相邻的位置而没有延伸到所述管芯的顶侧之上的倾斜部分，并且其中所述填角结构与所述管芯的侧壁相邻；
所述无核衬底的所述平面顶部部分上与所述管芯相邻的凸起的PoP岛，其中所述PoP岛和所述管芯能够接纳第二衬底；
与所述管芯的所述底侧/有源侧相邻的电介质膜，其中管芯互连结构设置在所述电介质膜中并连接至所述管芯的所述底侧/有源侧的焊盘；
连接至所述PoP岛的PoP互连结构；以及
设置在所述PoP互连结构和所述管芯互连结构上的第一金属层。
7.如权利要求6所述的微电子结构，其中所述PoP岛包括镀覆金属。
8.如权利要求6所述的微电子结构，其中所述无核衬底包括无核封装结构的一部分，其中第二封装连接至所述无核封装结构。
9.如权利要求8所述的微电子结构，其中所述第二封装的互连结构连接至所述无核封装结构的所述PoP岛。
10.如权利要求6所述的微电子结构，其中所述管芯的厚度小于150微米。
11.如权利要求6所述的微电子结构，还包括系统，所述系统包括：
在通信上耦合到所述微电子结构的总线；以及
在通信上耦合到所述总线的DRAM。
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