JP2013514664A - リセス埋込ダイを備えるコアレスパッケージ - Google Patents

リセス埋込ダイを備えるコアレスパッケージ Download PDF

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JP2013514664A
JP2013514664A JP2012544605A JP2012544605A JP2013514664A JP 2013514664 A JP2013514664 A JP 2013514664A JP 2012544605 A JP2012544605 A JP 2012544605A JP 2012544605 A JP2012544605 A JP 2012544605A JP 2013514664 A JP2013514664 A JP 2013514664A
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die
pop
forming
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package
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JP5442875B2 (ja
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グゼック，ジョン
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インテル コーポレイション
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Abstract

マイクロエレクトロニクスパッケージ構造を形成する方法、及びそれによって形成される構造物が提供される。該方法は、めっき部材に、ダイを保持するためのキャビティを形成し、前記キャビティ内にダイを取り付け、前記ダイに隣接して誘電体材料を形成し、前記ダイに隣接して前記誘電体材料内にビアを形成し、前記ビア内にＰｏＰランドを形成し、前記ビア内にインターコネクトを形成し、その後、前記めっき部材を除去して、前記ＰｏＰランドと前記ダイとを露出させることを有し、前記ダイは前記ＰｏＰランドより上に配置される。

Description

開示の実施形態は、マイクロエレクトロニクス構造及びその形成方法に関する。
より高いプロセッサ性能に向けて半導体技術が進展するにつれ、パッケージ技術は、パッケージ・オン・パッケージ（ＰｏＰ）アーキテクチャ及びその他のそのようなアセンブリを含むように進展し得る。パッケージ構造の設計がますます複雑になるにつれ、しばしば、組立コストの増大がもたらされる。故に、先端パッケージ構造のパッケージ・組立コストを有意に低減することが望まれる。
例えばパッケージ構造などのマイクロエレクトロニクス構造を形成する方法、それを使用する方法、及びそれらに関連する構造物が提供される。
一態様において、方法は、めっき部材に、ダイを保持するための孔を形成し、前記孔内にダイを取り付け、前記ダイに隣接して誘電体材料を形成し、前記ダイに隣接して前記誘電体材料内にビアを形成し、前記ビア内にＰｏＰランドを形成し、前記ビア内にインターコネクトを形成し、その後、前記めっき部材を除去して前記ＰｏＰランドと前記ダイとを露出させることを有し得る。本発明に係る方法は、部分的に凹所に置かれた（リセス化された）ダイ及び／又は完全に埋め込まれたダイを有する例えばＰｏＰアセンブリなどのパッケージ・オン・パッケージアーキテクチャ、又はその他の種類のボールグリッドアレイ（ＢＧＡ）パッケージの製造を可能にする。
本明細書は、本発明の特定の実施形態に注目し且つ区別して要求する請求項で締めくくられるが、以下の図を含む添付図面とともに以下の説明を読むことで、本発明の利点を更に容易に解明することができる。
本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係る構造を形成する方法を示す図である。 本発明の一実施形態に係るシステムを示す図である。
以下の詳細な説明においては、本発明が実施され得る特定の実施形態を例として示す添付図面を参照する。これらの実施形態は、当業者が本発明を実施することができるように十分に詳細に説明される。理解されるように、本発明の様々な実施形態は、相異なるものであったとしても、必ずしも相互に排他的なものではない。例えば、１つの実施形態に関連してここに記載される特定の機能、構造又は特徴は、本発明の精神及び範囲を逸脱することなく、その他の実施形態内で用いられ得る。また、理解されるように、開示の各実施形態内の個々の要素の位置又は構成は、本発明の精神及び範囲を逸脱することなく変更され得る。故に、以下の詳細な説明は限定的な意味で解されるべきものではなく、本発明の範囲は、適切に解釈される添付の請求項、並びに請求項の権利範囲に均等な範囲全体、によってのみ定められるものである。図面において、複数の図を通して、同一あるいは同様の機能は似通った参照符号によって参照することとする。
図１ａ−１ｍは、例えばパッケージ構造などのマイクロエレクトロニクス構造を形成する方法の実施形態を例示している。図１ａは部材１００を示している。一実施形態において、部材１００は、以下に限られないが例えば銅箔めっき部材などの、めっき部材を有し得る。一部の実施形態において、具体的な用途に応じて、好適な如何なるめっき部材が用いられてもよい。図１ｂにて、部材１００内にキャビティ（孔）１０２が形成され得る。キャビティ１０２は、一部の実施形態において、例えば技術的に既知のものなど、好適な如何なるエッチングプロセスを用いて形成されてもよい。一実施形態において、キャビティ１０２は、例えばマイクロエレクトロニクスダイなどのダイをキャビティ１０２が保持し得るように形成され得る。キャビティ１０２は、底面部１０１、傾斜部１０３、及び頂面部１０５を有し得る。一実施形態において、底面部及び頂面部は、キャビティ構造の形成において特にエッチングプロセスの助けとなるよう、バリア層によって隔てられてもよい。一実施形態（図示せず）において、表面１０１にＰｏＰランド構造（後述）を形成することができる。
一実施形態において、キャビティ１０２内にダイ１０４が取り付けられ得る（図１ｃ）。一実施形態において、ダイ１０４は薄いダイを有することができ、約１５０μｍ未満の厚さを有し得る。一実施形態において、ダイ１０４はキャビティ１０２の頂面部１０５に取り付けられ得る。一実施形態において、ダイ１０４は少なくとも１つの側壁１０６と、頂面１０７と、底面／アクティブ面１０８とを有し得る。一部の例において、めっき部材１００のキャビティ１０２内にダイ１０４を取り付けるために、接着膜及び／又は貼付プロセスが用いられ得る。一実施形態において、接着膜（図示せず）は、最終的なパッケージの常設部分として使用され、例えば、ダイの裏面を保護し、マーキング用の表面を提供し、且つ／或いはダイ１０４に生じ得る反りを制御することができる。誘電体材料１１０が、めっき部材１００のキャビティ１０２内にあるダイ１０４に隣接して、めっき部材１００上に形成され得る（図１ｄ）。一実施形態において、誘電体材料１１０は例えば、ラミネートプロセスによって形成され得る。誘電体材料１１０は、キャビティ１０２の底面部１０１上と、キャビティ１０２の傾斜部１０３上と、めっき部材１００のキャビティ１０２の頂面部１０５の、ダイ１０４を取り囲む部分上とに形成され得る。ダイ１０４に隣接する誘電体材料１１０の領域１１４にビア１１２が形成され得る（図１ｅ）。一実施形態において、ビア１１２内にパッケージ・オン・パッケージ（ＰｏＰ）ランド領域１１３が形成され得る。このとき、めっき部材１００の一部が除去されてＰｏＰランド領域１１３が形成される。一実施形態において、めっき部材１００及び誘電体材料１１０は、何らかの好適なエッチングプロセスを用いて除去され得る。
一実施形態において、ＰｏＰランド領域１１３にＰｏＰランド構造１１６が形成され得る（図１ｆ）。ＰｏＰランド構造１１６は、例えば、電解めっきプロセスを用いることによってＰｏＰランド領域１１３に形成され得るが、好適な如何なるプロセスを用いてＰｏＰランド構造１１６を形成してもよい。一実施形態において、ＰｏＰランド領域１１３内のめっき部材１００が、ＰｏＰランド構造１１６の形成のためのめっきバス（bus）として使用され得る。一実施形態において、めっき部材１００は、めっきバスとして使用され得る銅箔を有し得る。一部の例において、めっき金属は、具体的な用途に従って、金、ニッケル、金／ニッケル、金／ニッケル／パラジウム、及び同様の好適材料を含み得る。一実施形態において、ワイヤボンドパッドがＰｏＰランド領域１１３にめっきされて、例えば、ＣＰＵダイの裏面上の複合技術積層を可能にし得る。
一実施形態において、ダイ領域１１９にビア１１８が形成されて、ダイ１０４のアクティブ面１０８のダイパッド（例えば、銅ダイパッド）が露出され得る（図１ｇ）。ＰｏＰランド構造１１６に隣接するビア１１２（これらは誘電体領域１１４に位置する）、及びダイ領域１１９のビア１１８が金属材料でめっきされて、ＰｏＰランド相互接続（インターコネクト）構造１１７が形成されるとともに、ダイパッド相互接続構造１２０が形成され得る（図１ｈ）。一実施形態において、ＰｏＰランド相互接続構造１１７はＰｏＰランド構造１１６に電気的に接続され、ダイパッド相互接続構造１２０はダイ１０４のアクティブ面１０８のダイパッドに電気的に接続され得る。
一実施形態において、ダイパッド相互接続構造１２０及びＰｏＰ相互接続構造１１７を形成するために、セミアディティブ法（semi-additive process；ＳＡＰ）が用いられ得る。一部の実施形態において、ダイパッド相互接続構造１２０及びＰｏＰ相互接続構造１１７は同一のプロセス工程で形成されることができ、あるいは他の実施形態において、ダイパッド相互接続構造１２０及びＰｏＰ相互接続構造１１７は別々の形成工程で形成されてもよい。ダイパッド相互接続構造１２０及びＰｏＰ相互接続構造１１７の上に、第２の誘電体層１１０’が形成され得る（図１ｉ）。第２の誘電体層１１０’内に第１のメタライゼーション層１２１が形成され得る。
その後、例えば標準的な基板ＳＡＰビルドアッププロセスを用いて、後続のレイヤ（層）群が形成され得る。このとき、ビルドアッププロセスを用いることにより、更なる誘電体層１１０”及びメタライゼーション層１２１’が互いの上に形成されて、コアレス（コアを有しない）基板１２５が形成され得る（図１ｊ）。その後、めっき部材１００がダイ１０４及びコアレス基板１２５のＰｏＰランド構造１１６から取り除かれてＰｏＰランド及びダイが露出され、それにより、コアレスパッケージ構造１２６が形成される（図１ｋ）。コアレスパッケージ構造１２６は、ダイ１０４の周囲に誘電体材料１１０のフィレット構造１２７を有することができ、誘電体材料１１０は、ダイ１０４の側壁１０６及び底面１０８を囲み得るが、ダイ１０４の頂面１０７上には存在しない。
フィレット構造１２７は、コアレス基板１２５の誘電体１１０の平面状の頂面部１１１に対して傾斜／隆起された誘電体１１０の部分を有し得る。このフィレット構造１２７の幾何学形状は、ダイ／パッケージの信頼性を最大化するように最適化されることができ、フィレット構造１２７の角度１２８が、信頼性を最適化するように変化され得る。一実施形態において、フィレット構造の該角度は約７０°又はそれ未満を有し得るが、用途に従って様々となり得る。
一実施形態において、コアレスパッケージ構造１２６は、コアレス基板１２５内に少なくとも部分的に埋め込まれたダイ１０４を有し得る。他の実施形態において、コアレスパッケージ構造１２６は、コアレス基板１２５内に実質的に完全に埋め込まれたダイ１０４を有し得る。一部の実施形態において、ダイ１０４の頂面１０７は誘電体１１０の頂面部１１１と実質的に共平面であってもよい。他の一実施形態において、ダイ１０４の頂面１０７とＰｏＰランド１１６の頂面１３１との間に距離１２９が存在してもよい。
コアレスパッケージ構造１２６は、パッケージ相互接続構造領域１２２を有することができ、例えばボールグリッドアレイ（ＢＧＡ）ボールなどの相互接続構造１２４が取り付けられ得る（図１ｌ）。コアレスパッケージ構造１２６のＰｏＰランド構造１１６は、コアレス基板１２５の頂面に配置された、隆起（突出）した、電解めっきされたランド１１６を有することができ、故に、コアレスパッケージ構造１２６の頂部に別のパッケージを取り付けること（例えば、パッケージ・オン・パッケージ構造）を可能にし得る。
図１ｍは、ＰｏＰ構造１３０を示しており、ＰｏＰランド構造１１６への取り付けによって、第２のパッケージ１３２がコアレスパッケージ構造１２６に接続されている。一実施形態において、第２のパッケージ１３２は、コアレスパッケージ構造１２６のダイ１０４の真上にあるダイ１０４’を有し得る。第２のパッケージ１３２の相互接続ボール１２４’が、コアレスパッケージ構造１２６のＰｏＰランド構造１１６に取り付けられ得る。
図２は、例えば図１ｌのコアレスパッケージ構造１２６などのマイクロエレクトロニクス構造を製造する方法を用いて機能されることが可能な典型的なシステム２００を例示する図である。理解されるように、本実施形態は、本発明に係るコアレスパッケージ構造が使用され得る数多くの考え得るシステムのうちの単なる１つである。
図２は、本発明の一実施形態に従ったコンピュータシステムを示している。システム２００は、プロセッサ２１０、メモリデバイス２２０、メモリコントローラ２３０、グラフィックコントローラ２４０、入力／出力（Ｉ／Ｏ）コントローラ２５０、ディスプレイ２５２、キーボード２５４、ポインティングデバイス２５６、周辺装置２５８、及びバス２６０を含んでいる。プロセッサ２１０は、汎用プロセッサ又は特定用途向け集積回路（ＡＳＩＣ）とし得る。Ｉ／Ｏコントローラ２５０は、有線通信又は無線通信のための通信モジュールを含み得る。メモリデバイス２２０は、ダイナミックランダムアクセスメモリ（ＤＲＡＭ）デバイス、スタティックランダムアクセスメモリ（ＳＲＡＭ）デバイス、フラッシュメモリデバイス、又はこれらのメモリデバイスの組み合わせとし得る。故に、一部の実施形態において、システム２００内のメモリデバイス２２０はＤＲＡＭデバイスを含む必要はない。
システム２００内に示した構成要素のうちの１つ以上が、例えば図１ｌのコアレスパッケージ構造１２６などの１つ以上の集積回路パッケージに含められ得る。例えば、プロセッサ２１０、若しくはメモリデバイス２２０、若しくはＩ／Ｏコントローラ２５０の少なくとも一部、又はこれらのコンポーネントの組み合わせが、図１ａ−１ｍにて説明した構造の少なくとも１つの実施形態を含んだ集積回路パッケージに含められ得る。
システム２００は、コンピュータ（例えば、デスクトップ、ラップトップ、ハンドヘルド、サーバ、Ｗｅｂ機器、ルータなど）、無線通信装置（例えば、セル方式電話、コードレス電話、ポケットベル、携帯情報端末など）、コンピュータ関連周辺機器（例えば、プリンタ、スキャナ、モニタなど）、娯楽機器（例えば、テレビジョン、ラジオ、ステレオ、テーププレーヤ及びコンパクトディスクプレーヤ、ビデオカセットレコーダ、ビデオカメラ、デジタルカメラ、ＭＰ３（ＭＰＥＧオーディオレイヤ３）プレーヤ、ビデオゲーム装置、時計など）、及びこれらに類するものを含み得る。
本発明の利益により、現行のパッケージアーキテクチャのコストのおよそ半分で将来の移動／手持ち式システム・オン・チップ（ＳｏＣ）プロセッサの設計要求を満足することが可能な、新たなパッケージアーキテクチャが可能になる。実施形態により、多くの組立プロセスを排除することが可能な、基板内にダイを埋め込む方法が提供される。実施形態により、薄型ダイアセンブリ、ＰｏＰ互換性、基板設計ルールのスケーラビリティ、パッケージ薄型化、及びパッケージ／アセンブリコスト削減が実現にされる。さらに、基板はもはやストリップ（細長片）での製造可能性に制約されず、それにより、やはりコストを削減するフルパネルプロセスが可能になる。
以上の説明では、本発明に係る方法で使用され得る特定の工程及び材料を詳述しているが、当業者に認識されるように、数多くの変更及び代用が為され得る。そのような変更、改変、代用及び付加は、添付の請求項によって定められる発明の精神及び範囲に入ると見なされるべきものである。また、認識されるように、例えばパッケージ構造などの様々なマイクロエレクトロニクス構造は技術的に広く知られている。故に、ここに提示される図は、典型的なマイクロエレクトロニクスデバイスのうちの、本発明の実施に関係する部分のみを示している。従って、本発明はここに記載された構造に限定されるものではない。

Claims (30)

  1. めっき部材に孔を形成し、
    前記孔内にダイを取り付け、
    前記ダイに隣接して誘電体材料を形成し、
    前記ダイに隣接する前記誘電体材料の領域にビアを形成し、
    前記ビア内にＰｏＰランド領域を形成し、
    前記ＰｏＰランド領域にＰｏＰランド構造を形成し、
    ダイ領域にビアを形成して、前記ダイ上のダイパッドを露出させ、
    前記ダイ領域の前記ビア内にダイパッド相互接続構造を形成するとともに、前記誘電体材料の前記領域の前記ビア内にＰｏＰ相互接続構造を形成し、且つ
    前記めっき部材を除去して、前記ダイと前記ＰｏＰランド構造とを露出させる、
    ことを有する方法。
  2. 前記ダイパッド相互接続構造上及び前記ＰｏＰ相互接続構造上に構造の金属層を形成して、コアレス基板を形成することを更に有する請求項１に記載の方法。
  3. 前記ダイは前記コアレス基板内に部分的に埋め込まれ、前記誘電体材料は前記ダイの側壁の一部に沿って形成される、請求項２に記載の方法。
  4. 前記ダイは前記コアレス基板内に実質的に完全に埋め込まれ、前記誘電体材料は前記ダイの側壁の一部に沿って形成される、請求項２に記載の方法。
  5. 前記誘電体材料の一部は、前記ダイの側壁の一部を囲むフィレット構造を有する、請求項１に記載の方法。
  6. 前記フィレット構造の隆起部分と前記誘電体材料の平面状の頂面部との間に角度を有する、請求項５に記載の方法。
  7. 前記ＰｏＰランド構造は、前記コアレス基板の頂面に、隆起した電解めっきされたランドを有する、請求項２に記載の方法。
  8. 第２のパッケージの相互接続構造を前記ＰｏＰランド構造に取り付けることを更に有する請求項１に記載の方法。
  9. めっき部材に、ダイを保持するための孔を形成し、
    前記孔内にダイを取り付け、
    前記ダイに隣接して誘電体材料を形成し、
    前記ダイに隣接して前記誘電体材料内にビアを形成し、
    前記ビア内にＰｏＰランドを形成し、
    前記ビア内にインターコネクトを形成し、且つ
    前記めっき部材を除去して、前記ＰｏＰランドと前記ダイとを露出させる、
    ことを有し、
    前記ダイは前記ＰｏＰランドより上に配置される、
    方法。
  10. 前記ダイは、接着膜を用いて取り付けられる、請求項９に記載の方法。
  11. 前記めっき部材は電解めっき金属を有する、請求項９に記載の方法。
  12. 前記ビア内に前記ＰｏＰランドを形成することは、前記ビア内にワイヤボンドパッドを形成することを有する、請求項１１に記載の方法。
  13. 前記ビア内に前記ＰｏＰランドを形成することは、前記めっき部材をめっきバスとして用いて前記ＰｏＰランドを形成することを有する、請求項９に記載の方法。
  14. ダイ領域にビアを形成して、前記ダイ上のパッドを露出させ、且つ
    前記ダイ領域の前記ビアをめっきする、
    ことを更に有する請求項９に記載の方法。
  15. 前記ＰｏＰランド上及び前記めっきされたダイビア上にコアレス基板をビルドアップすることを更に有する請求項１４に記載の方法。
  16. コアレス基板内に部分的に埋め込まれて配置されたダイと、
    前記コアレス基板の頂部上の、前記ダイに隣接する隆起したＰｏＰランドと
    を有し、
    前記ＰｏＰランドは、第２の基板を受けることが可能である、
    構造物。
  17. 前記ダイの頂面に配置された接着膜を更に有し、前記コアレス基板はＰｏＰパッケージ構造の一部を有する、請求項１６に記載の構造物。
  18. 前記コアレス基板はＰｏＰパッケージ構造の一部を有し、第２のパッケージの相互接続構造が前記コアレス基板の前記ＰｏＰランド上に配置される、請求項１６に記載の構造物。
  19. 前記ダイは、前記ダイの側壁を囲む誘電体フィレット構造を有する、請求項１６に記載の構造物。
  20. 前記コアレス基板の誘電体材料の平面状の頂面部と前記誘電体フィレット構造との間に角度が存在する、請求項１９に記載の構造物。
  21. 前記第２のパッケージのダイが、前記コアレス基板の前記ダイの真上にある、請求項１８に記載の構造物。
  22. 前記ダイの頂面と前記ＰｏＰランドの頂面との間に距離が存在する、請求項１６に記載の構造物。
  23. コアレス基板に配設されたダイであり、当該ダイの少なくとも一部が前記コアレス基板に埋め込まれたダイと、
    前記ダイに隣接する隆起したＰｏＰランドであり、当該ＰｏＰランド及び前記ダイは第２の基板を受けることが可能である、ＰｏＰランドと、
    前記ダイに隣接する誘電体膜であり、ダイ相互接続構造が当該誘電体膜内に配設されて前記ダイのパッドに接続されている、誘電体膜と、
    前記ＰｏＰランド上に接続されたＰｏＰ相互接続構造と、
    前記ＰｏＰ相互接続構造上及び前記ダイ相互接続構造上に配設された第１の金属層と、
    を有する構造物。
  24. 前記誘電体膜の一部が、前記ダイの側壁に隣接し、且つ前記ＰｏＰランドの頂面より高く隆起されている、請求項２３に記載の構造物。
  25. 前記ＰｏＰランドはめっき金属を有する、請求項２３に記載の構造物。
  26. 当該構造物はコアレスパッケージ構造の一部を有し、第２のパッケージが前記コアレスパッケージ構造に接続される、請求項２３に記載の構造物。
  27. 前記第２のパッケージの相互接続構造が、前記コアレスパッケージ構造の前記ＰｏＰランドに接続される、請求項２６に記載の構造物。
  28. 前記コアレス基板の前記誘電体膜の平面状の頂面部と前記ダイの側壁に隣接する誘電体材料との間に角度が存在する、請求項２４に記載の構造物。
  29. 前記ダイは、約１５０μｍ未満の厚さを有する、請求項２３に記載の構造物。
  30. システムを更に有し、該システムは：
    当該構造物に通信可能に結合されたバスと、
    前記バスに通信可能に結合されたＤＲＡＭと
    を有する、請求項２３に記載の構造物。
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