JP5687709B2 - インターポーザ上へのパッチ取り付け及びそれにより形成される構造体及びその製造方法 - Google Patents
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L2224/732—Location after the connecting process
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Production Of Multi-Layered Print Wiring Board (AREA)
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- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
Claims (28)
- 熱の局部的な供給を行う熱圧着接合により第1の温度で、パッチ構造をインターポーザに取り付ける手順と;
前記インターポーザの上面に配置された相互接続構造のアレイの周囲にアンダーフィルを形成する手順と;
前記アンダーフィルを硬化する手順と;
前記パッチ構造にダイを取り付ける手順と;
を有し、
前記インターポーザに取り付けた前記パッチ構造は、前記アンダーフィルの硬化後にのみ前記第1の温度よりも高い第2の温度にさらされる方法。 - 前記パッチ構造が、前記インターポーザの上面に配置された中間レベル相互接続へ取り付けられる手順を更に有する、請求項1に記載の方法。
- 前記熱圧着接合が、前記アンダーフィルよりも前に行われる手順を更に有する、請求項2に記載の方法。
- 前記アンダーフィルが、中間レベル相互接続構造の周囲に形成される手順を更に有する、請求項2に記載の方法。
- 前記アンダーフィルが、ダイ取り付けプロセスより前に硬化される、請求項1に記載の方法。
- ダイ取り付け前に前記アンダーフィルを硬化することが、前記インターポーザ上の前記パッチ構造を強固にする、請求項1に記載の方法。
- 前記パッチ構造が、約400μmに満たない薄コアを有する手順を更に有する、請求項1に記載の方法。
- 前記インターポーザが、レーザにより積層される相互接続構造を更に有する積層パッケージデザインを有する、請求項1に記載の方法。
- 前記パッチ構造が、デバイスのルーティング及び電源供給機能をサポートすることを可能にする手順を更に有する、請求項1に記載の方法。
- はんだ接合部が、前記パッチ構造を前記インターポーザに取り付ける、請求項1に記載の方法。
- 熱の局部的な供給を行う熱圧着接合により第1の温度で、インターポーザ・ストリップの個別のインターポーザのうち少なくとも1つにパッチ構造を取り付ける手順であって、前記インターポーザ・ストリップが少なくとも2つの個別のインターポーザを有する、手順と;
前記個別のインターポーザのうち少なくとも1つに配置された相互接続構造のアレイの周囲にアンダーフィルを形成する手順と;
前記アンダーフィルを硬化する手順と;
前記パッチ構造にダイを取り付ける手順と;
を有し、
前記インターポーザに取り付けた前記パッチ構造は、前記アンダーフィルの硬化後にのみ前記第1の温度よりも高い第2の温度にさらされる方法。 - 前記インターポーザ・ストリップが、マルチ接続インターポーザ・ストリップ・デザインを有する、請求項11に記載の方法。
- 前記アンダーフィルが、前記インターポーザ・ストリップの分離プロセスより前に、前記インターポーザ・ストリップの少なくとも2つの隣接するインターポーザの中間レベル相互接続領域の周囲に形成される、請求項11に記載の方法。
- 前記少なくとも1つのパッチ構造が、前記インターポーザ・ストリップの個別のインターポーザの中間レベル相互接続に取り付けられる、請求項11に記載の方法。
- 前記少なくとも1つのパッチ構造が、前記アンダーフィルの手順より前に、前記インターポーザ・ストリップに取り付けられる手順を更に有する、請求項11に記載の方法。
- 熱圧着接合により第1の温度で、インターポーザの相互接続アレイの上に配置されたパッチ構造であって、前記インターポーザが積み重ねられた相互接続構造を有する、パッチ構造と;
前記インターポーザに前記パッチ構造を取り付けるはんだ接合部と;
前記相互接続アレイの周囲に配置されたアンダーフィルと;
前記パッチ構造に取り付けられたダイと;
を有し、
前記インターポーザの相互接続アレイの上に配置された前記パッチ構造は、前記アンダーフィルの硬化後にのみ前記第1の温度よりも高い第2の温度にさらされ、
前記パッチ構造が、前記パッチ構造の上面に配置された少なくとも1つの補強材を有する構造体。 - 前記相互接続アレイが、中間レベル相互接続ボール・グリッド・アレイを有する、請求項16に記載の構造体。
- 前記積み重ねられた相互接続構造が、レーザにより形成されたスタックドビアを有する、請求項16に記載の構造体。
- 前記パッチ構造が、約400μmに満たない厚さを有する、請求項17に記載の構造体。
- 前記はんだ接合部が、前記熱圧着接合によって形成されたはんだ接合部を有する、請求項16に記載の構造体。
- 前記パッチ構造が、ルーティング及び電源供給機能をサポートすることが可能である、請求項16に記載の構造体。
- 前記インターポーザが、マザーボード及びスモールカードのうち少なくとも1つを有する、請求項16に記載の構造体。
- 熱圧着接合により第1の温度で、インターポーザ・ストリップの個別のインターポーザに配置された少なくとも1つのパッチ構造であって、前記インターポーザ・ストリップが少なくとも2つの個別のインターポーザを有する、少なくとも1つのパッチ構造と;
個別のインターポーザの上面に配置された相互接続構造のアレイの周囲に配置されたアンダーフィルと;
前記少なくとも1つのパッチ構造に取り付けられたダイと;
を含む構造体を有し、
前記インターポーザに配置された前記パッチ構造は、前記アンダーフィルの硬化後にのみ前記第1の温度よりも高い第2の温度にさらされ、
前記構造体に通信可能に接続されたバスと;
前記バスに通信可能に接続されたDRAMと;
を有するシステムを更に有する、構造体。 - 前記アンダーフィルが、隣接する個別のインターポーザ下に配置される、請求項23に記載の構造体。
- 前記インターポーザ・ストリップが、マルチ接続インターポーザ・ストリップ・デザインを有する、請求項23に記載の構造体。
- 前記個別のインターポーザに前記少なくとも1つのパッチ構造を取り付けるはんだ接合部を更に有する、請求項23に記載の構造体。
- 前記パッチ構造が、薄いパッチ構造を有する、請求項23に記載の構造体。
- 前記構造体が、サーバパッケージの一部を更に有する、請求項23に記載の構造体。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/655,588 US8389337B2 (en) | 2009-12-31 | 2009-12-31 | Patch on interposer assembly and structures formed thereby |
US12/655,588 | 2009-12-31 | ||
PCT/US2010/059843 WO2011081844A2 (en) | 2009-12-31 | 2010-12-10 | Patch on interposer assembly and structures formed thereby |
Publications (2)
Publication Number | Publication Date |
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JP2013511160A JP2013511160A (ja) | 2013-03-28 |
JP5687709B2 true JP5687709B2 (ja) | 2015-03-18 |
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Application Number | Title | Priority Date | Filing Date |
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JP2012539093A Active JP5687709B2 (ja) | 2009-12-31 | 2010-12-10 | インターポーザ上へのパッチ取り付け及びそれにより形成される構造体及びその製造方法 |
Country Status (6)
Country | Link |
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US (2) | US8389337B2 (ja) |
JP (1) | JP5687709B2 (ja) |
KR (1) | KR101374433B1 (ja) |
CN (1) | CN102668067B (ja) |
TW (1) | TWI543281B (ja) |
WO (1) | WO2011081844A2 (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8389337B2 (en) | 2009-12-31 | 2013-03-05 | Intel Corporation | Patch on interposer assembly and structures formed thereby |
US9059241B2 (en) | 2013-01-29 | 2015-06-16 | International Business Machines Corporation | 3D assembly for interposer bow |
TWI489227B (zh) * | 2013-05-06 | 2015-06-21 | 巨擘科技股份有限公司 | 腕錶結構、腕錶用的電子旋鈕以及顯示器型腕錶 |
TWI556074B (zh) * | 2013-05-06 | 2016-11-01 | 巨擘科技股份有限公司 | 腕錶結構 |
CN104142623A (zh) * | 2013-05-06 | 2014-11-12 | 巨擘科技股份有限公司 | 腕表结构及腕表用的电子机芯 |
TW201503768A (zh) * | 2013-07-05 | 2015-01-16 | Phison Electronics Corp | 焊墊結構及應用其之印刷電路板與記憶體儲存裝置 |
DE112015006975T5 (de) * | 2015-09-25 | 2019-05-09 | Intel Corporation | Mikroelektronische Packung mit drahtloser Zwischenverbindung |
US9607973B1 (en) | 2015-11-19 | 2017-03-28 | Globalfoundries Inc. | Method for establishing interconnects in packages using thin interposers |
US9761535B1 (en) | 2016-06-27 | 2017-09-12 | Nanya Technology Corporation | Interposer, semiconductor package with the same and method for preparing a semiconductor package with the same |
US11552019B2 (en) * | 2019-03-12 | 2023-01-10 | Intel Corporation | Substrate patch reconstitution options |
US11973058B2 (en) | 2021-11-25 | 2024-04-30 | International Business Machines Corporation | Multiple die assembly |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2966972B2 (ja) * | 1991-07-05 | 1999-10-25 | 株式会社日立製作所 | 半導体チップキャリアとそれを実装したモジュール及びそれを組み込んだ電子機器 |
US6294407B1 (en) * | 1998-05-06 | 2001-09-25 | Virtual Integration, Inc. | Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same |
US6670430B1 (en) * | 1999-12-17 | 2003-12-30 | Henkel Loctite Corporation | Thermosetting resin compositions comprising epoxy resins, adhesion promoters, and curatives based on the combination of nitrogen compounds and transition metal complexes |
JP2004327951A (ja) * | 2003-03-06 | 2004-11-18 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP2005011908A (ja) * | 2003-06-17 | 2005-01-13 | Ngk Spark Plug Co Ltd | 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体 |
US7027289B2 (en) * | 2004-03-25 | 2006-04-11 | Intel Corporation | Extended thin film capacitor (TFC) |
JP2006086399A (ja) * | 2004-09-17 | 2006-03-30 | Ngk Spark Plug Co Ltd | 半導体パッケージの製造方法、中継基板の製造方法 |
US7372126B2 (en) * | 2005-03-31 | 2008-05-13 | Intel Corporation | Organic substrates with embedded thin-film capacitors, methods of making same, and systems containing same |
US7495330B2 (en) * | 2005-06-30 | 2009-02-24 | Intel Corporation | Substrate connector for integrated circuit devices |
WO2007052422A1 (ja) * | 2005-11-01 | 2007-05-10 | Murata Manufacturing Co., Ltd. | 回路装置の製造方法および回路装置 |
KR100929839B1 (ko) * | 2007-09-28 | 2009-12-04 | 삼성전기주식회사 | 기판제조방법 |
KR101551898B1 (ko) * | 2007-10-05 | 2015-09-09 | 신꼬오덴기 고교 가부시키가이샤 | 배선 기판, 반도체 장치 및 이들의 제조 방법 |
US8116097B2 (en) * | 2007-11-02 | 2012-02-14 | Oracle America, Inc. | Apparatus for electrically coupling a semiconductor package to a printed circuit board |
US8193624B1 (en) * | 2008-02-25 | 2012-06-05 | Amkor Technology, Inc. | Semiconductor device having improved contact interface reliability and method therefor |
US7936060B2 (en) * | 2009-04-29 | 2011-05-03 | International Business Machines Corporation | Reworkable electronic device assembly and method |
US8389337B2 (en) | 2009-12-31 | 2013-03-05 | Intel Corporation | Patch on interposer assembly and structures formed thereby |
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US20130141859A1 (en) | 2013-06-06 |
KR101374433B1 (ko) | 2014-03-17 |
CN102668067A (zh) | 2012-09-12 |
CN102668067B (zh) | 2016-06-01 |
WO2011081844A2 (en) | 2011-07-07 |
US8659171B2 (en) | 2014-02-25 |
JP2013511160A (ja) | 2013-03-28 |
US20110156276A1 (en) | 2011-06-30 |
KR20120098847A (ko) | 2012-09-05 |
TWI543281B (zh) | 2016-07-21 |
US8389337B2 (en) | 2013-03-05 |
WO2011081844A3 (en) | 2011-10-13 |
TW201133670A (en) | 2011-10-01 |
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