TWI598999B - 多元件封裝體與其製備方法 - Google Patents

多元件封裝體與其製備方法 Download PDF

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Publication number
TWI598999B
TWI598999B TW104127533A TW104127533A TWI598999B TW I598999 B TWI598999 B TW I598999B TW 104127533 A TW104127533 A TW 104127533A TW 104127533 A TW104127533 A TW 104127533A TW I598999 B TWI598999 B TW I598999B
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Taiwan
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layer
wafer
layout
element package
forming
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TW104127533A
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TW201643999A (zh
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管式凡
羅翊仁
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美光科技公司
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Description

多元件封裝體與其製備方法
本發明係關於一種多元件封裝體及其製造方法。
隨著半導體元件製造技術演進，半導體元件的電路密度不斷增加且元件尺寸亦進一步微縮以得到高集成密度的半導體元件。如此一來，在半導體元件的尺寸減少與密度增加的情況下，對於封裝技術的要求亦對應地漸驅嚴苛。近年來隨著對尺寸更小之電子裝置需求的成長，對於半導體晶片需要更創新的封裝技術。
通常會製備多個元件於一晶圓上，並以切割製程將晶圓上的多個元件分離成獨立的晶片。此些晶片會置放於一乘載基板上，再進行封裝製程以集成多個晶片於一個封裝體中。然而，在置放晶片於乘載基板上的過程中會產生震動，使得晶片易產生斷線或損壞的問題並降低了封裝體的良率。此外，使用乘載基板需耗費額外的成本，此更降低了封裝製程的效率。據此，業界亟需一種新穎的封裝體結構與其製備方法以解決上述的問題。
本發明之一態樣係提供一種多元件封裝體，包含一基板、至少兩個元件區域、一第一重佈局層、一外部晶片以及複數個第一連接件。此兩個元件區域係自基板形成，而第一重佈局層設置於基板上，並電性連接至此兩個元件區域。外部晶片設置於第一重佈局層上，而複數個第一連接件設置於第一重佈局層與外部晶片之間，以連接第一重佈局層與外部晶片。
根據本發明一或多個實施方式，多元件封裝體更包含複數個第二連接件設置於第一重佈局層上。
根據本發明一或多個實施方式，第二連接件之一直徑大於第一連接件之一直徑與外部晶片之一厚度的總和。
根據本發明一或多個實施方式，多元件封裝體更包含一封膠層、一第二重佈局層以及複數個第三連接件。封膠層覆蓋外部晶片與第一重佈局層，第二重佈局層設置於封膠層上，而此些第三連接件設置於第二重佈局層上。
根據本發明一或多個實施方式，封膠層包含一第一導電接觸通過封膠層以連接第一重佈局層與第二重佈局層。
根據本發明一或多個實施方式，封膠層包含一第二導電接觸通過封膠層與外部晶片以連接第一重佈局層與第二重佈局層。
根據本發明一或多個實施方式，第一重佈局層與 第二重佈局層包含一介電層、複數個金屬層以及複數個導電柱。此些金屬層於介電層中呈平行排列，而此些導電柱同樣位於介電層中並電性連接相鄰的兩金屬層。
根據本發明一或多個實施方式，封膠層包含環氧樹脂。
本發明之一態樣係提供一種多元件封裝體，包含一基板、至少兩個元件區域、一第一重佈局層、一外部晶片、一第二重佈局層以及一封膠層。此兩個元件區域係自基板形成，而第一重佈局層設置於基板上。外部晶片設置於第一重佈局層上，而第二重佈局層設置於第一重佈局層上。封膠層設置於第一重佈局層與第二重佈局層之間，且封膠層包含一第一導電接觸與一第二導電接觸。第一導電接觸通過封膠層，而第二導電接觸通過封膠層與外部晶片，且第一導電接觸與第二導電接觸連接第一重佈局層與第二重佈局層。
本發明之一態樣係提供一種多元件封裝體的製備方法，包含下列步驟。先形成一第一重佈局層於一晶圓上，晶圓具有至少兩個元件區域，且第一重佈局層電性連接至此兩個元件區域。接著形成複數個第一連接件於第一重佈局層上，並配置一外部晶片於此些第一連接件上，以令使外部晶片藉由此些第一連接件電性連接至第一重佈局層。
根據本發明一或多個實施方式，多元件封裝體的製備方法更包含形成複數個第二連接件於第一重佈局層上，且第二連接件之一直徑大於第一連接件之一直徑與外部晶片之一厚度的總和。
根據本發明一或多個實施方式，多元件封裝體的製備方法更包含下列步驟。形成一暫時黏著層覆蓋第二連接件與外部晶片並薄化晶圓，最後再移除暫時黏著層。
根據本發明一或多個實施方式，多元件封裝體的製備方法更包含沿著一切割道切割晶圓以形成多元件封裝體。
根據本發明一或多個實施方式，外部晶片具有一第一穿孔。
根據本發明一或多個實施方式，多元件封裝體的製備方法更包含下列步驟。形成一封膠層覆蓋第一重佈局層與外部晶片，並移除部分的封膠層以形成一第二穿孔與一第三穿孔。其中第二穿孔暴露第一重佈局層，而第三穿孔貫通第一穿孔以暴露第一重佈局層。之後再填充一導電材料至第一穿孔、第二穿孔與第三穿孔中以形成一第一導電接觸與一第二導電接觸。
根據本發明一或多個實施方式，多元件封裝體的製備方法更包含下列步驟。形成一第二重佈局層於封膠層上，且第二重佈局層電性連接至第一導電接觸與第二導電接觸。之後再形成複數個第三連接件於第二重佈局層上。
根據本發明一或多個實施方式，多元件封裝體的製備方法更包含下列步驟。形成一暫時黏著層覆蓋第三連接件與第二重佈局層並薄化晶圓，最後再移除暫時黏著層。
根據本發明一或多個實施方式，多元件封裝體的製備方法更包含沿著切割道切割晶圓以形成多元件封裝體。
根據本發明一或多個實施方式，形成第一重佈局層於晶圓上包含下列步驟。沉積一介電材料覆蓋晶圓，再移除部分的介電材料以形成複數個開口暴露晶圓中的此些元件區域。之後形成複數個導電柱於此些開口中，並形成一金屬層於此些導電柱上後再圖案化金屬層。
根據本發明一或多個實施方式，形成第二重佈局層於晶圓上包含下列步驟。沉積一介電材料覆蓋封膠層，再移除部分的介電材料以形成複數個開口暴露第一導電接觸與第二導電接觸。之後形成複數個導電柱於此些開口中，並形成一金屬層於此些導電柱上後再圖案化金屬層。
100、200、200a‧‧‧多元件封裝體
110、210‧‧‧基板
120、220‧‧‧元件區域
122、222‧‧‧導電墊
130、230‧‧‧第一重佈局層
132、232、272‧‧‧介電層
134、234、274‧‧‧金屬層
136、236、276‧‧‧導電柱
140、240‧‧‧外部晶片
150、250‧‧‧第一連接件
160‧‧‧第二連接件
242‧‧‧第一穿孔
260‧‧‧封膠層
262‧‧‧第一導電接觸
264‧‧‧第二導電接觸
270‧‧‧第二重佈局層
280‧‧‧第三連接件
300、400‧‧‧晶圓
310、420‧‧‧暫時黏著層
312、422‧‧‧黏著層
314、424‧‧‧乘載層
320、430‧‧‧切割道
412‧‧‧第二穿孔
414‧‧‧第三穿孔
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之詳細說明如下：第1A圖為依據本發明之部分實施方式中一種多元件封裝體的上視圖；第1B圖為本發明之部分實施方式中，第1A圖的多元件封裝體沿著AA剖線的剖視圖；第2A圖為依據本發明之部分實施方式中一種多元件封裝體的上視圖；第2B圖為本發明之部分實施方式中，第2A圖的多元件封裝體沿著AA剖線的剖視圖；第2C圖為本發明之部分實施方式中外部晶片的立體示意圖； 第2D圖為本發明之其他部分實施方式中一種多元件封裝體的剖視圖；第3A至3D圖為依據本發明之部分實施方式中，第1A與1B圖的多元件封裝體在製程各個階段的剖視圖；第4A至4F圖為依據本發明之部分實施方式中，第2A與2B圖的多元件封裝體在製程各個階段的剖視圖；以及第5圖為依據本發明之部分實施方式中，第2D圖的多元件封裝體在製程的中間階段的剖視圖。
之後將以示例圖式以詳細描述本發明的各種實施方式，且在圖式和說明書中使用相同的元件符號以指代相同或相似的部分。
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
請參閱第1A圖與第1B圖。第1A圖為依據本發明之部分實施方式中一種多元件封裝體的上視圖，而第1B圖為本發明之部分實施方式中，第1A圖的多元件封裝體沿著AA剖線的剖視圖。如第1A圖與第1B圖所示，一多元件封裝體100包含一基板110、至少兩個元件區域120、一第 一重佈局層130、一外部晶片140、複數個第一連接件150與複數個第二連接件160。
此些元件區域120係自基板110形成，因此元件區域120與基板110之間無任何介面(interface)。通常會切割一晶圓以將其上的多個元件區域分離成獨立的晶片，並將此些晶片置放於一乘載基板上，因此會形成介面於乘載基板與晶片之間。接著再進行封裝製程以集成多個晶片於一個封裝體中。然而在置放晶片於乘載基板上的過程中會產生震動，使得晶片易產生斷線或損壞的問題並降低了封裝體的良率。此外，使用乘載基板需花費額外的成本，此更降低了封裝製程的效率。相對於先前技術，本發明的多元件封裝體100是以晶圓級(wafer-level)封裝製程所製備。晶圓級封裝是指在形成此些元件區域120於晶圓中後，再封裝與測試整片晶圓中的元件，之後再切割晶圓而形成第1A與1B圖所示的多元件封裝體100。值得注意的是，晶圓中的此些元件區域120在切割前即先進行直接集成，因此可省略使用乘載基板，且元件區域120與基板110之間無任何界面。
每一個元件區域120包含一半導體元件、一層間介電層(inter-layer dielectric(ILD)layer)覆蓋半導體元件、一內金屬介電層(inter-metal dielectric(IMD)layer)位於層間介電層上、以及一金屬內連結構設置於內金屬介電層中並電性連接至半導體元件。此外，每一個元件區域120具有一導電墊122，其為金屬內連結構的最上層金屬層。在本發明之部分實施方式中，基板110係形成自一晶 圓，而晶圓的材質包含矽、鍺、或其他的III-V族元素，但不以此為限。在本發明之其他實施方式中，半導體元件為一記憶體元件，但不以此為限，其他的半導體元件同樣適用於本發明。
繼續參閱第1B圖，第一重佈局層130設置於基板110上並電性連接至至少兩個元件區域120。第一重佈局層130與元件區域120的導電墊122接觸，以使此些元件區域120藉由第一重佈局層130彼此電性連接。再參閱第1A圖，第1A圖繪示的多元件封裝體100中具有四個元件區域120，而第一重佈局層130電性連接這四個元件區域120。舉例來說，元件區域120中的半導體元件可為記憶體元件，且每一個元件區域120可提供2G(gigabyte)的儲存容量。第一重佈局層130則集成此四個元件區域120而達到8G的儲存容量，但不以此為限。
再者，第一重佈局層130更可重新分配或重新定位信號至外部設備或輸入/輸出連結的配置處。第一重佈局層130包含一介電層132、複數個金屬層134與複數個導電柱136。此些金屬層134於介電層132中呈平行排列，而導電柱136同樣位於介電層132以電性連接相鄰的兩金屬層134。值得注意的是，金屬層134更藉由導電柱136以電性連接至元件區域120的導電墊122，因此可藉由導電墊122、導電柱136與金屬層134以電性連接至少兩個元件區域120。此外，可依據設計需求預先決定導電層136的數量。在本發明之部分實施方式中，導電柱136與金屬層134的材 質包含鋁、銅、或其組合，但不以此為限。其他合適的導電材料同樣可用於形成導電柱136與金屬層134。在本發明之其他實施方式中，介電層132之材質包含氧化矽、氮化矽、氮氧化矽、或其組合，但不以此為限。其他合適的絕緣材料同樣可用於形成介電層132。
繼續參閱第1A與1B圖，外部晶片140設置於第一重佈局層130上，而複數個第一連接件150位於第一重佈局層130與外部晶片140之間以連接第一重佈局層130與外部晶片140。如前所述，第一重佈局層130係電性連接至至少兩個元件區域120，而第一連接件150設置於第一重佈局層130上並接觸第一重佈局層130。外部晶片140則設置於第一連接件150上並接觸第一連接件150，因此外部晶片140能藉由第一連接件150、第一重佈局層130與導電墊122而電性連接至此些元件區域120。藉此，外部晶片140即可接收元件區域120的訊號並進行運算操作。
繼續參閱第1A與1B圖，複數個第二連接件160設置於第一重佈局層130上。如第1A圖所示，此些第二連接件160環繞外部晶片140。第二連接件160設置於第一重佈局層130上並接觸第一重佈局層130以使外部晶片140產生的運算結果傳輸至第二連接件160。此些第二連接件160更傳輸運算結果至一外部裝置，例如一印刷電路板。在本發明之部分實施方式中，第二連接件160之一直徑大於第一連接件150之一直徑與該外部晶片140之一厚度的總和，藉此讓外部晶片140不會與後續形成的印刷電路板接觸，以避免錯 誤的電性連接。在本發明之部分實施方式中，第一連接件150與第二連接件160可為材質為錫的焊球或焊接凸塊，但不以此為限。
繼續參閱參閱第2A圖與第2B圖。第2A圖為依據本發明之部分實施方式中一種多元件封裝體的上視圖。如第2A圖與第2B圖所示，一多元件封裝體200包含一基板210、至少兩個元件區域220、一第一重佈局層230、一外部晶片240、複數個第一連接件250、一封膠層260、一第二重佈局層270與複數個第三連接件280。
此些元件區域220係自基板210形成，因此元件區域220與基板210之間無任何介面。本發明的晶片封裝體200同樣是以晶圓級封裝製程所製備，其是指在形成此些元件區域220於晶圓中後，再封裝與測試整片晶圓中的元件，之後再切割晶圓而形成第2A與2B圖所示的多元件封裝體200。值得注意的是，晶圓中的此些元件區域220在切割前即先進行直接集成，因此可省略使用乘載基板，且元件區域220與基板210之間無任何界面。每一個元件區域220包含一半導體元件、一層間介電層覆蓋半導體元件、一內金屬介電層位於層間介電層上、以及一金屬內連結構設置於內金屬介電層中並電性連接至半導體元件。此外，每一個元件區域220具有一導電墊222，其為金屬內連結構的最上層金屬層。
在本發明之部分實施方式中，基板210係形成自一晶圓，而晶圓的材質包含矽、鍺、或其他的III-V族元素，但不以此為限。在本發明之其他實施方式中，半導體元 件為一記憶體元件，但不以此為限，其他的半導體元件同樣適用於本發明。
繼續參閱第2B圖，第一重佈局層230設置於基板210上並電性連接至至少兩個元件區域220。第一重佈局層230與元件區域220的導電墊222接觸，以使此些元件區域220藉由第一重佈局層230彼此電性連接。再參閱第2A圖，第2A圖繪示的多元件封裝體200中具有四個元件區域220，而第一重佈局層230電性連接這四個元件區域220。舉例來說，元件區域220中的半導體元件可為記憶體元件，且每一個元件區域220可提供2G的儲存容量。第一重佈局層230則集成此四個元件區域220而達到8G的儲存容量，但不以此為限。
再者，第一重佈局層230更可重新分配或重新定位信號至外部設備或輸入/輸出連結的配置處。第一重佈局層230包含一介電層232、複數個金屬層234與複數個導電柱236。此些金屬層234於介電層232中呈平行排列，而導電柱236同樣位於介電層232中以電性連接相鄰的兩金屬層234。值得注意的是，金屬層234更藉由導電柱236以電性連接至元件區域220的導電墊222，因此可藉由導電墊222、導電柱236與金屬層234以電性連接至少兩個元件區域220。此外，可依據設計需求預先決定導電層234的數量。在本發明之部分實施方式中，導電柱236與金屬層234的材質包含鋁、銅、或其組合，但不以此為限。其他合適的導電材料同樣可用於形成導電柱236與金屬層234。在本發明之 其他實施方式中，介電層232之材質包含氧化矽、氮化矽、氮氧化矽、或其組合，但不以此為限。其他合適的絕緣材料同樣可用於形成介電層232。
繼續參閱第2A與2B圖，外部晶片240設置於第一重佈局層230上，而複數個第一連接件250位於第一重佈局層230與外部晶片240之間以連接第一重佈局層230與外部晶片240。如前所述，第一重佈局層230係電性連接至至少兩個元件區域220，而第一連接件250設置於第一重佈局層230上並接觸第一重佈局層230。外部晶片240則設置於第一連接件250上並接觸第一連接件250，因此外部晶片240能藉由第一連接件250、多元件封裝體200與導電墊222而電性連接至此些元件區域222。藉此，外部晶片140即可接收元件區域220的訊號並進行運算操作。
多元件封裝體100與多元件封裝體200之間的差別在於多元件封裝體200中並不具有接觸第一重佈局層230的第二連接件。多元件封裝體200具有覆蓋第一重佈局層230與外部晶片240的封膠層260，且第二重佈局層270設置於封膠層260上。封膠層260中具有一第一導電接觸262以及一第二導電接觸264。第一導電接觸262通過封膠層260，因此其將接觸第一重佈局層230與第二重佈局層270，以連接第一重佈局層230與第二重佈局層270。再者，第二導電接觸264通過封膠層260與外部晶片240，因此其將接觸第一重佈局層230與第二重佈局層270，以連接第一重佈局層230與第二重佈局層270。在本發明之部分實施方 式中，封膠層260之材質包含環氧樹脂。
請參閱第2C以更清楚理解外部晶片240的結構。第2C圖為本發明之部分實施方式中外部晶片的立體圖。如第2C圖所示，外部晶片240具有一第一穿孔242貫穿外部晶片240，而第二導電接觸264通過封膠層260與此第一穿孔242而接觸外部晶片240下方的第一重佈局層230，以提高第一重佈局層230與第二重佈局層270之間的電性連接性質。再者，第一重佈局層230與第二重佈局層270的線路佈局方式可較為彈性，更增加了製程效率。值得注意的是，第二導電接觸264不會接觸外部晶片240中的內部線路以避免錯誤的連接關係。
第二重佈局層270包含一介電層272、複數個金屬層274與複數個導電柱276。此些金屬層274於介電層272中呈平行排列，而導電柱276同樣位於介電層272中以電性連接相鄰的兩金屬層274。值得注意的是，金屬層274更藉由導電柱276以電性連接至第一導電接觸262與第二導電接觸264。此外，更可依據設計需求預先決定導電層274的數量。
繼續參閱第2A與2B圖，複數個第三連接件280設置於第二重佈局層270上。此些第三連接件280接觸第二重佈局層270以使外部晶片240產生的運算結果藉由第一連接件250、第一重佈局層230、第一導電接觸262、第二導電接觸264與第二重佈局層270傳輸至第三連接件280。此些第三連接件280更傳輸運算結果至一外部裝置，例如一印 刷電路板。此外，藉由第二導電接觸264的設置，第三連接件280的布局可更為彈性。在本發明之部分實施方式中，第一連接件250與第三連接件285可為材質為錫的焊球或焊接凸塊，但不以此為限。
相較於多元件封裝體100，多元件封裝體200中的第三連接件280的尺寸相似於多元件封裝體100中的第二連接件160的尺寸，但第三連接件280的密集度大於第二連接件160。由於第三連接件280與外部晶片240分別設置於不同的層別，此增加置放第三連接件280的空間並提升其密集度。藉此，具有較高密集度的第三連接件280更提高多元件封裝體200與印刷電路板之間的電性連接性質。
接著參閱第2D圖，第2D圖為本發明之部分實施方式中一種多元件封裝體的剖視圖。第2D圖繪示一多元件封裝體200a，並於下文中討論多元件封裝體200a與多元件封裝體200之間的差別。在多元件封裝體200a中省略了第二重佈局層270，因此此些第三連接件280係直接設置於封膠層260上。具體而言，每一個第三連接件280均位於封膠層260上並接觸第一導電接觸262或第二導電接觸264，以使外部晶片240產生的運算結果藉由第一連接件250、第一重佈局層230、以及第一導電接觸262或第二導電接觸264傳輸至第三連接件280。此些第三連接件280更傳輸運算結果至其他外部裝置，例如印刷電路板。值得注意的是，省略第二重佈局層270的好處在於可減少晶片封裝體200a的厚度，此外更可提升封膠層260上的第三連接件280之密集 度，以提高多元件封裝體200a與後續形成的印刷電路板之間的電性連接性質。
請參閱第3A至3D圖以清楚理解第1A與1B圖中的多元件封裝體100的製備方法。第3A至3D圖為依據本發明之部分實施方式中，第1A與1B圖的多元件封裝體在製程各個階段的剖視圖。
先參閱第3A圖，形成一第一重佈局層130於一晶圓300上，晶圓300具有至少兩個元件區域120，且第一重佈局層130電性連接至此兩個元件區域120。值得注意的是，每一個元件區域120包含一半導體元件、一層間介電層覆蓋半導體元件、一內金屬介電層位於層間介電層上、以及一金屬內連結構設置於內金屬介電層中並電性連接至半導體元件。此外，每一個元件區域120具有一導電墊122，其為金屬內連結構的最上層金屬層。第一重佈局層130係以下列的步驟所形成。先沉積一介電材料以覆蓋晶圓300，接著使用微影蝕刻製程移除部分的介電材料，藉此形成多個開口以暴露晶圓300中的元件區域120。具體而言，每一個開口係對應至元件區域120的一個導電墊122。之後形成複數個導電柱136於此些開口中，再形成一金屬層134於導電柱136上，並依據佈局設置(layout design)圖案化金屬層134以電性連接至少兩個元件區域120。上述的步驟可重複數次以製備得第一重佈局層130，其具有複數個金屬層134於一介電層132中，且可依據設計需求預先決定導電層134的數量。
參閱第3B圖，形成複數個第一連接件150於第一重佈局層130上，並配置一外部晶片140於此些第一連接件150上。可使用一回焊製程以形成此些第一連接件150於第一重佈局層130上，接著再形成外部晶片140接觸此些第一連接件150。外部晶片140藉由第一連接件150、第一重佈局層130與導電墊122電性連接至多個元件區域120，藉此外部晶片140即可接收此些元件區域120的訊號並進行運算操作。
繼續參閱第3C圖，形成複數個第二連接件於第一重佈局層130上，並形成一暫時黏著層310覆蓋第二連接件160與外部晶片140。同樣使用一回焊製程以形成此些第二連接件160於第一重佈局層130上，且第二連接件160之一直徑大於第一連接件150之一直徑與外部晶片140之一厚度的總和以確保外部晶片140不會與後續形成的印刷電路板接觸。在形成第二連接件160後即形成暫時黏著層310，接著再薄化晶圓300以減少其厚度，以讓最後形成的多元件封裝體具有較小的尺寸。暫時黏著層310具有一乘載層314與一黏著層312。暫時黏著層310能減少薄化製程中產生的應力，因此降低了晶圓破裂的風險。在本發明之部分實施方式中，暫時黏著層310為一膠帶。在本發明之部分實施方式中，晶圓300係以一化學機械研磨(chemical mechanical polishing)製程進行薄化。
繼續參閱第3D圖，移除暫時黏著層310，並沿著一切割道320切割晶圓300以形成第2A與2B圖所示的多元件封裝體100。可使用合適的溶劑消除黏著層312的黏性 以分離暫時黏著層310與晶圓300。之後再沿著切割道320切割晶圓300以形成多個獨立的多元件封裝體100。值得注意的是，切割道320不會通過第一重佈局層130中的金屬層134，以避免第一重佈局層130的斷線。在本發明之部分實施方式中，在移除暫時黏著層310前即先沿著切割道320切割晶圓300。在本發明之其他部分實施方式中，多元件封裝體100更藉由第二連接件160連接至一印刷電路板，而外部晶片140產生的運算結果即可藉由第一連接件150、第一重佈局層130以及第二連接件160傳輸至印刷電路板。
請參閱第4A至4F圖以清楚理解第2A與2B圖中的多元件封裝體200的製備方法。第4A至4F圖為依據本發明之部分實施方式中，第2A與2B圖的多元件封裝體在製程各個階段的剖視圖。
先參閱第4A圖，形成一第一重佈局層230於一晶圓400上，晶圓400具有至少兩個元件區域220，且第一重佈局層230電性連接至此兩個元件區域220。值得注意的是，每一個元件區域220包含一半導體元件、一層間介電層覆蓋半導體元件、一內金屬介電層位於層間介電層上、以及一金屬內連結構設置於內金屬介電層中並電性連接至半導體元件。此外，每一個元件區域220具有一導電墊222，其為金屬內連結構的最上層金屬層。形成第一重佈局層230的步驟類似於形成第一重佈局層130的步驟，其細節在此不再贅述。
參閱第4B圖，形成複數個第一連接件250於第一重佈局層230上，並配置一外部晶片240於此些第一連接 件250上。可使用一回焊製程以形成此些第一連接件250於第一重佈局層230上，接著再形成外部晶片240接觸此些第一連接件250。外部晶片240藉由第一連接件250、第一重佈局層230與導電墊222電性連接至多個元件區域220，藉此外部晶片240即可接收此些元件區域220的訊號並進行運算操作。
繼續參閱第4C圖，形成一封膠層260覆蓋第一重佈局層230與外部晶片240，並移除部分的封膠層260已形成一第二穿孔412與一第三穿孔414。第二穿孔412暴露第一重佈局層230，而第三穿孔414貫通外部晶片240的第一穿孔242以暴露第一重佈局層230。可塗佈或噴灑環氧樹脂以形成封膠層260，再使用微影蝕刻製程移除部分的封膠層260以形成第二穿孔412與第三穿孔414。如之前於第2C圖中所述，外部晶片240具有第一穿孔242，而第三穿孔414大致對準於第一穿孔242以暴露外部晶片240下的第一重佈局層230。再者，第二穿孔412通過封膠層260並同樣暴露第一重佈局層230。之後，填充一導電材料至第一穿孔242、第二穿孔412與第三穿孔414中以形成一第一導電接觸262與一第二導電接觸264。在本發明之部分實施方式中，第一導電接觸262與第二導電接觸264之材質包含銅、鋁、及其組合，但不以此為限。
繼續參閱第4D圖，形成一第二重佈局層270於封膠層260上。第二重佈局層270係以下列的步驟所形成。先沉積一介電材料以覆蓋封膠層260，接著使用微影蝕刻製程移除部分的介電材料，藉此形成多個開口，每一個開口係 對應至第一導電接觸262或第二導電接觸264。之後形成複數個導電柱276於此些開口中，再形成一金屬層274於導電柱276上，並依據佈局設置(layout design)圖案化金屬層274。上述的步驟可重複數次以製備得第一重佈局層270，其具有複數個金屬層274於一介電層272中，且可依據設計需求預先決定導電層274的數量。
繼續參閱第4E圖，形成複數個第三連接件280於第二重佈局層270上，並形成一暫時黏著層420覆蓋第三連接件280與第二重佈局層270。使用一回焊製程以形成此些第三連接件280於第二重佈局層270上。在形成第三連接件280後即形成暫時黏著層420，接著再薄化晶圓400以減少其厚度，以讓最後形成的多元件封裝體具有較小的尺寸。暫時黏著層420具有一乘載層424與一黏著層422。暫時黏著層420能減少薄化製程中產生的應力，因此降低了晶圓破裂的風險。在本發明之部分實施方式中，暫時黏著層420為一膠帶。在本發明之部分實施方式中，晶圓400係以一化學機械研磨製程進行薄化。
繼續參閱第4F圖，移除暫時黏著層420，並沿著一切割道430切割晶圓400以形成第2A與2B圖所示的多元件封裝體200。可使用合適的溶劑消除黏著層412的黏性以分離暫時黏著層420與晶圓400。之後再沿著切割道430切割晶圓400以形成多個獨立的多元件封裝體200。值得注意的是，切割道430不會通過第一重佈局層230中的金屬層234與第二重佈局層270中的金屬層274，以避免第一重佈局層230與第二重佈局層270的斷線。在本發明之部分實施 方式中，在移除暫時黏著層420前即先沿著切割道430切割晶圓400。在本發明之其他部分實施方式中，多元件封裝體200更藉由第三連接件260連接至一印刷電路板，而外部晶片240產生的運算結果即可藉由第一連接件250、第一重佈局層230、第一導電接觸262、第二導電接觸264、第二重佈局層270以及第三連接件280傳輸至印刷電路板。
請繼續參閱第5圖，第5圖為依據本發明之部分實施方式中，第2D圖的多元件封裝體在製程的中間階段的剖視圖。具體而言，第5圖為晶片封裝體200a於製造過程中第4C圖下一階段的剖面示意圖。在形成第一導電接觸262與第二導電接觸264於封膠層260中後，更使用回焊製程形成第三連接件280於封膠層260上。值得注意的是，每一個第三連接件280係接觸第一導電接觸262或第二導電接觸264，以電性連接至外部晶片240。之後再使用類似於第4E與4F圖的薄化製程與切割製程，以減少晶圓400的厚度並將晶圓400切割成多個如第2D圖所示之獨立的多元件封裝體200a，其細節在此不再詳述。
由上述本發明實施例可知，本發明優於習知的封裝體結構與製備方法，並總結此些優點如下。本發明提供一種晶圓級封裝製程，以集成至少兩個元件區域於一個多元件封裝體中，而不需使用任何乘載基板，因此多元件封裝體中的基板與元件區域之間不具有任何界面。再者，晶圓中的元件區域係直接集成而可降低元件區域斷線或損壞的風險。總結以上數點，省略乘載基板的使用降低了多元件封裝體的成本，而封裝製程的效率更大幅增加並提升了多元件封裝體的良率。
本發明已經相當詳細地描述某些實施方式，但其他的實施方式亦為可能的。因此，所附請求項的精神和範籌不應限於本文所描述的實施方式。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧多元件封裝體
110‧‧‧基板
120‧‧‧元件區域
122‧‧‧導電墊
130‧‧‧第一重佈局層
132‧‧‧介電層
134‧‧‧金屬層
136‧‧‧導電柱
140‧‧‧外部晶片
150‧‧‧第一連接件
160‧‧‧第二連接件

Claims (15)

  1. 一種多元件封裝體，包含：自一基板形成的至少兩個元件區域；一第一重佈局層設置於該基板上，並電性連接至該兩個元件區域；一外部晶片設置於該第一重佈局層上；複數個第一連接件設置於該第一重佈局層與該外部晶片之間，以連接該第一重佈局層與該外部晶片；一封膠層覆蓋該外部晶片與該第一重佈局層；以及一第二重佈局層設置於該封膠層上，其中該封膠層包含一第一導電接觸通過該封膠層與該外部晶片以連接該第一重佈局層與該第二重佈局層。
  2. 如請求項1所述之多元件封裝體，更包含複數個第二連接件設置於該第二重佈局層上。
  3. 如請求項1所述之多元件封裝體，其中該封膠層包含一第二導電接觸通過該封膠層以連接該第一重佈局層與該第二重佈局層。
  4. 如請求項1所述之多元件封裝體，其中該第一重佈局層與該第二重佈局層包含：複數個金屬層，該些金屬層於一介電層中呈平行排列；以及複數個導電柱，且該些導電柱電性連接該些金屬層中 的相鄰兩層。
  5. 如請求項1所述之多元件封裝體，其中該封膠層包含環氧樹脂。
  6. 一種多元件封裝體，包含：至少兩個元件區域設置於一基板中；一第一重佈局層設置於該基板上；一外部晶片設置於該第一重佈局層上；一第二重佈局層設置於該第一重佈局層上；以及一封膠層設置於該第一重佈局層與該第二重佈局層之間，該封膠層包含：一第一導電接觸通過該封膠層；以及一第二導電接觸通過該封膠層與該外部晶片，且該第一導電接觸與該第二導電接觸連接該第一重佈局層與該第二重佈局層。
  7. 一種多元件封裝體的製備方法，包含：形成一第一重佈局層於一晶圓上，該晶圓具有至少兩個元件區域，且該第一重佈局層電性連接至該兩個元件區域；形成複數個第一連接件於該第一重佈局層上；配置一外部晶片於該些第一連接件上，以令使該外部晶片藉由該些第一連接件電性連接至該第一重佈局層；形成複數個第二連接件於該第一重佈局層上，且該第 二連接件之一直徑大於該第一連接件之一直徑與該外部晶片之一厚度的總和；形成一暫時黏著層覆蓋該第二連接件與該外部晶片；薄化該晶圓；以及移除該暫時黏著層。
  8. 如請求項7所述之多元件封裝體的製備方法，更包含：沿著一切割道切割該晶圓以形成該多元件封裝體。
  9. 一種多元件封裝體的製備方法，包含：形成一第一重佈局層於一晶圓上，該晶圓具有至少兩個元件區域，且該第一重佈局層電性連接至該兩個元件區域；形成複數個第一連接件於該第一重佈局層上；以及配置一外部晶片於該些第一連接件上，以令使該外部晶片藉由該些第一連接件電性連接至該第一重佈局層，其中該外部晶片具有一第一穿孔。
  10. 如請求項9所述之多元件封裝體的製備方法，更包含：形成一封膠層覆蓋該第一重佈局層與該外部晶片；移除部分的該封膠層以形成一第二穿孔與一第三穿孔，該第二穿孔暴露該第一重佈局層，而該第三穿孔貫通該第一穿孔以暴露該第一重佈局層；以及 填充一導電材料至該第一穿孔、該第二穿孔與該第三穿孔中以形成一第一導電接觸與一第二導電接觸。
  11. 如請求項10所述之多元件封裝體的製備方法，更包含：形成一第二重佈局層於該封膠層上，且該第二重佈局層電性連接至該第一導電接觸與該第二導電接觸；以及形成複數個第三連接件於該第二重佈局層上。
  12. 如請求項11所述之多元件封裝體的製備方法，更包含：形成一暫時黏著層覆蓋該第三連接件與該第二重佈局層；薄化該晶圓；以及移除該暫時黏著層。
  13. 如請求項12所述之多元件封裝體的製備方法，更包含：沿著一切割道切割該晶圓以形成該多元件封裝體。
  14. 如請求項9所述之多元件封裝體的製備方法，其中形成該第一重佈局層於該晶圓上包含：沉積一介電材料覆蓋該晶圓；移除部分的該介電材料以形成複數個開口暴露該晶圓中的該些元件區域； 形成複數個導電柱於該些開口中；形成一金屬層於該些導電柱上；以及圖案化該金屬層。
  15. 如請求項11所述之多元件封裝體的製備方法，其中形成該第二重佈局層於該晶圓上包含：沉積一介電材料覆蓋該封膠層；移除部分的該介電材料以形成複數個開口暴露該第一導電接觸與該第二導電接觸；形成複數個導電柱於該些開口中；形成一金屬層於該些導電柱上；以及圖案化該金屬層。
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