CN109037089B - 重布线层的测试方法 - Google Patents

重布线层的测试方法 Download PDF

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CN109037089B
CN109037089B CN201710680991.6A CN201710680991A CN109037089B CN 109037089 B CN109037089 B CN 109037089B CN 201710680991 A CN201710680991 A CN 201710680991A CN 109037089 B CN109037089 B CN 109037089B
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redistribution layer
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CN109037089A (zh
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林汉文
徐宏欣
张简上煜
林南君
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Abstract

本发明公开一种重布线层的测试方法，导电层成形于第一载体的第一表面上，重布线层成形于导电层上，然后于重布线层上执行断路测试，由于导电层与重布线层构成一封闭的回路，故若重布线层成形正确，则断路测试时将会有负载呈现，于断路测试执行完毕后，将第一载体与导电层移除，并于重布线层上执行一短路测试，由于重布线层本身为一开启的回路，故若重布线层成形正确，则短路测试时将不会有负载呈现，因此可在芯片结合于重布线层之前确定重布线层是否具有缺陷，则将不会因为重布线层的缺陷而浪费良好的芯片。

Description

重布线层的测试方法
技术领域
本发明涉及一种在半导体装置工艺中的测试方法，尤其涉及一种测试重布线层的方法。
背景技术
基于可携式电子装置的广泛使用，可携式电子装置中所需要内建的功能越来越多，市场上所需的电子装置不仅要效能佳，还需要轻薄短小，为了满足市场需求，采用一种新的制法是将重布线层(redistribution layer，RDL)直接施加在硅芯片和有机化合物的组合物的表面，重布线层是由金属线及通孔所组成的层状物，其提供用以自芯片的接脚传送电力或信号至封装体外部的路径，一般而言，积体电路装置需要高I/O数来实现高性能。然而，对于固定的芯片尺寸来说，芯片的面积可能不足以提供空间给大量的I/O数使用，此问题可通过重布线层加以解决，同时，由于缩短了传送路径，故性能预计会更好、且耗能更低。
有几种方法可以执行该种技术，其中一种为所谓的「后芯片(chip-last)」工艺，后芯片封装的工艺顺序，先将重布线层成形在载体上，再将芯片结合于重布线层上。在后芯片工艺中，由于电路的不完整性，在芯片结合之前无法确定重布线层的电性，因此，若良好的芯片结合于有缺陷的重布线层上，则会浪费该良好的芯片，因而导致产量损失并增加生产成本。基于有缺陷的重布线层只能在芯片结合于其上后加以确定，所以在不清楚其品质的前提下，将良好的芯片结合在重布线层上是具有风险的。
发明内容
有鉴于此，本发明的目的在于系针对工艺中无法在结合芯片前获知重布线层的电性进行改良。
为达到上述的发明目的，本发明所采用的手段为创作一种重布线层的测试方法，其中包括：
成形一导电层于一第一载体上；
成形一重布线层于该导电层上；
于该重布线层上执行一断路测试；
执行一转移结合工艺，以移除该第一载体及该导电层，并将该重布线层转移至一第二载体上；
于该重布线层上执行一短路测试。
本发明所采用的另一手段为创作一种重布线层的测试方法，其中包括：
成形一导电层于一第一载体上；
成形一重布线层于该导电层上；
于该重布线层上执行一断路测试；
成形一后续重布线层于先前的重布线层上；
于该后续重布线层上执行一断路测试；
判断是否要成形下一接续重布线层，若是，则回到成形一后续重布线层的步骤，若否，则执行一转移结合工艺以移除该第一载体与该导电层；
对前述步骤成形的所有重布线层执行一短路测试。
本发明的优点在于，通过导电层与重布线层所构成的封闭回路，可在芯片未结合前先测试重布线层的电性，则确保后续使用良好的重布线层与芯片相结合，以避免将良好的芯片结合于损坏的重布线层上，而浪费良好的芯片。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图说明
图1为本发明的第一实施例流程图；
图2为本发明的成形导电层时的流程图；
图3A至3B、4及5为本发明的各步骤进行时的结构剖面图；
图6为本发明在测试后续重布线层时的结构剖面图；
图7A至7B及8为本发明的各步骤进行时的结构剖面图；
图9为本发明的第二实施例流程图。
其中，附图标记
10导电层 20第一载体
201第一表面 30黏着层
40重布线层 41、42子层
50测试工具 60第二载体
61辅助黏着层
具体实施方式
以下配合附图及本发明的实施例，进一步阐述本发明为达成预定发明目的所采取的技术手段，其中附图已被简化以仅为了说明目的，而通过描述本发明的元件和组件之间的关系来说明本发明的结构或方法发明，因此，图中所示的元件不以实际数量、实际形状、实际尺寸以及实际比例呈现，尺寸或尺寸比例已被放大或简化，藉此提供更好的说明，已选择性地设计和配置实际数量、实际形状或实际尺寸比例，而详细的元件布局可能更复杂。
请参阅图1所示，本发明的重布线层的测试方法包含以下步骤：成形一导电层于一第一载体上(S1)、成形一重布线层于该导电层上(S2)、于该重布线层上执行一断路测试(S3)、执行一转移结合(transfer bonding)工艺(S4)、于该重布线层上执行一短路测试(S5)。
请参阅图1、2及3A至3B所示，导电层成形于第一载体20上(S1)可包含以下步骤，但不限于此：
施以一黏着层30于该第一载体20上(S11)(如图3A所示)：将一黏着层30施加于该第一载体20的第一表面201上。
成形导电层10于黏着层30上(S12)(如图3B所示)：将导电层10成形于黏着层30上。在一实施例中，所述导电层10沉积于黏着层30上。在一实施例中，所述导电层10为金属所制，如钛(titanium，Ti)、钛钨(titanium-tungsten，TiW)、钛铜(titanium-copper，TiCu)、或其他可做为黏着或晶种层的金属。
请参阅图1及图4所示，当导电层10成形于第一载体20上之后，将重布线层40成形于导电层10上(S2)，重布线层40可藉由溅镀(sputtering)、图案化蚀刻(patternedetching)、图案化电镀(patterned electrical plating)、或掀离(lift-off)工艺来加以成形之。
请参阅图1及图5所示，当重布线层40成形于导电层10上之后，于重布线层40上执行断路测试(S3)，重布线层40电连接于一测试工具50，藉以于重布线层40执行断路测试。
由于测试工具50与重布线层40构成一封闭的回路，故若重布线层40正确设置，则在断路测试过程中将会呈现有负载的状态。
请进一步参阅图6所示，重布线层40可包含多个子层41、42，可在每一子层41、42成形后均执行断路测试及短路测试，藉此可在每一子层41、42成形后确认每一子层41、42的品质。
请参阅图1、7A及7B所示，当执行完断路测试后，藉由转移结合工艺来将导电层10移除(S4)，将重布线层40结合于一第二载体60上并移除导电层10及第一载体20，施以具有辅助黏着层61的第二载体60于重布线层40的第一表面上，其中重布线层40的第二表面与第一表面位于相异侧，再将第一载体20及导电层10移除以使重布线层40的第二表面外露，因此，重布线层40的第二表面可用以在后续的工艺中与芯片结合。在一实施例中，在第一载体20被分离后，导电层10可单独藉由蚀刻(etching)、抛光(polishing)、或研磨(grinding)等工艺加以移除；在另一实施例中，第一载体20与导电层10可同时通过研磨工艺加以移除。研磨工艺亦可用来确保当第一载体20与导电层10被移除后的表面平整度。
请参阅图1及图8所示，当执行完转移结合工艺后，于重布线层40上执行一短路测试(S5)，重布线层40电连接于一测试工具50，藉以于重布线层40执行短路测试。由于测试工具50与重布线层40构成一开启的回路，故若重布线层40设置正确，则在短路测试过程中将无负载呈现。
因此，在重布线层40上执行断路测试及短路测试之后，可确定重布线层40是否正确设置或具有缺陷。进一步而言，由于断路测试及短路测试分别于重布线层40上全面执行，故可在与芯片结合前确保重布线层40的整体的品质。
请参阅图9所示，本发明的重布线层的测试方法的另一实施例包含以下步骤：成形一导电层于一第一载体上(S41)；成形一重布线层于该导电层上(S42)；于该重布线层上执行一断路测试(S43)；成形一后续重布线层于先前的重布线层上(S44)；于该接续重布线层上执行一断路测试(S45)；判断是否要成形下一接续重布线层(S46)；若是，则回到步骤S44；若否，则执行一转移结合工艺(S47)以移除第一载体及导电层；对重布线层执行一短路测试(S48)。因此，当设置多个重布线层时，针对每一层重布线层均进行断路测试，以确定每一重布线层的品质。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims (10)

1.一种重布线层的测试方法，其特征在于，包括：
成形一导电层于一第一载体上；
成形一重布线层于该导电层上；
于该重布线层上执行一断路测试；
执行一转移结合工艺，以移除该第一载体及该导电层，并将该重布线层转移至一第二载体上；
于该重布线层上执行一短路测试。
2.根据权利要求1所述的重布线层的测试方法，其特征在于，成形导电层的步骤包含以下步骤：
施以一黏着层于该第一载体的第一表面；
成形该导电层于该黏着层上。
3.根据权利要求1或2所述的重布线层的测试方法，其特征在于，于执行转移结合工艺步骤中，在该第一载体被分离后，导电层单独藉由蚀刻、抛光、或研磨工艺加以移除。
4.根据权利要求3所述的重布线层的测试方法，其特征在于，该重布线层包含有多个子层，且于每一子层成形后均执行断路测试。
5.根据权利要求1或2所述的重布线层的测试方法，其特征在于，于执行转移结合工艺步骤中，该第一载体与该导电层同时通过研磨工艺加以移除。
6.根据权利要求5所述的重布线层的测试方法，其特征在于，该重布线层包含有多个子层，且于每一子层成形后均执行断路测试。
7.根据权利要求1或2所述的重布线层的测试方法，其特征在于，该重布线层包含有多个子层，且于每一子层成形后均执行断路测试。
8.一种重布线层的测试方法，其特征在于，包括：
成形一导电层于一第一载体上；
成形一重布线层于该导电层上；
于该重布线层上执行一断路测试；
成形一后续重布线层于先前的重布线层上；
于该后续重布线层上执行一断路测试；
判断是否要成形下一接续重布线层，若是，则回到成形一后续重布线层的步骤，若否，则执行一转移结合工艺以移除该第一载体与该导电层；
对前述步骤成形的所有重布线层执行一短路测试。
9.根据权利要求8所述的重布线层的测试方法，其特征在于，成形导电层的步骤包含以下步骤：
施以一黏着层于该第一载体的第一表面；
成形该导电层于该黏着层上。
10.根据权利要求8所述的重布线层的测试方法，其特征在于，于执行转移结合工艺步骤中，在该第一载体被分离后，导电层单独藉由蚀刻、抛光、或研磨工艺加以移除。
CN201710680991.6A 2017-06-12 2017-08-10 重布线层的测试方法 Expired - Fee Related CN109037089B (zh)

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