TWI656585B - 重佈線層的測試方法 - Google Patents
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- 238000010998 test method Methods 0.000 title claims description 10
- 238000012360 testing method Methods 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000010410 layer Substances 0.000 claims description 148
- 239000012790 adhesive layer Substances 0.000 claims description 12
- 238000007517 polishing process Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 4
- 239000002699 waste material Substances 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910010165 TiCu Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
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Abstract
本發明為一種重佈線層的測試方法，導電層成形於第一載體之第一表面上，重佈線層成形於導電層上，然後於重佈線層上執行斷路測試，由於導電層與重佈線層構成一封閉的迴路，故若重佈線層成形正確，則斷路測試時將會有負載呈現，於斷路測試執行完畢後，將第一載體與導電層移除，並於重佈線層上執行一短路測試，由於重佈線層本身為一開啟的迴路，故若重佈線層成形正確，則短路測試時將不會有負載呈現，因此可在晶粒結合於重佈線層之前確定重佈線層是否具有缺陷，則將不會因為重佈線層之缺陷而浪費良好的晶粒。
Description
本發明為一種在半導體裝置製程中的測試方法，尤指一種測試重佈線層的方法。
基於可攜式電子裝置的廣泛使用，可攜式電子裝置中所需要內建的功能越來越多，市場上所需的電子裝置不僅要效能佳，還需要輕薄短小，為了滿足市場需求，採用一種新的製法係將重佈線層（redistribution layer，RDL）直接施加在矽晶粒和有機化合物之組合物的表面，重佈線層係由金屬線及通孔所組成的層狀物，其提供用以自晶粒的接腳傳送電力或訊號至封裝體外部的路徑，一般而言，積體電路裝置需要高I/O數來實現高性能。然而，對於固定的晶粒尺寸來說，晶粒的面積可能不足以提供空間給大量的I/O數使用，此問題可透過重佈線層加以解決，同時，由於縮短了傳送路徑，故性能預計會更好、且耗能更低。
有幾種方法可以執行該種技術，其中一種為所謂的「後晶片（chip-last）」製程，後晶片封裝之製程順序，係先將重佈線層成形在載體上，再將晶粒結合於重佈線層上。在後晶片製程中，由於電路的不完整性，在晶粒結合之前無法確定重佈線層的電性，因此，若良好的晶粒結合於有缺陷的重佈線層上，則會浪費該良好的晶粒，因而導致產量損失並增加生產成本。基於有缺陷的重佈線層只能在晶粒結合於其上後加以確定，所以在不清楚其品質的前提下，將良好的晶粒結合在重佈線層上是具有風險的。
有鑑於此，本發明係針對製程中無法在結合晶片前獲知重佈線層之電性進行改良。
為達到上述之發明目的，本發明所採用的手段為創作一種重佈線層的測試方法，其中包括： 成形一導電層於一第一載體上； 成形一重佈線層於該導電層上； 於該重佈線層上執行一斷路測試； 執行一轉移結合製程，以移除該第一載體及該導電層，並將該重佈線層轉移至一第二載體上； 於該重佈線層上執行一短路測試。
本發明所採用的另一手段為創作一種重佈線層的測試方法，其中包括： 成形一導電層於一第一載體上； 成形一重佈線層於該導電層上； 於該重佈線層上執行一斷路測試； 成形一後續重佈線層於先前的重佈線層上； 於該後續重佈線層上執行一斷路測試； 判斷是否要成形下一接續重佈線層，若是，則回到成形一後續重佈線層之步驟，若否，則執行一轉移結合製程以移除該第一載體與該導電層； 於所述重佈線層上執行一短路測試。
本發明的優點在於，透過導電層與重佈線層所構成的封閉迴路，可在晶粒未結合前先測試重佈線層之電性，則確保後續係使用良好的重佈線層與晶粒相結合，以避免將良好的晶粒結合於損壞的重佈線層上，而浪費良好的晶粒。
以下配合圖式及本發明之實施例，進一步闡述本發明為達成預定發明目的所採取的技術手段，其中圖式已被簡化以僅為了說明目的，而通過描述本發明的元件和組件之間的關係來說明本發明的結構或方法 發明，因此，圖中所示的元件不以實際數量、實際形狀、實際尺寸以及實際比例呈現，尺寸或尺寸比例已被放大或簡化，藉此提供更好的說明，已選擇性地設計和配置實際數量、實際形狀或實際尺寸比例，而詳細的元件佈局可能更複雜。
請參閱圖1所示，本發明之重佈線層的測試方法包含以下步驟：成形一導電層於一第一載體上（S1）、成形一重佈線層於該導電層上（S2）、於該重佈線層上執行一斷路測試（S3）、執行一轉移結合（transfer bonding）製程（S4）、於該重佈線層上執行一短路測試（S5）。
請參閱圖1、2及3A至3B所示，導電層成形於第一載體20上（S1）可包含以下步驟，但不限於此：
施以一黏著層30於該第一載體20上（S11）（如圖3A所示）：將一黏著層30施加於該第一載體20之第一表面201上。
成形導電層10於黏著層30上（S12）（如圖3B所示）：將導電層10成形於黏著層30上。在一實施例中，所述導電層10係沉積於黏著層30上。在一實施例中，所述導電層10為金屬所製，如鈦（titanium，Ti）、鈦鎢（titanium-tungsten，TiW）、鈦銅（titanium-copper，TiCu）、或其他可做為黏著或晶種層的金屬。
請參閱圖1及圖4所示，當導電層10成形於第一載體20上之後，將重佈線層40成形於導電層10上（S2），重佈線層40可藉由濺鍍（sputtering）、圖案化蝕刻（patterned etching）、圖案化電鍍（patterned electrical plating）、或掀離（lift-off）製程來加以成形之。
請參閱圖1及圖5所示，當重佈線層40成形於導電層10上之後，於重佈線層40上執行斷路測試（S3），重佈線層40電連接於一測試工具50，藉以於重佈線層40執行斷路測試。
由於測試工具50與重佈線層40構成一封閉的迴路，故若重佈線層40正確設置，則在斷路測試過程中將會呈現有負載的狀態。
請進一步參閱圖6所示，重佈線層40可包含多個子層41、42，可在每一子層41、42成形後均執行斷路測試及短路測試，藉此可在每一子層41、42成形後確認每一子層41、42的品質。
請參閱圖1、7A及7B所示，當執行完斷路測試後，藉由轉移結合製程來將導電層10移除（S4），將重佈線層40結合於一第二載體60上並移除導電層10及第一載體20，施以具有輔助黏著層61的第二載體60於重佈線層40的第一表面上，其中重佈線層40之第二表面與第一表面位於相異側，再將第一載體20及導電層10移除以使重佈線層40的第二表面外露，因此，重佈線層40的第二表面可用以在後續的製程中與晶粒結合。在一實施例中，在第一載體20被分離後，導電層10可單獨藉由蝕刻（etching）、拋光（polishing）、或研磨（grinding）等製程加以移除；在另一實施例中，第一載體20與導電層10可同時透過研磨製程加以移除。研磨製程亦可用來確保當第一載體20與導電層10被移除後的表面平整度。
請參閱圖1及圖8所示，當執行完轉移結合製程後，於重佈線層40上執行一短路測試（S5），重佈線層40電連接於一測試工具50，藉以於重佈線層40執行短路測試。由於測試工具50與重佈線層40構成一開啟的迴路，故若重佈線層40設置正確，則在短路測試過程中將不會無負載呈現。
因此，在重佈線層40上執行斷路測試及短路測試之後，可確定重佈線層40是否正確設置或具有缺陷。進一步而言，由於斷路測試及短路測試分別於重佈線層40上全面執行，故可在與晶粒結合前確保重佈線層40之整體的品質。
請參閱圖9所示，本發明之重佈線層的測試方法的另一實施例包含以下步驟：成形一導電層於一第一載體上（S41）；成形一重佈線層於該導電層上（S42）；於該重佈線層上執行一斷路測試（S43）；成形一後續重佈線層於先前的重佈線層上（S44）；於該接續重佈線層上執行一斷路測試（S45）；判斷是否要成形下一接續重佈線層（S46）；若是，則回到步驟S44；若否，則執行一轉移結合製程（S47）以移除第一載體及導電層；於該重佈線層上執行一短路測試（S48）。因此，當設置多個重佈線層時，係針對每一層重佈線層均進行斷路測試，以確定每一重佈線層的品質。
以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。
10‧‧‧導電層
20‧‧‧第一載體
201‧‧‧第一表面
30‧‧‧黏著層
40‧‧‧重佈線層
41、42‧‧‧子層
50‧‧‧測試工具
60‧‧‧第二載體
61‧‧‧輔助黏著層
圖1為本發明之第一實施例流程圖。 圖2為本發明之成形導電層時的流程圖。 圖3A至3B、4及5為本發明之各步驟進行時之結構剖面圖。 圖6為本發明在測試後續重佈線層時之結構剖面圖。 圖7A至7B及8為本發明之各步驟進行時之結構剖面圖。 圖9為本發明之第二實施例流程圖。
Claims (10)
- 一種重佈線層的測試方法，其中包括： 成形一導電層於一第一載體上； 成形一重佈線層於該導電層上； 於該重佈線層上執行一斷路測試； 執行一轉移結合製程，以移除該第一載體及該導電層，並將該重佈線層轉移至一第二載體上； 於該重佈線層上執行一短路測試。
- 如請求項1所述之重佈線層的測試方法，其中成形導電層之步驟包含以下步驟： 施以一黏著層於該第一載體之第一表面； 成形該導電層於該黏著層上。
- 如請求項1或2所述之重佈線層的測試方法，其中於執行轉移結合製程步驟中，在該第一載體被分離後，導電層單獨藉由蝕刻、拋光、或研磨製程加以移除。
- 如請求項3所述之重佈線層的測試方法，其中該重佈線層包含有多數個子層，且係於每一子層成形後均執行斷路測試。
- 如請求項1或2所述之重佈線層的測試方法，其中於執行轉移結合製程步驟中，該第一載體與該導電層同時透過研磨製程加以移除。
- 如請求項5所述之重佈線層的測試方法，其中該重佈線層包含有多數個子層，且係於每一子層成形後均執行斷路測試。
- 如請求項1或2所述之重佈線層的測試方法，其中該重佈線層包含有多數個子層，且係於每一子層成形後均執行斷路測試。
- 一種重佈線層的測試方法，其中包括： 成形一導電層於一第一載體上； 成形一重佈線層於該導電層上； 於該重佈線層上執行一斷路測試； 成形一後續重佈線層於先前的重佈線層上； 於該後續重佈線層上執行一斷路測試； 判斷是否要成形下一接續重佈線層，若是，則回到成形一後續重佈線層之步驟，若否，則執行一轉移結合製程以移除該第一載體與該導電層； 於所述重佈線層上執行一短路測試。
- 如請求項8所述之重佈線層的測試方法，其中成形導電層之步驟包含以下步驟： 施以一黏著層於該第一載體之第一表面； 成形該導電層於該黏著層上。
- 如請求項8所述之重佈線層的測試方法，其中於執行轉移結合製程步驟中，在該第一載體被分離後，導電層單獨藉由蝕刻、拋光、或研磨製程加以移除。
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| US15/619,969 US10079218B1 (en) | 2017-06-12 | 2017-06-12 | Test method for a redistribution layer |
| US15/619,969 | 2017-06-12 |
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| KR20210128483A (ko) * | 2019-02-28 | 2021-10-26 | 엑소 이미징, 인크. | 고밀도 다극성 박막 압전 디바이스 및 그 제조 방법 |
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| TW201903923A (zh) | 2019-01-16 |
| CN109037089A (zh) | 2018-12-18 |
| CN109037089B (zh) | 2020-09-15 |
| US10079218B1 (en) | 2018-09-18 |
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