TW202114089A - 封裝結構及其製作方法 - Google Patents

封裝結構及其製作方法 Download PDF

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TW202114089A
TW202114089A TW109132361A TW109132361A TW202114089A TW 202114089 A TW202114089 A TW 202114089A TW 109132361 A TW109132361 A TW 109132361A TW 109132361 A TW109132361 A TW 109132361A TW 202114089 A TW202114089 A TW 202114089A
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Taiwan
Prior art keywords
semiconductor die
bonding
layer
semiconductor
supporting substrate
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TW109132361A
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English (en)
Inventor
陳明發
吳念芳
葉松峯
劉醇鴻
史朝文
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台灣積體電路製造股份有限公司
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Priority claimed from US16/896,219 external-priority patent/US11322477B2/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202114089A publication Critical patent/TW202114089A/zh

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Abstract

一種包括堆疊基材、第一半導體晶粒、第二半導體晶粒及絕緣包封體的封裝結構。所述第一半導體晶粒設置在所述堆疊基材之上。所述第二半導體晶粒堆疊在所述第一半導體晶粒之上。所述絕緣包封體包括包封所述第一半導體晶粒的第一包封體部分及包封所述第二半導體晶粒的第二包封體部分。

Description

封裝結構及其製作方法
本發明是有關於一種封裝結構及其製作方法。
由於各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的集成密度的持續提高，半導體行業已經歷快速增長。在很大程度上，集成密度的這一提高是源自最小特徵大小（minimum feature size）的持續減小，此使更多的組件能夠集成到給定的面積中。隨著近來對小型化、較高的速度、較大的頻寬、較低的功率損耗及較少的延遲的需求的增加，對更小且更具創造性的半導體晶粒封裝技術的需要也隨著增加。目前，系統集成晶片（System-on-Integrated-Chip，SoIC）元件因其多功能及緊湊性而越來越受歡迎。然而，與SoIC元件相關的封裝製程存在有許多挑戰。
根據本公開的一些實施例，提供一種包括堆疊基材、第一半導體晶粒、第二半導體晶粒及絕緣包封體的結構。所述第一半導體晶粒設置在所述堆疊基材之上。所述第二半導體晶粒堆疊在所述第一半導體晶粒之上。所述絕緣包封體包括包封所述第一半導體晶粒的第一包封體部分及包封所述第二半導體晶粒的第二包封體部分。
根據本公開的一些其他實施例，提供一種包括支撐基材、第一半導體晶粒、第二半導體晶粒、金屬層及絕緣包封體的結構。所述第一半導體晶粒設置在所述支撐基材的第一表面之上。所述第二半導體晶粒設置在所述第一半導體晶粒之上。所述金屬層設置在所述支撐基材的第二表面之上，且所述第一表面與所述第二表面相對。所述絕緣包封體包括包封所述第一半導體晶粒的第一包封體部分及包封所述第二半導體晶粒的第二包封體部分。
根據本公開的一些其他實施例，提供一種包括以下步驟的方法。將第一半導體晶粒結合到載體，其中所述第一半導體晶粒彼此間隔開，且所述第一半導體晶粒的前表面面對所述載體。在所述載體之上形成第一包封體部分，以在側向上包封所述第一半導體晶粒。從所述第一半導體晶粒的所述前表面及所述第一包封體部分移除所述載體。在所述第一半導體晶粒的所述前表面及所述第一包封體部分上形成結合層。將第二半導體晶粒結合到所述結合層，其中所述第二半導體晶粒的前表面面對所述結合層。在所述結合層之上形成第二包封體部分，以在側向上包封所述第二半導體晶粒。在所述載體之上形成所述第一包封體部分以在側向上包封所述第一半導體晶粒之後，將支撐基材結合到所述第一半導體晶粒的後表面及所述第一包封體部分。
以下公開內容提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下描述元件及設置形式的具體實例以簡化本公開。當然，這些僅為實例且非旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開可能在各種實例中重複使用參考編號和/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例和/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“之下（beneath）”、“下方（below）”、“下部的（lower）”、“之上（above）”、“上部的（upper）”等空間相對性用語來描述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或其他取向），且本文中所用的空間相對性描述語可同樣相應地進行解釋。
也可包括其他特徵及製程。舉例來說，可包括測試結構以説明對三維（three-dimensional，3D）封裝或三維積體電路（three-dimensional integrated circuit，3DIC）裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基材上形成的測試焊墊（test pad），以便能夠對3D封裝或3DIC進行測試、對探針和/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，可將本文中所公開的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用，以提高良率並降低成本。
圖1到圖10是示意性示出根據本公開一些實施例製作SoIC元件的製程剖視圖。
參照圖1，提供半導體載體C1，而半導體載體C1包括形成在其表面上的結合層B。半導體載體C1可以是半導體晶圓，並且結合層B可以是準備進行熔融結合（fusion bond）的結合層。在一些實施例中，結合層B是在半導體載體C1的頂表面之上形成的沉積層。在一些替代實施例中，結合層B是用於熔融結合的半導體載體C1的一部分。舉例來說，半導體載體C1的材料包括矽（Si）或其他合適的半導體材料，並且結合層B的材料包括矽（Si）、二氧化矽（SiO2 ）或其他合適的結合材料。在一些其他實施例中，結合層B是在半導體載體C1的表面上自然生長的天然氧化物層。
提供半導體晶粒100（例如，邏輯晶粒）並將其放置在結合層B的頂表面上。半導體晶粒100中的每一者可分別包括主動表面100a（即，前表面）及與主動表面100a相對的後表面100b。半導體晶粒100中的每一者可分別包括結合部分102。將半導體晶粒100放置在結合層B的頂表面上，使得半導體晶粒100的主動表面100a面對結合層B，並且半導體晶粒100的結合部分102與結合層B的頂表面接觸。半導體晶粒100可以並排的方式放置在結合層B上，使得半導體晶粒100彼此間隔開。在一些實施例中，結合部分102的材料包括矽（Si）、二氧化矽（SiO2 ）或其他合適的結合材料。
在拾取半導體晶粒100並將其放置在結合層B上之後，可執行晶圓到晶圓的熔融結合製程，使得在結合層B與半導體晶粒100的結合部分102之間形成熔融結合介面。舉例來說，用於結合結合層B與半導體晶粒100的結合部分102的熔融結合製程是在介於從約250攝氏度到約400攝氏度範圍內的溫度下執行的。結合層B可直接結合到半導體晶粒100的結合部分102。換句話說，在結合層B與半導體晶粒100的結合部分102之間沒有形成中間層。在結合層B與半導體晶粒100的結合部分102之間形成的上述熔融結合介面可以是或可包括Si-Si熔融結合介面、Si-SiO2 熔融結合介面、SiO2 -SiO2 熔融結合介面或其他合適的熔融結合介面。
參照圖1及圖2，在將半導體晶粒100結合到結合層B之後，形成絕緣材料以覆蓋結合層B及半導體晶粒100。在一些實施例中，絕緣材料通過包覆模塑製程（over-molding process）形成，使得半導體晶粒100（在圖1中示出）的後表面100b及側表面被絕緣材料覆蓋。在執行包覆模塑製程之後，可執行研磨製程以減小絕緣材料的厚度及半導體晶粒100（在圖1中示出）的厚度，使得具有減小的厚度的半導體晶粒100’及第一包封體部分110形成在結合層B之上。在一些實施例中，用於減小絕緣材料的厚度及半導體晶粒100（在圖1中示出）的厚度的研磨製程包括機械研磨製程、化學機械研磨（chemical mechanical polishing，CMP）製程或其組合。
如圖2所示，在一些實施例中，半導體晶粒100’的厚度等於第一包封體部分110的厚度，並且半導體晶粒100’在側向上被第一包封體部分110包封。換句話說，第一包封體部分110僅與半導體晶粒100’的側表面接觸，並且半導體晶粒100’的後表面100b’被第一包封體部分110以可被暴露出。在圖2中未示出的一些替代實施例中，由於研磨製程的研磨選擇性，半導體晶粒的厚度略小於或略大於第一包封體部分的厚度。換句話說，第一包封體部分的頂表面可略高於或略低於半導體晶粒的後表面。
參照圖3，在一些實施例中，在半導體晶粒100’的後表面100b’之上形成對準標記120。在一些替代實施例中，在第一包封體部分的頂表面之上形成對準標記。對準標記120的數量、形狀及位置在本發明中不受限制。對準標記120可通過沉積、微影及蝕刻製程形成。在一些實施例中，在半導體晶粒100’的後表面100b’及第一包封體部分110的頂表面之上沉積金屬材料，且然後通過例如微影製程、隨後進行蝕刻製程將沉積的金屬材料圖案化。
在形成對準標記120之後，可在半導體晶粒100’的後表面100b’及第一包封體部分110的頂表面之上形成結合層130，使得對準標記120被結合層130覆蓋。可通過化學氣相沉積（chemical vapor deposition，CVD）製程或其他合適的沉積製程形成結合層130。結合層130可以是準備進行熔融結合的結合層，並且結合層130的材料可包括矽（Si）、二氧化矽（SiO2 ）或其他合適的結合材料。在一些實施例中，結合層130具有平坦的頂表面。
參照圖4，在形成對準標記120及結合層130之後，提供用於翹曲控制的支撐基材140，並將其放置在結合層130之上。使用對準標記120使支撐基材140與圖3所示的所得結構對準。支撐基材140的厚度可介於從約750微米到約800微米的範圍內。舉例來說，如圖4所示，支撐基材140是半導體晶圓（例如，矽晶圓），並且支撐基材140的厚度是約775微米。在一些實施例中，執行晶圓到晶圓的熔融結合製程（wafer-to-wafer fusion bonding process），使得在支撐基材140與結合層130之間形成熔融結合介面。舉例來說，用於結合支撐基材140與結合層130的熔融結合製程是在介於從約250攝氏度到約400攝氏度範圍內的溫度下執行的。支撐基材140可直接結合到結合層130。換句話說，在支撐基材140與結合層130之間沒有形成中間層。在圖4未示出的一些替代實施例中，支撐基材是上面形成有介電結合層（例如，SiO2層）的半導體晶圓（例如，矽晶圓）。此外，形成在支撐基材140與結合層130之間的熔融結合介面可以是Si-Si熔融結合介面、Si-SiO2 熔融結合介面、SiO2 -SiO2 熔融結合介面或其他合適的熔融結合介面。
參照圖4及圖5，在結合支撐基材140與結合層130之後，可執行剝離或移除製程，使得結合層B及半導體載體C1從半導體晶粒100’及第一包封體部分110剝離。剝離製程可以是雷射掀離製程（laser lift-off process）或其他合適的移除製程。在移除結合層B及半導體載體C1之後，半導體晶粒100’的主動表面100a及第一包封體部分110的表面被露出。
在移除結合層B及半導體載體C1之後，將從結合層B及半導體載體C1剝離的結構上下翻轉，使得半導體晶粒100’的主動表面100a及第一包封體部分110的露出的表面可面向上。然後，在半導體晶粒100’的主動表面100a及第一包封體部分110的露出的表面之上形成結合結構150。結合結構150可包括介電層150a及導體150b，每個導體150b穿透介電層150a。介電層150a的材料可以是氧化矽（SiOx，其中x＞0）、氮化矽（SiNx，其中x＞0）、氮氧化矽（SiOxNy，其中x＞0且y＞0）或其他合適的介電材料，並且導體150b可以是導通孔（例如，銅通孔）、導電焊墊（例如，銅焊墊）或其組合。可通過以下方式來形成結合層150：通過化學氣相沉積（CVD）製程（例如，電漿增強CVD製程或其他合適的沉積製程）沉積介電材料；圖案化介電材料以形成包括開口或穿孔的介電層150a；以及在介電層150a中界定的開口或穿孔中填充導電材料，以形成嵌入介電層150a中的導體150b。
參照圖6，提供半導體晶粒160（例如，記憶體晶粒），並將其放置在結合結構150的一些部分上。在一些實施例中，半導體晶粒160中的每一者分別放置在半導體晶粒100中的一者之上。半導體晶粒160中的每一者可包括半導體基材162、設置在半導體基材162上的內連結構164、設置在內連結構164上並電連接到內連結構164的結合結構166以及形成在半導體基材162中的半導體穿孔168。將半導體晶粒160放置在結合結構150上，使得半導體晶粒160的結合結構166與結合結構150的一些部分接觸。半導體晶粒160可以並排的方式放置在結合結構150上，使得半導體晶粒160彼此間隔開。結合結構166可包括介電層166a及導體166b，每個導體166b穿透介電層166a。介電層166a的材料可以是氧化矽（SiOx，其中x＞0）、氮化矽（SiNx，其中x＞0）、氮氧化矽（SiOxNy，其中x＞0且y＞0）或其他合適的介電材料，並且導體166b可以是導通孔（例如，銅通孔）、導電焊墊（例如，銅焊墊）或其組合。
結合結構166的導體166b與結合結構150的導體150b對準，並且可實現半導體晶粒160與結合結構150之間的次微米對準精度。一旦半導體晶粒160的結合結構166與結合結構150精確對準，便執行晶圓到晶圓的混合結合，使得半導體晶粒160混合結合到結合結構150。
在一些實施例中，為了促進結合結構150與半導體晶粒160的結合結構166之間的晶圓到晶圓的混合結合，執行結合結構166及結合結構150的結合表面的表面準備。表面準備可包括例如表面清潔及活化。可對結合結構166及結合結構150的結合表面執行表面清潔，以移除在導體150b、介電層150a、導體166b及介電層166a的結合表面上的顆粒。通過例如濕式清潔來清潔結合結構166及結合結構150的結合表面。不僅可移除顆粒，而且可移除在導體150b及導體166b的結合表面上形成的天然氧化物。可通過濕式清潔中使用的化學物質來移除在導體150b及導體166b的結合表面上形成的天然氧化物。
在清潔結合結構166及結合結構150的結合表面之後，可執行對介電層150a及介電層166a的頂表面的活化，以形成高結合強度。在一些實施例中，執行電漿活化以處理介電層150a及介電層166a的結合表面。
當介電層150a的活化結合表面與介電層166a的活化結合表面接觸時，結合結構150的介電層150a與半導體晶粒160的介電層166a被預結合。通過介電層150a與介電層166a的預結合，半導體晶粒160與結合結構150預結合。在預結合介電層150a與介電層166a之後，導體150b與導體166b接觸。
在預結合介電層150a與介電層166a之後，執行半導體晶粒160與結合結構150的混合結合。半導體晶粒160與結合結構150的混合結合可包括用於介電質結合的處理及用於導體結合的熱退火。執行用於介電質結合的處理以加強介電層150a與介電層166a之間的結合。用於介電質結合的處理可在例如介於從約100攝氏度到約150攝氏度範圍內的溫度下執行。在執行用於介電質結合的處理之後，執行用於導體結合的熱退火以促進導體150b與導體166b之間的結合。用於導體結合的熱退火可在例如介於從約300攝氏度到約400攝氏度範圍內的溫度下執行。用於導體結合的熱退火的製程溫度高於用於介電質結合的處理的製程溫度。由於用於導體結合的熱退火是在相對較高的溫度下執行的，因此在導體150b與導體166b之間的結合介面處可能發生金屬擴散及結晶生長。在執行用於導體結合的熱退火之後，介電層150a被結合到介電層166a，並且導體150b被結合到導體166b。導體150b與導體166b之間的導體結合可以是通孔到通孔的結合、焊墊到焊墊的結合或通孔到焊墊的結合。
參照圖6及圖7，在將半導體晶粒160結合到結合結構150之後，形成絕緣材料以覆蓋結合結構150及半導體晶粒160。在一些實施例中，通過包覆模塑製程形成絕緣材料，使得半導體晶粒160（在圖6中示出）的後表面及側表面被絕緣材料覆蓋。在執行包覆模塑製程之後，可執行研磨製程以減小絕緣材料的厚度及半導體晶粒160（在圖6中示出）的厚度，使得具有減小的厚度的半導體晶粒160’及第二包封體部分170形成在結合結構150之上。在執行研磨製程之後，形成具有減小的厚度的半導體基材162’，並且從半導體基材162’的後表面露出半導體穿孔168。在一些實施例中，用於減小絕緣材料的厚度及半導體晶粒160（在圖6中示出）的厚度的研磨製程包括機械研磨製程、化學機械研磨（CMP）製程或其組合。
如圖7所示，在一些實施例中，半導體晶粒160’的厚度等於第二包封體部分170的厚度，並且半導體晶粒160’在側向上被第二包封體部分170包封。換句話說，第二包封體部分170僅與半導體晶粒160’的側表面接觸，並且半導體晶粒160’的後表面通過第二包封體部分170以可被暴露出。在圖7未示出的一些替代實施例中，由於研磨製程的研磨選擇性，半導體晶粒的厚度略小於或略大於第二包封體部分的厚度。換句話說，第二包封體部分的頂表面可略高於或略低於半導體晶粒的後表面。
在第二包封體部分170中形成絕緣體穿孔（through insulator via，TIV）172。絕緣體穿孔172電連接到導體150b的未被半導體晶粒160’覆蓋的部分。第二包封體部分170可通過雷射鑽孔製程、微影製程、隨後進行蝕刻製程或其他合適的圖案化製程來圖案化，以在第二包封體部分170中形成穿孔，並且可將導電材料填充在穿孔中以形成絕緣體穿孔172。在一些實施例中，在第二包封體部分170中形成穿孔後，通過沉積導電材料、隨後進行化學機械研磨製程來形成絕緣體穿孔172。舉例來說，在半導體晶粒160’及第二包封體部分170之上沉積金屬材料（例如，銅）以填充在第二包封體部分170中界定的穿孔，且然後通過化學機械研磨製程研磨金屬材料，直到露出半導體晶粒160’及第二包封體部分170。
參照圖8，在半導體晶粒160’及第二包封體部分170的後表面上形成重佈線路層174。重佈線路層174可通過絕緣體穿孔172電連接到半導體晶粒100’。重佈線路層174可電連接到半導體晶粒160’中的半導體穿孔168。可在半導體晶粒160’及第二包封體部分170的後表面上形成鈍化層176，以覆蓋重佈線路層174。在形成重佈線路層174及鈍化層176之後，製作成結構D。
參照圖9，將結構D上下翻轉並轉移結合到半導體載體C2，使得鈍化層176與半導體載體C2接觸。在由半導體載體C2承載的結構D的支撐基材140的表面上形成結合層180。結合層180可以是準備進行熔融結合的沉積結合層。舉例來說，結合層180的材料包括二氧化矽（SiO2 ）或其他合適的結合材料。
在形成結合層180之後，提供用於翹曲控制的支撐基材182，並將其放置在結合層180上。支撐基材182的厚度可介於從約750微米到約800微米的範圍內。舉例來說，如圖9所示，支撐基材182是半導體晶圓（例如，矽晶圓），並且支撐基材182的厚度是約775微米。在一些實施例中，執行晶圓到晶圓的熔融結合製程，使得在支撐基材182與結合層180之間形成熔融結合介面。舉例來說，用於結合支撐基材182與結合層180的熔融結合製程是在介於從約250攝氏度到約300攝氏度範圍內的溫度下執行。支撐基材182可直接結合到結合層180。換句話說，在結合層180與支撐基材182之間沒有形成中間層。在圖9未示出的一些替代實施例中，支撐基材是上面形成有介電結合層（例如，SiO2 層）的半導體晶圓（例如，矽晶圓）。此外，形成在支撐基材182與結合層180之間的熔融結合介面可以是Si-SiO2 熔融結合介面、SiO2 -SiO2 熔融結合介面或其他合適的熔融結合介面。
在執行支撐基材182與結合層180的熔融結合製程之後，可在支撐基材182的表面之上形成後側金屬層184。換句話說，在堆疊基材140及182的表面之上形成後側金屬層184。舉例來說，後側金屬層184的厚度介於從約10微米到約1000微米的範圍內，以提供適當的翹曲控制能力。後側金屬層184設置在堆疊基材140及182的表面之上，半導體晶粒100’設置在堆疊基材140及182的另一表面之上。換句話說，後側金屬層184與半導體晶粒100’設置在堆疊基材140及182的相對側。在一些實施例中，後側金屬層184可包括多層結構金屬結構。舉例來說，後側金屬層184可包括形成在支撐基材182的表面上的鋁（Al）層、形成在Al層上的鈦（Ti）層、形成在Ti層上的NiV層、形成在NiV層上的Au層、形成在Au層上的銅（Cu）層以及形成在Cu層上的Ni層。Al層的厚度可以是約200微米，Ti層的厚度可以是約100微米，NiV層的厚度可以是約350微米，Au層的厚度可以是約100微米，Cu層的厚度可介於約10微米到約1000微米的範圍內；並且Ni層的厚度可介於約1微米到約30微米的範圍內。
參照圖9及圖10，在形成後側金屬層184之後，從結構D剝離半導體載體C2，使得鈍化層176被露出。通過例如微影製程、隨後進行蝕刻製程將鈍化層176圖案化，使得重佈線路層174被暴露出。形成導電端子186（例如，導電凸塊）以電連接被鈍化層176覆蓋的重佈線路層174。在形成導電端子186之後，沿著切割道SL1執行單體化製程，以獲得多個單體化的SoIC元件D1。
單體化的SoIC元件D1包括堆疊基材140及182、半導體晶粒100’、半導體晶粒160’及絕緣包封體，其中絕緣包封體包括包封半導體晶粒100’的第一包封體部分110及包封半導體晶粒160’的第二包封體部分170。半導體晶粒100’設置在堆疊基材140及182之上。半導體晶粒160’堆疊在半導體晶粒100’之上。支撐基材140可通過結合層180與支撐基材182結合，並且SoIC組件D1還可包括設置在支撐基材182的底表面上的後側金屬層284。在一些實施例中，堆疊基材140及182的總體厚度介於從約1500微米到約1600微米的範圍內，以提供適當的翹曲控制能力。如圖10所示，第一包封體部分110設置在堆疊基材140及182之上，且第二包封體部分170設置在第一包封體部分110及半導體晶粒100’之上。此外，第一包封體部分110通過位於半導體晶粒100’與半導體晶粒160’之間的結合層150與第二包封體部分170間隔開。
具有足夠總體厚度的支撐基材140及支撐基材182可用于平衡或控制SoIC組件D1的翹曲。此外，後側金屬層184可用于平衡或控制SoIC組件D1的翹曲。
圖11是示意性示出根據本公開一些替代實施例的封裝結構的剖視圖。
參照圖10及圖11，封裝結構200包括中介層202、設置在中介層202上並電連接到中介層202的SoIC元件D1、設置在中介層202上並電連接到中介層202的記憶體堆疊204、底部填充材料206、絕緣包封體208、具有導電端子212的電路基材210、導電端子220及另一底部填充材料230。中介層202可以是矽中介層。記憶體堆疊204可以是包括堆疊的高頻寬記憶體晶粒的高頻寬記憶體（high bandwidth memory，HBM）堆疊體。SoIC元件D1及記憶體堆疊204可通過由底部填充材料206包封的微凸塊電連接到中介層202。絕緣包封體208可包封SoIC組件D1、記憶體堆疊204及底部填充材料206。中介層202可通過由底部填充材料230包封的導電端子220，例如受控塌陷晶圓連接（controlled collapse chip connection，C4）凸塊，電連接到電路基材210。導電端子212可以是球柵陣列（ball grid array，BGA）導電球。
在封裝結構200中，SoIC元件D1的後側金屬層184、支撐基材140及支撐基材182不僅可控制SoIC組件D1的翹曲，還可最小化SoIC元件D1與記憶體堆疊204之間的厚度差。由於後側金屬層184、支撐基材140及支撐基材182可控制SoIC組件D1的翹曲，因此SoIC元件D1與中介層202之間的結合的良率可增加。
圖12及圖13是示意性示出根據本公開的其他實施例製作SoIC元件的製程剖視圖。
參照圖8及圖12，在執行圖8所示的製程之後，在結構D上形成導電端子186（例如，導電凸塊），使得導電端子186電連接到被鈍化層176覆蓋的重佈線路層174。
參照圖13，在形成導電端子186之後，在支撐基材140的表面之上形成後側金屬層184。舉例來說，後側金屬層184的厚度介於從約10微米到約1000微米的範圍內。後側金屬層184與導電端子186設置在結構D的相對側。在形成後側金屬層184之後，沿著切割道SL2執行單體化製程，以獲得多個單體化的SoIC元件D2。
在圖13中，SoIC組件D2包括單個支撐基材140及形成在支撐基材140上的後側金屬層184。由於支撐基材140及後側金屬層184可控制SoIC組件D2的翹曲，因此SoIC組件D2的製作良率可增加。
圖14及圖15是示意性示出根據本公開的另一些實施例製作SoIC元件的製程剖視圖。
參照圖8及圖14，在執行圖8所示的製程之後，在結構D上形成導電端子186（例如，導電凸塊），使得導電端子186電連接到被鈍化層176覆蓋的重佈線路層174。
參照圖15，將結構D上下翻轉，並在結構D的支撐基材140的表面上形成結合層180。結合層180可以是準備進行熔融結合的沉積結合層。舉例來說，結合層180的材料包括二氧化矽（SiO2 ）或其他合適的結合材料。在形成結合層180之後，提供用於翹曲控制的支撐基材182，並將其放置在結合層180之上。支撐基材182的厚度可介於從約750微米到約800微米的範圍內。舉例來說，如圖15所示，支撐基材182是半導體晶圓（例如，矽晶圓），並且支撐基材182的厚度是約775微米。在一些實施例中，執行晶圓到晶圓的熔融結合製程，使得在支撐基材182與結合層180之間形成熔融結合介面。舉例來說，用於結合支撐基材182與結合層180的熔融結合製程是在介於從約250攝氏度到約400攝氏度範圍內的溫度下執行的。支撐基材182可直接結合到結合層180。換句話說，在結合層180與支撐基材182之間沒有形成中間層。在圖15未示出的一些替代實施例中，支撐基材是上面形成有介電結合層（例如，SiO2 層）的半導體晶圓（例如，矽晶圓）。此外，形成在支撐基材182與結合層180之間的熔融結合介面可以是Si-SiO2 熔融結合介面、SiO2 -SiO2 熔融結合介面或其他合適的熔融結合介面。
在執行支撐基材182與支撐基材140的結合之後，沿著切割道SL3執行單體化製程，以獲得多個單體化的SoIC元件D3。
在圖15中，SoIC組件D3包括多個堆疊基材140及182，並且省略了後側金屬層。堆疊基材140及182的總體厚度介於從約1500微米到約1600微米的範圍內。由於堆疊基材140及182的厚度足以控制SoIC組件D3的翹曲，因此SoIC組件D3的製作良率可增加。
圖16到圖21是示意性示出根據本公開的一些替代實施例製作SoIC元件的製程剖視圖。
參照圖3及圖16到圖20，在執行圖3所示的製程之後，執行圖16到圖20所示的製程。除了在本實施例中使用的單個支撐基材140’更厚之外，圖16到圖20所示的製程類似於圖4到圖8所示的製程。舉例來說，單個支撐基材140’的厚度介於從約1500微米到約1600微米的範圍內。如圖20所示，在形成重佈線路層174及鈍化層176之後，製作成結構D’。
參照圖21，在結構D’上形成導電端子186（例如，導電凸塊），使得導電端子186電連接到被鈍化層176覆蓋的重佈線路層174。在形成導電端子186之後，沿著切割道SL4執行單體化製程，以獲得多個單體化的SoIC元件D4。
圖22是示意性示出根據本公開一些實施例的另一SoIC元件的剖視圖。
參照圖21及圖22，除了位於單個支撐基材140’的底表面上的後側金屬層184之外，圖22所示的結構類似於圖21所示的結構。在單個支撐基材140’的底表面上形成後側金屬層184之後，沿著切割道SL5執行單體化製程，以獲得多個單體化的SoIC元件D5。
儘管在圖11中示出了包括SoIC組件D1的封裝結構200，但其他類型的SoIC元件（例如，SoIC元件D2、D3、D4或D5）也可封裝在如圖11所示的封裝結構200中。
根據本公開的一些實施例，提供一種包括堆疊基材、第一半導體晶粒、第二半導體晶粒及絕緣包封體的結構。所述第一半導體晶粒設置在所述堆疊基材之上。所述第二半導體晶粒堆疊在所述第一半導體晶粒之上。所述絕緣包封體包括包封所述第一半導體晶粒的第一包封體部分及包封所述第二半導體晶粒的第二包封體部分。在一些實施例中，所述堆疊基材的總體厚度介於從約1500微米到約1600微米的範圍內。在一些實施例中，所述第一包封體部分設置在所述堆疊基材之上，且所述第二包封體部分設置在所述第一包封體部分及所述第一半導體晶粒之上。在一些實施例中，所述第一包封體部分通過位於所述第一半導體晶粒與所述第二半導體晶粒之間的結合層與所述第二包封體部分間隔開。在一些實施例中，所述結構還包括設置在所述堆疊基材之上的後側金屬層，其中所述後側金屬層設置在所述堆疊基材的第一表面之上，所述第一半導體晶粒設置在所述堆疊基材的第二表面之上，且所述第一表面與所述第二表面相對。在一些實施例中，所述後側金屬層的厚度介於從約10微米到約1000微米的範圍內。
根據本公開的一些其他實施例，提供一種包括支撐基材、第一半導體晶粒、第二半導體晶粒、金屬層及絕緣包封體的結構。所述第一半導體晶粒設置在所述支撐基材的第一表面之上。所述第二半導體晶粒設置在所述第一半導體晶粒之上。所述金屬層設置在所述支撐基材的第二表面之上，且所述第一表面與所述第二表面相對。所述絕緣包封體包括包封所述第一半導體晶粒的第一包封體部分及包封所述第二半導體晶粒的第二包封體部分。在一些實施例中，所述支撐基材的厚度介於從約1500微米到約1600微米的範圍內。在一些實施例中，所述第一包封體部分設置在所述支撐基材的所述第一表面上，且所述第二包封體部分設置在所述第一包封體部分及所述第一半導體晶粒之上以在側向上包封所述第二半導體晶粒。在一些實施例中，所述第一包封體部分通過位於所述第一半導體晶粒與所述第二半導體晶粒之間的結合層與所述第二包封體部分間隔開。在一些實施例中，所述金屬層的厚度介於從約10微米到約1000微米的範圍內。在一些實施例中，所述支撐基材包括厚度介於從約1500微米到約1600微米範圍內的單個支撐基材。
根據本公開的一些其他實施例，提供一種包括以下步驟的方法。將第一半導體晶粒結合到載體，其中所述第一半導體晶粒彼此間隔開，且所述第一半導體晶粒的前表面面對所述載體。在所述載體之上形成第一包封體部分，以在側向上包封所述第一半導體晶粒。從所述第一半導體晶粒的所述前表面及所述第一包封體部分移除所述載體。在所述第一半導體晶粒的所述前表面及所述第一包封體部分上形成結合層。將第二半導體晶粒結合到所述結合層，其中所述第二半導體晶粒的前表面面對所述結合層。在所述結合層之上形成第二包封體部分，以在側向上包封所述第二半導體晶粒。在所述載體之上形成所述第一包封體部分以在側向上包封所述第一半導體晶粒之後，將支撐基材結合到所述第一半導體晶粒的後表面及所述第一包封體部分。在一些實施例中，所述支撐基材包括單個支撐基材。在一些實施例中，在從所述第一半導體晶粒的所述前表面及所述第一包封體部分移除所述載體之前，所述支撐基材被結合到所述第一半導體晶粒的所述後表面及所述第一包封體部分。在一些實施例中，所述方法還包括：在所述第二半導體晶粒的後表面及所述第二包封體部分上形成重佈線路層；以及在所述重佈線路層上形成導電端子。在一些實施例中，所述支撐基材包括第一支撐基材及結合到所述第一支撐基材的第二支撐基材。在一些實施例中，在從所述第一半導體晶粒的所述前表面及所述第一包封體部分移除所述載體之前，所述第一支撐基材被結合到所述第一半導體晶粒的所述後表面及所述第一包封體部分。在一些實施例中，在所述第二半導體晶粒及所述第二包封體部分上形成所述重佈線路層之後，所述第二支撐基材被結合到所述第一支撐基材；且在所述重佈線路層上形成所述導電端子之前，所述第二支撐基材被結合到所述第一半導體晶粒的所述後表面及所述第一包封體部分。在一些實施例中，在所述重佈線路層上形成所述導電端子之後，所述第二支撐基材被結合到所述第一支撐基材。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解，其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
100、100’:半導體晶粒 100a:半導體晶粒的主動表面 100b、100b’:半導體晶粒的後表面 102:結合部分 110:第一包封體部分 120:對準標記 130:結合層 140、140’:支撐基材 150:結合結構 150a:介電層 150b:導體 160、160’:半導體晶粒 162、162’:半導體基材 164:內連結構 166:結合結構 166a:介電層 166b:導體 168:半導體穿孔 170:第二包封體部分 172:絕緣體穿孔（TIV） 174:重佈線路層 176:鈍化層 180:結合層 182:支撐基材 184:後側金屬層 186:導電端子 200:封裝結構 202:中介層 204:記憶體堆疊 206:底部填充材料 208:絕緣包封體 210:電路基材 212:導電端子 220:導電端子 230:底部填充材料 B:結合層 C1、C2:半導體載體 D、D’:結構 D1、D2、D3、D4、D5:SoIC組件 SL1、SL2、SL3、SL4、SL5:切割道
圖1到圖10是示意性示出根據本公開一些實施例製作SoIC元件的製程剖視圖。 圖11是示意性示出根據本公開一些替代實施例的封裝結構的剖視圖。 圖12及圖13是示意性示出根據本公開的其他實施例製作SoIC元件的製程剖視圖。 圖14及圖15是示意性示出根據本公開的另一些實施例製作SoIC元件的製程剖視圖。 圖16到圖21是示意性示出根據本公開的一些替代實施例製作SoIC元件的製程剖視圖。 圖22是示意性示出根據本公開一些實施例的另一SoIC元件的剖視圖。
140:支撐基材
180:結合層
182:支撐基材
184:後側金屬層
C2:半導體載體
D:結構

Claims (1)

  1. 一種封裝結構，包括： 堆疊基材； 第一半導體晶粒，設置在所述堆疊基材之上； 第二半導體晶粒，堆疊在所述第一半導體晶粒之上；以及 絕緣包封體，包括包封所述第一半導體晶粒的第一包封體部分及包封所述第二半導體晶粒的第二包封體部分。
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CN114361025A (zh) * 2022-03-21 2022-04-15 宁波芯健半导体有限公司 一种GaN超薄芯片扇出型封装结构及封装方法
US11610878B1 (en) 2021-09-02 2023-03-21 Nanya Technology Corporation Semiconductor device with stacked chips and method for fabricating the same
US11804445B2 (en) 2021-04-29 2023-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming chip package structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11804445B2 (en) 2021-04-29 2023-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming chip package structure
TWI825572B (zh) * 2021-04-29 2023-12-11 台灣積體電路製造股份有限公司 晶片封裝結構及其形成方法
US11610878B1 (en) 2021-09-02 2023-03-21 Nanya Technology Corporation Semiconductor device with stacked chips and method for fabricating the same
TWI809607B (zh) * 2021-09-02 2023-07-21 南亞科技股份有限公司 具有堆疊晶片的半導體元件及其製備方法
CN114361025A (zh) * 2022-03-21 2022-04-15 宁波芯健半导体有限公司 一种GaN超薄芯片扇出型封装结构及封装方法

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